Interconnect/Via CONCORDIA VLSI DESIGN LAB

Transcription

1 Interconnect/Via 1

2 Delay of Devices and Interconnect 2

3 Reduction of the feature size Increase in the influence of the interconnect delay on system performance Skew The difference in the arrival times of the clock signal to all registers in a synchronous digital system 3

4 An Example, The Clock Distribution Network (CDN) A set of interconnections that delivers reliably a time reference, clock signal, to every register element in a synchronous digital system. PowerPC microprocessor 32,000 master/slave latch 4

5 Power Consumption &Routing and system complexity P= CV 2 f Short-Circuit Leakage 6% 6% Global Interconnect 8% 11% I/O 12% 3% Clock Memory 54% Logic and Local Routing 5

6 Delay model of the CDN, Elmore Delay model er 0 It takes into account the interconnect resistance and capacitance and the capacitance of the registers ec 0/ /2 ec 0/ /2 s 0 r 1 s 1 r 2 s 1 s 2 s 0 s 2 r 3 r 1 r 2 r 3 r 4 r 4 6

7 Example: Routing delay problems The Clock Skew The difference between time arrivals of the clock signal to all the registers in a synchronous digital system In R i T i T PD(min) /T PD(max) R j T j Out S(ij) = T i - T j Two conditions: S(ij) T HOLDj - T PD(min) Race Conditions Permissible range Clock Period Limitations S(ij) T clk - T PD(max) S(ij) min S(ij) max 7

8 Minimizing the effects of delay, The H_Tree If it is possible to divide the set of registers R into two symmetric sets recursively and alternatively by vertical and horizontal lines, then the set R can be connected by an H-tree 8

9 Interconnect Length 9

10 Interconnect/Via 10

11 Cross Section View of Capacitances in interconnect Units are in Angstrom, 1A=0.1nm 11

12 Interconnect Interconnects in chips are routed in several layers horizontally and vertically and used according to their application 12

13 Small line length: transistor speed governs the circuit speed. Medium line length Transistor output resistance and line capacitance govern the circuit speed. Long line length, line resistance and line capacitance govern the circuit speed. Cooling the room temperature to 77K reduces the resistivity by an order of magnitude. At higher frequencies, Ghz and above the skin effect has to be taken into account.

14 Interconnect usage Local interconnect are used for short distances on the chip. Mainly to connect the device Drain, source, gates or immediate devices. Semi_global interconnect is used to connect gates FFs other small devices within a block of the hierarchy. Global wiring is used for long interconnect such as Clock signal or other control signals. Separating the interconnect wires and the devices from each other are the dielectric material. The dielectric material gets thicker as move higher in the hierarchy of the wire placement

15 Parallel and fringing Capacitance 15

16 Fringing Capacitance ance.html

17 Fringing Capacitance T is the thickness of wire H is the distance of wire to substrate. C F r * 2H T ln(1 (1 1 )) T H T 4H 17

18 Cross Talk 18

19 Cross talk Is a disturbance caused by the electric or magnetic fields of one telecommunication signal affecting a signal in an adjacent circuit. Two effects: increased capacitance on the driver. Introduction of unwanted signal or noise from one line to the other. Design tips: Methods to reduce cross talk, Increase inter_wire spacing. Place Vdd or ground wires between signal lines.

20 Fringing/ Parallel Plate Capacitance of Interconnect 20

21 Modeling Interconnect LUMPED MODEL T-MODEL -MODEL 2T-MODEL 2π -MODEL 21

22 Modeling of Interconnect 22

23 Delay of Interconnect delay rcl 2 2 delay rc N( N 1) 2 Capacitance = C/unit area * L (length) * W (width) = C Resistance = R/ * number of squares = R 23

24 Delay comparison Voltage Range Lumped RC Distributed RC 0 50% 0.69RC 0.38RC 0 63% RC 0.5RC 10 90% 2.2RC 0.9RC 24

25 RC delay with distributed parameters: More accurate than lumped RC model More difficult to solve for large N Need full-scale SPICE simulation

26 Example A signal is propagated on a 6mm length metal 1 (M1) interconnect of CMOSIS5 Process, using minimum wire width. Calculate the delay and comment on methods for reducing this delay. 6mm Now the resistance and capacitance of CMOSIS5 are given as (from the manual): r = 0.07 W / c = 46 af/µm 2, c = 46*1 exp -18, (a = 1 exp -18), 26

27 Rent s rule, relates number of i/o pins T, to the number of gates N in a random logic network: T T=kN**p Where: k = average I/O per gate P= Rent s exponent. It reflects wiring complexity, p=1 is the highest.

28 What is the maximum size of silicon chip? Power dissipation Packaging Number of pins Technology The interconnect used A chip 0.16 R R C o int C o int C ln( INT Area 2 C packaging o C l ) 28

29 Thank you! 29

30 Inductances For die wires L 4h ln( ) 2 d h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material 30

31 Inductance For on-chip, L 8h w ln( ) 2 w 4h h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material 31

32 Ground Bounce and Vdd Sag examples from Alterahttp:// 32

33 Example on V DD Bounce Determine the values of due to inductive and resistive losses x, y when the output driver sources 10mA in 1.5ns in the following circuit. Assume inductance of 13.9nH/mm. 33

34 Board Vdd Circuit Vdd Board Gnd Circuit Gnd 34

35 Example on Power lines What will be the power line width if you drive a 10pF load at 1GHz Assume Vdd=3.5V. 35

36 Example on Charge Sharing Calculate the drop in voltage for 64 read lines each consisting of 0.1pF capacitances. Assume bus capacitance to be 10pF. 36

37 Thank you! 37