ECE 497 JS Lecture - 22 Timing & Signaling

Transcription

1 ECE 497 JS Lecture - 22 Timing & Signaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1

2 Announcements - Signaling Techniques (4/27) - Signaling - EMI/EMC Overview (4/29) - Q & A (5/4) - Microstrip S-parameter data uploaded 2

3 Model for On-Chip Power Distribution V P R P R P R V P R P R P R 1 V 1 V 1 V P 1 V 1 V 1 GND I 1 I 2 I 3 I 4 I 5 R P R P R P R P R P R P I N R P = Lr P w 2NW P A P = LW P 2Nk P P N/2 N/2 2 ij pk L r P IR = pk P P = 2 i= 1 i= 1 4NkP V ij A R V IR J r x = = J r L LP /2 pk w pk w dx 0 kp 8kP 2 P 3

4 Bypass Capacitor Network Design (D&P 5-13) Chip mm in area with 1M Gates. Each has a 200 ff load (40 ff gate, 160 ff wire) and switches on average every 1/3 cycle of a 100 MHz clock. Find total power dissipation of chip. Peak current to average current ratio is 4:1, how many metal layers are needed to distribute power so the overall supply fluctuation of a 2.5V supply in ± 250 mv? From: K dv 1 Iavg = C = 1 M 200 ff 2.5 V 100 MHz= A dt J = I /(15 mm) = A/ mm P avg avg J = 4J = A/ mm V peak IR avg 2 rw L J peak 2 ( ) = = = V K P J r L r L J = = 2 2 peak W P W peak KP 8K 8 V P IR The number of metal layers is However, if we think that the supply fluctuation is between the Gnd and V dd, each layer has less than ± 125 mv. Thus for each Gnd and V dd ( ) 2 2 rw L J peak = = = V

5 (Dally & Poulton 6-3) 1k 1.2 µm 3 mm 0.6 µm line a Cc Co line b Cc=90 ff Co=300 ff line c Co The resistance of the wires are much smaller than the 1kΩ of the drivers and thus can be ignored Worst case condition which will cause maximum delay is when the effective capacitance is maximum. If the 2 side aggressor lines transition in the opposite direction of the main driver on the victim line, this will create the most amount of capacitance (Miller effect) 5

6 Example (Dally & Poulton 6-5) Full-swing (3.3V) CMOS signal with a fast 500 ps rise time next to a low-swing (300 mv) signal for a 10 cm run of microstrip line. The lines are each 8 mils wide spaced 6 mils above a ground plane and spaced 8 mils from one another (see D&P Table 6-3).Is the noise induced in the low-swing line a concern? 3.3V - + A Aggressor B V Victim From table 6-3, we get k fx =-0.047, k rx =0.058 Far end crosstalk C=C+C m =88+6.4=94.4 pf/m L = 355 nh/m 1 1 v= = = m/s LC 94.4 pf / m 355 nh / m t x 10cm = = ns

7 Example (Dally & Poulton 6-5) In worst case, near- and far-end crosstalk will be added add absolute values Vaggressor V = k t + V k k xtalk fx x aggressor rx r t 3.3 = ns = ps V 0.37 V is bigger than 300 mv/2=150 mv This will cause problem to the system Victim line also produces crosstalk on the agressor. However, only second order effect is considered. 7

8 Transmission Systems Vdd + - R o 50W, 6 ns - V N + Full-swing CMOS transmission system 3.3 ma 50W, 6 ns R + T - Low-swing current-mode transmission system 8

9 Transmission Systems CMOS LSC Signaling Voltage mode: 0=GND, Current mode: 0=-3.3 ma 1=V dd 1=+3.3 ma Reference Power supply: V r ~V dd /2 Self-centered: I r =0 ma Termination Series terminated in output Parallel-terminated at receiver impedance of driver with R T within 10% of Z o Signal energy 1.3 nj 22 pj Power dissipation 130 mw 11mW Noise immunity 1.2:1 actual:required signal 3.6:1 swing (with LSC receiver) Delay 18 ns 6 ns 9

10 Transmission Systems CMOS (V) LSC (mv) V OH V OL V IH V IL V MH V ML CMOS (mv) LSC (mv) Receiver sensitivity Receiver offset Power supply noise Total noise (swing-independent) CMOS (%) (%) LSC Self-induced power supply noise (K in ) 10 0 Crosstalk from other signals (K xt ) Reflections of the same signal large(>5) 5 from previous clock cycles (K r ) Transmitter offset (K to ) Total proportional noise fraction (K N ) >

11 CMOS vs LSC Basic CMOS system is most commonly used and yet is far from optimal Large energy signal is used where it is not needed Transmitted signal not isolated from supply noise Receiver uses reference that changes significantly with process variations 11

12 Signaling Modes for Transmission Lines V T R O Z O V R V r + - R T Z GT Z RT V N Z RR Z GR TGND RGND - Signal return impedances Z RT and Z RR - Coupling to local power supply Z GT and Z GR - Introduce noise V N - Sections can be separated if TL is terminated into match impedance 12

13 Transmitter Signaling Parameters Output impedance, R o Coupling between signal and power supply Polarity of signal Amplitude of signal 13

14 Current- & Voltage-Mode Transmission Current-Mode Transmission Z O Voltage-Mode Transmission Z O I T V T Z GT TGND Z RT TGND Z RT Provides isolation of both the signal and current return from the local power supplies Makes a difference in: - Signal return crosstalk - Single power supply noise - Large ZGT 14

15 Nonideal Return Paths A nonideal return path will appear as an inductive discontinuity A nonideal return path will slow the edge rate by filtering out highfrequency components If the current divergence path is long enough, a nonideal return path will cause signal integrity problems at the receiver Nonideal return paths will increase current loop area and exacerbate EMI Nonideal return paths may significantly increase the coupling coefficient between signals 15

16 Signal Return Crosstalk Return crosstalk can be reduced with rise-time control As rise times get faster, every signal requires its own return might as well use differential signaling With voltage-mode signaling, the transmitter signal return crosstalk is a maximum High output impedance offers advantage and reduces transmitter return crosstalk For current-mode signaling, this form of crosstalk is completely eliminated 16

17 Transmitter Signal Return Crosstalk V T1 V T2 V TN Z X ZRT ( RO + ZO ) ( ) RO + ZO = ZRT P = N 1 N 1 Z + R + Z RT O O Z RT R O R O R O + Z I I I X RT X = T1 = T1 RO + ZO ( N 1) ZRT + RO + ZO Z Z O Z O Z O V L - V I Z V Z N Z + R + Z RT X = X O = T1 ( 1) RT O O K XRT ( ) ( 1) ( ) ( N 1) V N 1 ZRT N 1 Z X = = V N Z + R + Z R + Z T1 RT O O O O RT - With voltage-mode signaling, R o =0, the transmitter signal return crosstalk is a maximum. For curr ent-mode signaling, R o is infinite and this form of crosstalk is eliminated 17

18 Application: Return Signal Optimization Voltage-mode signaling with Z o =50 Ω and rise time t r =2 ns and Z RT dominated by 5 nh inductance. Approximate Z RT =L/t r = 2.5 Ω Want k XRT = 0.1 Solving for N shows that we will need 1 return for every 3 signal traces to meet the spec. If the rise time is decreased to 1 ns, we will need 1 return for every 2 signal line to keep the same spec If the rise time is lower than 1 ns, we will need 1 return for every signal might as well use differential signaling 18

19 Application: (D&P 7-2) Line impedance: Z o = 50 Ω Source Resistance: R o = 50 Ω Lead Inductance: L = 5 nh Pin count: P = 32 Data rate: TBR = 8GB/s S+N=P S*B=TBR ( N ) Z K XRT R + Z O 1 RT O B: Bit rate per signal pin TBR: Total bit rate S: Number of signal pins N: Number of return pins Z RT is due to the lead inductance Z RT Z RT /N since there are N ground pins Need to determine S and N 19

20 8-Bit Connector Pin-Out Options G S S S S S S S S P inferior G S S P S S G S S P S S G improved G S P S G S P S G S P S G S P S G More improved G P S G P S G P S G P S G P S G P S G P S G P S G P Optimal 20

21 Connector Design Minimize physical length of connector pins. Maximize the ratio of power and ground pins to the signal pins. If possible these ratios should be < 1. Place each signal pin as close as possible to a current return pin. Place power pins adjacent to ground pins. 21

22 Receiver Signal Return Crosstalk Z RR 2V i1 Z O 2V i2 Z O 2V in Z O K XRR ( N 1) ( N 1) ZRR = ( N 1) Z + 2Z 2Z RR O O Z RR + R T R T R T V R - - All N terminators return their current through ZRR (shared impedance) - No crosstalk advantage to current-mode signaling - TL is like a matched source 22

23 Ringback and Rise Time Control (waveform into reference load) (waveform at receiver) Vih Threshold Vil Maximum flight time measured at last crossing of Vih or Vil Time Violation into threshold region Detrimental even if threshold is not crossed Can exacerbate ISI Can be aggravated by nonlinear (time varying) terminations Can increase skew between signals 23

24 Signaling Over Lumped RLC Interconnect R O L P + V T (t) i C L V R - 1 R ω = LC 2L RT V () t = 1 exp cos( ωt) R 2L 1 L Q = π R C 2 Q: high Q: medium Q: low 24

25 Example (Dally & Poulton 7-4) Z O R O L R R T - V N + C N Z O =R T =50Ω R O =1 kω C N =5 pf L R =5 nh V N =500 mv Determine the amount of supply noise V N that appears across R T as a function of frequency. How much signal swing is required to keep the power-supply noise less than 10% of the signal swing across the spectrum from DC to 1GHz 25

26 Example (7-4) Solution C N V N + - L R R T Z O + V RN - V RN = V ( Z jω L N O R) ( )( ) 1 2Z jωl + 2Z + jωl jωc O R O R = V 4π Z L Cf 8π N O R 2 2 Z LCf + Z + π fl O R O R f = f j f We want 0.1 V s > V RN VS > 10V RN 26

27 Required Voltage Swing V S (Volts) X 10 8 f (Hz) 27

28 Voltage Reference Uncertainty Vref + uncertainty V ih Threshold Threshold region V il Vref - uncertainty Time Major Contributors Power supply effects (SSN, ground bounce, rail collapse) Noise from IC Receiver transistor mismatches Return path discontinuities Coupling to reference voltage circuitry 28

29 Efficient Bus Design Methodology Spreadsheets & metrics Signal categories Topology options Sensitivity analysis Routing guidelines Reference design Buffer guidelines Simulation of design Fix Pass Design check Fail Tapeout 29

30 Bus System Variables I/O capacitance Trace length, velocity, and impedance Interlayer impedance variations Buffer strengths and edge rates Termination values Receiver setup and hold times Interconnect skew specifications Package, daughtercard, and parameters 30