2.5D & 3D Package Signal Integrity A Paradigm Shift

Transcription

1 2.5D & 3D Package Signal Integrity A Paradigm Shift Nozad Karim Technology & Platform Development November, 2011 Enabling a Microelectronic World

2 Content Traditional package signal integrity vs. 2.5D/3D package signal integrity TSV equivalent circuit representation Power saving System level electrical analysis System configuration Pre-design stage Simulation Summary

3 Traditional Package Signal integrity vs. 2.5D/3D Package Signal Integrity Electric circuit made up of signal path and return path Standard 2D Package (signal path) 2.5D & 3D Package signal path

4 Quasi 3D Package Core logic is isolated from I/O interconnects I/O region Core region

5 True 3D Package Core logic is not isolated from I/O interconnects Die 1 Die 2 Die 3 Die 4 Die 5 Die 6 Die 7 Die 8 Die 9 I/O & Core regions TSV Electromagnetic radiations

6 Current Distribution for multi TSV Single Interconnect i Current is not uniformly distributed in TSV TSV pad-a TSV Pad-B i

7 1 St order Electrical Characteristic Model Silicon interposer Memory Cube CPU Memory Cube Memory Cube CPU Memory Cube De-Cap Organic substrate Cu Si SiO2 Insulator

8 TSV Equivalent SPICE Circuit Representation Series elements, resistance and inductance, plus shunt elements, capacitance and conductance Cu Si SiO2 Insulator T Circuit or π Circuit

9 TSV Equivalent Resistance Representation The first order model for the resistance is always the resistance of a cylinder of given length, diameter and material Resistance (mω) RAC RDC LTV length (um) for n:m diameter:length ratio l TSV is the TSV length, R TSV is the radius of the TSV, P cu resistivity of copper, δ skin effect

10 TSV Equivalent Capacitance Model The equivalent TSV capacitance is the most important as well as the most difficult parameter to model having a thin layer of silicon oxide deposited between the copper of the barrel and the silicon itself TSV capacitance is the series combination of silicon oxide capacitance and depletion capacitance metal Si SiO metal Cox Cdep Cox Cdep CTSV = Cox Cdep Cox + Cdep metal

11 TSV Equivalent Capacitance Model-2 ε ox is the electric permittivity of the silicon oxide, l TSV is the TSV length, R ox is the radius of the silicon oxide around the TSV, R metal is the radius of the TSV ε Si is the electric permittivity of the silicon, R max is the radius of the depletion region around the oxide. oxide and depletion capacitances as a function of the TSV length

12 The Propagation Path in TSV The signal time delay can be estimated using RC plot, at frequency region where the skin effect is not yet developed Normalized Value R RC C LTV length (um) for n:m diameter:length Ratio The effects of TSV in the propagation path from the source to the load can be modeled by inserting various T or π circuits to model the entire interconnects.

13 TSV Equivalent Inductor Model Inductance is less complex than the capacitance model (*) 1:10 ratio 1:5 ratio Inductor (ph) LTV length (um) for n:m diameter:length Ratio (*) IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010, Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional Ics. Guruprasad Katti, Michele Stucchi, Kristin De Meyer, and Wim Dehaene, Senior Member, IEEE

14 Silicon Substrate and I/O Power Reductions Average total system power reductions 20% to 40% Reduced I/O parasitic Removal of ASIC (FPGA) & Memory packages (bare die only) Short distance interconnects High resistance of lossy 1um-2um trace acts as damp resistor to reduce signal reflections Elimination of termination resistors on Chip P (power) = n * T * C * f * V n = number of signals switching T = Average toggle rate per clock cycle C = Total capacitance of the signal f = Clock frequency V = Voltage

15 2.5D/3D System Level Electrical Analysis I The complete die-to-die signal path of an interface Power & signals distributions, along with electromagnetic radiation and susceptibility Silicon interposer Signal paths can cross multiple levels of physical boundaries: Memory Cube CPU Memory Cube Chip, TSV, ubump, silicon interposer, organic/ceramic substrate, de-caps, package and system loads (PCB,& connectors) Memory Cube CPU Memory Cube Accurate IO model for low power I/O buffers Multiphysics approach Impact of the thermal and mechanical variations on the electrical characteristic of chip-to-chip interconnect De-Cap Organic substrate

16 2.5D/3D System Level Electrical Analysis II Pre-Design Stage Library Development Chip, I/O, TSV, ubump, interposer, package, stackup, etc. System configuration Different Topologies Component placements Estimating target parameters Interconnect delay, Set up and hold timing, etc. Simulation setup Frequency domain Time domain

17 2.5D/3D System Level Electrical Analysis III Electrical Simulations Accurate assessment of high speed and wide band data bus Time domain and frequency domain analysis for chip, package, and PCB models Efficient full-wave extraction of on-chip and the system Concurrent simulation of all major effects reflections and ISI crosstalk, simultaneous switching noise Detail Eye diagrams with timing reference Power grid concurrent simulation of all major effects to determine Setup and Hold margins Back annotate packaging analysis data to the silicon design tools to verify 3D interconnect impact on chip

18 Summary Traditional Package Signal integrity is not efficient for 2.5D/3D package Signal Integrity Carefully design consideration for TSV location on a chip Increase inter & intra chip coupling and noise sharing Concurrent simulation of all major effects Reflections and ISI crosstalk, simultaneous switching noise Detail Eye diagrams with timing reference Silicon and package design integration methodology to run system level analysis Silicon IP supplier must verify their libraries with 3D structure package Need for 3D package PDK