EE241 - Spring 2004 Advanced Digital Integrated Circuits. Announcements. Borivoje Nikolic. Lecture 15 Low-Power Design: Supply Voltage Scaling

Transcription

1 EE241 - Spring 2004 Advanced Digital Integrated Circuits Borivoje Nikolic Lecture 15 Low-Power Design: Supply Voltage Scaling Announcements Homework #2 due today Midterm project reports due next Thursday 2 1

2 Class Material Last lecture Introduction to power dissipation in CMOS Today s lecture Supply voltage scaling 3 Reducing active power Downsizing transistors (C L ) Slows down logic Lowering the supply voltage (V DD ) Slows down logic Reducing swing slows down the succeeding stage Pd y n Reducing frequency (f) E Does not reduce energy Reducing switching activity (a) Logic restructuring Reducing glitching Balancing logic ~ α C ~ α C L L V V swing swing V V DD DD f 4 2

3 Reducing Active Power Downsizing, lowering the supply on the critical path will lower the operating frequency Downsize non-critical paths Narrows down the path delay distribution Increases impact of variations Path count Original delay distribution Target delay Delay 5 Power-Performance Optimization Energy/op Unoptimized design E max E min D min D max Delay Achieve the highest performance under the power cap 6 3

4 Power-Performance Optimization E max E min Energy/op D min Unoptimized design Var1 D max Design optimization curves Delay Achieve the highest performance under the power cap 7 Power-Performance Optimization E max E min Energy/op D min Unoptimized design Var2 Var1 D max Design optimization curves Delay Achieve the highest performance under the power cap 8 4

5 Power-Performance Optimization E max E min Energy/op D min Unoptimized design Var2 Var1 Var1 + Var2 D max Design optimization curves Delay How far away are we from the optimal solution? 9 Power-Performance Optimization E max E min Energy/op Global D min Unoptimized design Var2 Var1 Var1 + Var2 D max Design optimization curves Delay Global optimum best performance 10 5

6 Power-Performance Optimization Energy/op Unoptimized design E max E min D min D max Delay Maximize throughput for given energy or Minimize energy for given throughput 11 Power-Performance Optimization There are many sets of parameters to adjust Tuning variables Circuit (sizing, supply, threshold) Logic style (std. cells, custom, ) Block topology (adder: CLA, CSA, ) Micro-architecture (parallel, pipelined) Energy/op topology A topology B Delay 12 6

7 Power-Performance Optimization There are many sets of parameters to adjust Tuning variables Circuit (sizing, supply, threshold) Logic style (std. cells, custom, ) Block topology (adder: CLA, CSA, ) Micro-architecture (parallel, pipelined) Energy/op topology A topology B Delay Globally optimal power-performance curve for a given function 13 Multi-Level Approach Energy minimization subject to delay constraint Optimal trade-off between energy and area Architecture Micro-Architecture Circuit (Logic & s) Energy-Area (Cost) Performance Energy-Performance Energy-Delay 14 7

8 Multi-Level Optimization E-D tradeoff par, t-mux Area E-D tradeoff Vdd, Vth, W E&A-Perf Architecture Micro Arch. Circuit parallel time-mux E-Perf parallel pipeline time-mux E-D W Vth Vdd # of bits throughput algorithm delay cct topology 15 6 Sizing, Supply, Threshold Optimization Transistor sizing can yield large power savings with small delay penalties Gate sizing Beta-ratio adjustments Stack resizing IBM EinsTuner Supply voltage affects both active and leakage energy Threshold voltage affects primarily the leakage 16 8

9 Supply Voltage Scaling How to maintain throughput under reduced supply? Introducing more parallelism/pipelining Area increase cost up Cost/power tradeoff Multiple voltage domains Separate supply voltages for different blocks Lower VDD for slower blocks Cost of DC-DC converters Dynamic voltage scaling with variable throughput Reducing V TH to improve speed Leakage issues 17 Reducing V dd NORMALIZED POWER-DELAY PRODUCT quadratic dependence 51 stage ring oscillator 8-bit adder Vdd (volts) 2 P x t d = E t = C L * V dd E (Vdd=2) (C L ) * (2) 2 = E (C L ) * (5) 2 (Vdd=5) E (Vdd=2) 0.16 E (Vdd =5) Strong function of voltage (V 2 dependence). Relatively independent of logic function and style. Power Delay Product Improves with lowering V DD. 18 9

10 Lower V dd Increases Delay NORMALIZED DELAY multiplier clock generator ring oscillator adder adder (SPICE) 2.0µm technology microcoded DSP chip V dd (volts) T d = Td(Vdd=5) C L * V dd I I ~ (V dd - V t ) 2 T d(vdd=2) = (2) * (5-0.7) 2 4 (5) * (2-0.7) 2 Relatively independent of logic function and style. 19 Power and Delay 20 10

11 Energy-Efficiency Metric: Max Throughput Process Queue from [Burd95] (HICSS 95) 21 Power-Delay vs. Energy-Delay Product 22 11

12 Power = a Power [W/gate] Trade-off Between Power and Delay x f 0.5 C V DD [V] V 2 DD I 0-10 VTH s V V TH [V] DD Delay [ps] nm node, FO3 INV Delay Equi-delay V DD [V] C ( V - V ) 1. 3 DD V DD TH V TH [V] 23 Two Types of Processing Fixed-rate processing (e.g. signal processing for multimedia or communications) Stream-based computation No advantage in obtaining throughput in excess of the real-time constraint Variable-rate or burst-mode computation (e.g. general purpose computation) Mostly idle (or low-load) with bursts of computation Faster is better 24 12

13 Architecture Trade-off for Fixed-rate Processing Reference Datapath 25 Parallel Datapath 26 13

14 Pipelined Datapath 27 A Simple Datapath: Summary 28 14

15 Multiple Supply Voltages Block-level supply assignment Higher throughput/lower latency functions are implemented in higher V DD Slower functions are implemented with lower V DD Voltage islands as called by IBM Separate supply grids, level conversion performed at block boundaries Multiple supplies inside a block Non-critical paths moved to lower supply voltage Level conversion within the block Physical design challenging 29 Multiple Supplies in a Block Conventional Design CVS Structure Level-Shifting F/F Critical Path Critical Path Lower V DD portion is shaded M.Takahashi, ISSCC 98. Clustered voltage scaling 30 15

16 Multiple Supplies in a Block CVS Layout: U s a m i Three V DD s Power Reduction Ratio V V2 3 (V) V 3 (V) From Kuroda V 2 (V) V1 (V) V 2 (V) V 1 = 1.5V, V TH = 0.3V, p(t):lambda 32 16

17 Supply Voltage Ratio Power Dissipation Ratio Optimum Numbers of Supplies { V 1, V 2 } V 2 /V 1 P 2 /P V 1 (V) { V 1, V 2, V 3 } V 2 /V 1 V 3 /V 1 P 3 /P V 1 (V) { V 1, V 2, V 3, V 4 } V 2 /V 1 V 3 /V 1 V 4 /V 1 P 4 /P V 1 (V) The more V DD s, the less power, but the effect will be saturated. Power reduction effect will be decreased as V DD s are scaled. Optimum V 2 /V 1 is around 0.7. [Hamada, CICC 01] 33 Multiple Supply Voltages Two supply voltages per block are optimal Optimal ratio between the supply voltages is 0.7 Level conversion is performed on the voltage boundary, using a level-converting flip-flop (LC) An option is to use an asynchronous level converter More sensitive to coupling and supply noise 34 17

18 Level-Converting Flip-Flop V H V L CLK CK CK Q D CK CK CK CK M 1 M 2 CK 35 Dual-Supply-Datapath: Layout Issue : V DDH circuit : V DDL circuit : S i g n a l f l o w V DDL R o w V DDH R o w (empty) (a) Dedicated row (Conventional) V DDL R o w V DDH R o w C o m p l e x interconnections (b) Possible layout reduction (Conventional) (c) Shared-well layout A shared-well technique is appropriate for random placement of cells 36 18

19 Standard-Cell Dual-Supply-Voltage N- well isolation V DDH V DDL V DDH V DDL i1 o 1 i2 o 2 V SS V SS V DDH circuit V DDL circuit (a) circuit schematic V DDH circuit (b) layout V DDL circuit A V DDH circuit is assigned only to a critical path A V DDL circuit is used in a non-critical path and for driving a large capacitive load 37 V DDH V DDL Shared-Well Dual-Supply-Voltage i1 o 1 i2 o 2 V DDH V DDL Shared N-well V SS V DDH circuit V DDL circuit V SS V DDH circuit (a) circuit schematic (b) layout Both circuits can be placed in the same N-well Cell layout becomes complex An intrinsic negative back-biasing of PMOS degrades speed Shimazaki, ISSCC 03 V DDL circuit 38 19

20 Shared-Well : Cell Layout N- well contacts Connected to V DDL Local interconnect V DDH V DDL V SS Two power rails Resistance of power rails c a r e f u l d e s i g n Cell height (18 tracks) usually set by architecture or p e r f o r m a n c e Local interconnect layer helps layout Layout example of V DDL cell 39 ALU Block Diagram clock gen. INV2 9 : 1 MUX 9 : 1 MUX a i n 0 ain 5 : 1 MUX 2 : 1 MUX : V DDH circuit : V DDL circuit bin clk gp gen. carry gen. p a r t i a l s u m logical unit carry s u m s e l. s0/s1 s u m INV p F s u m b (long loop-back bus) 40 20

21 s u m Low Swing Bus & Level Converter V DDL INV1 s u m b V DDL INV2 pc s e l (V DDH ) V DDH k e e p e r V DDH a i n 0 domino level converter (9:1 MUX) Delay of INV1 does not increase INV2 is placed near 9:1 MUX to increase noise immunity Level conversion is done by a domino 9:1 MUX 41 Energy [pj] Measured Results: Energy & Delay GHz R o o m t e m p. V DDL =1.4V Energy: % Delay :+2.8% V DDL =1.2V Energy: % Delay :+8.3% T CYCLE [ns] Single -s u p p l y Shared well (V DDH = 1. 8 V ) The dual-supply technique expands the power-delay optimization space 42 21

22 Adaptive Supply Voltages 43 Variable Algorithmic Workload 44 22

23 Processors for Portable Devices Performance (MIPS) Dynamic Voltage Scaling PDAs Pocket-PCs Notebook Computers Processor Energy (Watt*sec) Eliminate performance «energy trade-off. Burd ISSCC Normalized power P ƒv Dynamic Power Reduction Through Software-Hardware Cooperation Super-linear Required speed ƒ S. Lee et al, DAC, June 2000 Required speed Software Controller Processor Clock & V DD Hardware If you don t need to hustle, relax and save power

24 Typical MPEG IDCT Histogram 47 Processor Usage Model Desired Throughput Compute-intensive and low-latency processes Maximum Processor Speed System Idle Background and high-latency processes System Optimizations: Maximize Peak Throughput Minimize Average Energy/operation time Burd ISSCC

25 Common Design Approaches (Fixed VDD) Delivered Throughput Compute ASAP: Always high throughput Clock Frequency Reduction: f CLK Reduced Excess throughput time Energy/operation remains unchanged while throughput scaled down with f CLK time 49 Scale V DD with Clock Frequency Energy/operation ~10x Energy Reduction 1.1V Constant supply voltage Reduce V DD, slow circuits down Throughput ( f CLK ) 3.3V Burd ISSCC