Incorporating Variability into Design
|
|
- Reynold Hopkins
- 5 years ago
- Views:
Transcription
1 Incorporating Variability into Design Jim Farrell, AMD Designing Robust Digital Circuits Workshop UC Berkeley 28 July 2006
2 Outline Motivation Hierarchy of Design tradeoffs Design Infrastructure for variability Circuits techniques for variability Architectural techniques for variability Conclusion 2
3 Motivation Beyond basic yield, Variation costs frequency, which reduces revenue. Example of how we might partition a lot into frequency bins: Top Bin Fmax Mid Bin Bottom Bin Sidd 3
4 How Variability affects Circuit Delay Which components are more affected by variations, LARGE gates or SMALL gates? Example: Inverter Chain with different inverter sizes Delay Variations (%) Large Gates vs. Small Gates Gate Width (um) Gate Width (um) Variation (%)
5 Impact of Variation on Leakage Power -3 sigma Nom Le +3 sigma leakage device distribution leakage distribution Relative Speed Part Frequency P C TOT α F Vdd 2 + N TOT α F Vdd I CO + N ON I LEAK Vdd Selective use of High Vt and longer channel devices shifts leakage profile to lower values But, poly bias is limited in CPP From Naffziger, 2006 VLSI Ckt Symp Switching Power Crossover Power Leakage Power 5
6 Limits to poly biasing for leakage variation reduction Contacted poly pitch includes: PC width CA width Spacer and overlay tolerances CA Competing requirements for: CA resistance CA-PC capacitance CA-PC breakdown voltage And, maximum poly bias for leakage PC RX 6
7 Infrastructure to Reduce Variability This is the Boring stuff Classic engineering isolation of problem areas Is this a problem that should addressed? Simulation, data and judgment Critical work at the beginning of the project Examples: Contact vs Salicide resistance Feedback sizing in M/S flops 7
8 Infrastructure: Transistor R,C model Question do I care about the variation in contact or salicide resistance? Rc Rc Rc Rdiff Rdiff Rdiff Rdiff Rc Rc Rc 8
9 Comparing Source vs Contact effect on transistor delay. Delay Diff Normalized (%) N Width Contact resistance dominates over source resistance Conclusion: Concentrate on minimizing variation impact of contacts Rc(min)-Rc(0) Rc(nom)-Rc(0) Rc(max)-Rc(0) Ra(min)-Ra(0) Ra(nom)-Ra(0) Ra(max)-Ra(0) 9
10 Choices for M/S Flops: clocked feedback safer for variation Din Qb CLK Ability to use ratioed feedback severely compromised by writeability vs noise margin 10
11 Consider variation in design of Flops Din Qb CLK Noise pulse on clock requires analysis of sizing of keeper devices vs data path ->Reducing keeper stack sizing by half for clock power reduces noise margin by from 14 to 9% at 6sigma due to Vt and Leff variation. 11
12 Circuit Techniques for Variability Based on triage from infrastructure work Focus on the goals of the design: Power Timing Voltage range Look for opportunities to reduce constraints imposed by standard circuits 12
13 Latching In 45/32nm with a 16 FO4 T CYCLE and the standard MSFF design, the time available for logic is = 11.5 usable FO4 delays. T SU +T CQ = 3 FO4s, T JITTER 1.5 FO4s (~25ps typical) Jitter is likely to be larger than this given process variability trends The jitter budget must comprehend path variability due to supply droop and device/wire variations A flop that tolerates variations in clock and data arrival time without hurting frequency is highly desirable Should also provide low flow-through time Should provide the ability to incorporate logic for reduced delay Multiple flavors of flops is a usage and support cost (i.e. SA flop, fqbx, msfqbx etc.) If a single flop can provide good performance and robustness, that s better AMD s eight generation processors have ~140,000 flops. At 10fC switching cap on average (10% data activity) and assuming 25% avg. clock gating, 15% of our C AC budget is spent on flops T JIT T CQ T LOGIC T LOGIC = T CYCLE T CQ T SU - T JIT T SU TCQ From Naffziger, 2006 VLSI Ckt Symp 13
14 Some Ways to Shoulder the Variation Burden: Adaptive clocking Programmable Delay Buffers Empirically set the clock edge to optimize frequency Higher granularity more variation tolerance From Naffziger, 2006 VLSI Ckt Symp L BIST and GA search algorithms show promise for per-part optimization 14
15 Logic vs Metal Delay variations Logic deltal dominated Interconnect linewidth and material dominated 65nm timing tools dominated by worst case assumptions Next generation needs to consider the statistical variation of the logic and the interconnect. Biasing metal linewidth may provide margin for critical interconnect much like biasing Lpoly for transistors. Ideally consider layout of interconnect to incorporate dependencies. Metal fill improves variation. 15
16 Metal fill tradeoffs Opportunity to improve variation from processing Designer needs to be cognizant of o additional capacitance (and coupling if not tied fill) o cad tool burden datasize, fill generation o data prep time Before fill After fill 16
17 Clkin from PLL Adaptive Circuits Example: duty cycle correction for process variation through training cycle (Agarwal, 2006 VLSI) Delay Line c d Clkout: Corrected duty cycle from variation a b Ctrl bits From detector/cntr 17
18 Architectural Techniques to reduce variability Goal change the problem to one that can be solved. Example: Rather than make every cell perfect, redundancy reduces effect of weak bitcells Consider the larger issue of identifying weak cells Anticipate problems during the full life of the product 18
19 Architectural Options separate voltage planes VDD1 L2$ L3 Cache VDD2 VDD3 L2$ L2$ VDD4 VDD0 L2$ Solving problem with how to increase headroom for small memory cells Common Technique but difficulty in supplying multiple supplies and architectural latency crossing Boundaries (Kanno, 2006 ISSCC) Core VDD5 Core Core Core VDD6 VDD7 VDD8 Architectural choices in how many supplies can be supported or tied together. 19
20 Adaptive Supply Voltage Energy / Operation Per-part and dynamic voltage management are key More range flexibility and finer grain response will provide differentiation Short Nom High Channel Length Long Low Vdd From Naffziger, 2006 VLSI Ckt Symp 20
21 Options for weak memory elements Cache Datapath1 RegFile Datapath2 Ctrl Identify weakness at test Redundancy in cache Fusing off bad entries in Register file (virtual vs Physical registers Datapath/ctrl can use redundant storage elements at significant area cost (similar to ultradrowsy from L. Clark, et.al, JSSC Feb 2005) Difficult problem for test: BIST for weakness Ideally probe for weakness over life of product and softfuse off any failing cells 21
22 Conclusions Variation requires a new body of infrastructure that must be analyzed for critical requirements Minimizing the impact through circuit techniques is the first answer Consider the overall problem: architectural tradeoffs can also minimize the effect of variation 2006, Advanced Micro Devices. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. 22
EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3. EECS 427 F09 Lecture Reminders
EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3 [Partly adapted from Irwin and Narayanan, and Nikolic] 1 Reminders CAD assignments Please submit CAD5 by tomorrow noon CAD6 is due
More informationLecture 9: Clocking for High Performance Processors
Lecture 9: Clocking for High Performance Processors Computer Systems Lab Stanford University horowitz@stanford.edu Copyright 2001 Mark Horowitz EE371 Lecture 9-1 Horowitz Overview Reading Bailey Stojanovic
More informationEECS 427 Lecture 22: Low and Multiple-Vdd Design
EECS 427 Lecture 22: Low and Multiple-Vdd Design Reading: 11.7.1 EECS 427 W07 Lecture 22 1 Last Time Low power ALUs Glitch power Clock gating Bus recoding The low power design space Dynamic vs static EECS
More informationEE241 - Spring 2004 Advanced Digital Integrated Circuits. Announcements. Borivoje Nikolic. Lecture 15 Low-Power Design: Supply Voltage Scaling
EE241 - Spring 2004 Advanced Digital Integrated Circuits Borivoje Nikolic Lecture 15 Low-Power Design: Supply Voltage Scaling Announcements Homework #2 due today Midterm project reports due next Thursday
More informationInterconnect-Power Dissipation in a Microprocessor
4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition
More informationLecture 11: Clocking
High Speed CMOS VLSI Design Lecture 11: Clocking (c) 1997 David Harris 1.0 Introduction We have seen that generating and distributing clocks with little skew is essential to high speed circuit design.
More informationLecture 10. Circuit Pitfalls
Lecture 10 Circuit Pitfalls Intel Corporation jstinson@stanford.edu 1 Overview Reading Lev Signal and Power Network Integrity Chandrakasen Chapter 7 (Logic Families) and Chapter 8 (Dynamic logic) Gronowski
More informationHIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW. Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray
HIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray Agenda Problems of On-chip Global Signaling Channel Design Considerations
More informationDeep Trench Capacitors for Switched Capacitor Voltage Converters
Deep Trench Capacitors for Switched Capacitor Voltage Converters Jae-sun Seo, Albert Young, Robert Montoye, Leland Chang IBM T. J. Watson Research Center 3 rd International Workshop for Power Supply on
More informationSeong-Ook Jung VLSI SYSTEM LAB, YONSEI University
Low-Power VLSI Seong-Ook Jung 2011. 5. 6. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical l & Electronic Engineering i Contents 1. Introduction 2. Power classification 3. Power
More informationEE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Lecture 16: Power and Performance
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 16: Power and Performance Announcements Homework 3 due on Monday Quiz #3 on Monday Makeup lecture on Friday, 3pm, in 540AB 2 1 Outline Last
More informationAnnouncements. Advanced Digital Integrated Circuits. Midterm feedback mailed back Homework #3 posted over the break due April 8
EE241 - Spring 21 Advanced Digital Integrated Circuits Lecture 18: Dynamic Voltage Scaling Announcements Midterm feedback mailed back Homework #3 posted over the break due April 8 Reading: Chapter 5, 6,
More informationProbabilistic and Variation- Tolerant Design: Key to Continued Moore's Law. Tanay Karnik, Shekhar Borkar, Vivek De Circuit Research, Intel Labs
Probabilistic and Variation- Tolerant Design: Key to Continued Moore's Law Tanay Karnik, Shekhar Borkar, Vivek De Circuit Research, Intel Labs 1 Outline Variations Process, supply voltage, and temperature
More informationEE-382M-8 VLSI II. Early Design Planning: Back End. Mark McDermott. The University of Texas at Austin. EE 382M-8 VLSI-2 Page Foil # 1 1
EE-382M-8 VLSI II Early Design Planning: Back End Mark McDermott EE 382M-8 VLSI-2 Page Foil # 1 1 Backend EDP Flow The project activities will include: Determining the standard cell and custom library
More informationPower Spring /7/05 L11 Power 1
Power 6.884 Spring 2005 3/7/05 L11 Power 1 Lab 2 Results Pareto-Optimal Points 6.884 Spring 2005 3/7/05 L11 Power 2 Standard Projects Two basic design projects Processor variants (based on lab1&2 testrigs)
More informationLecture 10 Circuit Design Rules of Thumb. Overview
Lecture 10 Circuit Design Rules of Thumb Zongjian Chen Broadcom Zongjian_chen@yahoo.com Copyright 2004 by Zongjian Chen 1 Overview What: Sets of design guidelines, practices, numerical rules to follow
More informationRuixing Yang
Design of the Power Switching Network Ruixing Yang 15.01.2009 Outline Power Gating implementation styles Sleep transistor power network synthesis Wakeup in-rush current control Wakeup and sleep latency
More informationDESIGNING powerful and versatile computing systems is
560 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 5, MAY 2007 Variation-Aware Adaptive Voltage Scaling System Mohamed Elgebaly, Member, IEEE, and Manoj Sachdev, Senior
More informationLeakage Power Minimization in Deep-Submicron CMOS circuits
Outline Leakage Power Minimization in Deep-Submicron circuits Politecnico di Torino Dip. di Automatica e Informatica 1019 Torino, Italy enrico.macii@polito.it Introduction. Design for low leakage: Basics.
More informationLow Power System-On-Chip-Design Chapter 12: Physical Libraries
1 Low Power System-On-Chip-Design Chapter 12: Physical Libraries Friedemann Wesner 2 Outline Standard Cell Libraries Modeling of Standard Cell Libraries Isolation Cells Level Shifters Memories Power Gating
More informationLecture 19: Design for Skew
Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004 Outline Clock Distribution Clock Skew Skew-Tolerant Circuits Traditional Domino Circuits Skew-Tolerant
More informationDESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM
DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM 1 Mitali Agarwal, 2 Taru Tevatia 1 Research Scholar, 2 Associate Professor 1 Department of Electronics & Communication
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
More informationA Novel Low-Power Scan Design Technique Using Supply Gating
A Novel Low-Power Scan Design Technique Using Supply Gating S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette,
More informationLow Power Design of Successive Approximation Registers
Low Power Design of Successive Approximation Registers Rabeeh Majidi ECE Department, Worcester Polytechnic Institute, Worcester MA USA rabeehm@ece.wpi.edu Abstract: This paper presents low power design
More informationEE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces. Announcements
EE290C - Spring 04 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 11 Components Phase-Locked Loops Viterbi Decoder Borivoje Nikolic March 2, 04. Announcements Homework #2 due
More informationIntroduction to CMOS VLSI Design (E158) Lecture 9: Cell Design
Harris Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture
More informationLecture 9: Cell Design Issues
Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the
More informationReliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches
1 Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches Wael M. Elsharkasy, Member, IEEE, Amin Khajeh, Senior Member, IEEE, Ahmed M. Eltawil, Senior Member, IEEE,
More informationCMOS Process Variations: A Critical Operation Point Hypothesis
CMOS Process Variations: A Critical Operation Point Hypothesis Janak H. Patel Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign jhpatel@uiuc.edu Computer Systems
More informationLow Power Design in VLSI
Low Power Design in VLSI Evolution in Power Dissipation: Why worry about power? Heat Dissipation source : arpa-esto microprocessor power dissipation DEC 21164 Computers Defined by Watts not MIPS: µwatt
More informationHigh Temperature Mixed Signal Capabilities
High Temperature Mixed Signal Capabilities June 29, 2017 Product Overview Features o Up to 300 o C Operation o Will support most analog functions. o Easily combined with up to 30K digital gates. o 1.0u
More informationDisseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor
Disseny físic Disseny en Standard Cells Enric Pastor Rosa M. Badia Ramon Canal DM Tardor 2005 DM, Tardor 2005 1 Design domains (Gajski) Structural Processor, memory ALU, registers Cell Device, gate Transistor
More informationEECS 427 Lecture 21: Design for Test (DFT) Reminders
EECS 427 Lecture 21: Design for Test (DFT) Readings: Insert H.3, CBF Ch 25 EECS 427 F09 Lecture 21 1 Reminders One more deadline Finish your project by Dec. 14 Schematic, layout, simulations, and final
More informationLecture 23: PLLs. Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 23: PLLs Announcements Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class Open book open notes Project
More informationRECENT technology trends have lead to an increase in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1581 Noise Analysis Methodology for Partially Depleted SOI Circuits Mini Nanua and David Blaauw Abstract In partially depleted silicon-on-insulator
More information04/29/03 EE371 Power Delivery D. Ayers 1. VLSI Power Delivery. David Ayers
04/29/03 EE371 Power Delivery D. Ayers 1 VLSI Power Delivery David Ayers 04/29/03 EE371 Power Delivery D. Ayers 2 Outline Die power delivery Die power goals Typical processor power grid Transistor power
More informationDESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS
DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,
More informationTiming analysis can be done right after synthesis. But it can only be accurately done when layout is available
Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate
More informationActive Decap Design Considerations for Optimal Supply Noise Reduction
Active Decap Design Considerations for Optimal Supply Noise Reduction Xiongfei Meng and Resve Saleh Dept. of ECE, University of British Columbia, 356 Main Mall, Vancouver, BC, V6T Z4, Canada E-mail: {xmeng,
More informationDESIGN FOR LOW-POWER USING MULTI-PHASE AND MULTI- FREQUENCY CLOCKING
3 rd Int. Conf. CiiT, Molika, Dec.12-15, 2002 31 DESIGN FOR LOW-POWER USING MULTI-PHASE AND MULTI- FREQUENCY CLOCKING M. Stojčev, G. Jovanović Faculty of Electronic Engineering, University of Niš Beogradska
More informationLeakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for Sub-130nm CMOS Technologies
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for Sub-30nm CMOS Technologies Bhaskar Chatterjee, Manoj Sachdev Ram Krishnamurthy * Department of Electrical and Computer
More informationTrends and Challenges in VLSI Technology Scaling Towards 100nm
Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends
More informationDIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N
DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic CONTENTS PART I: THE FABRICS Chapter 1: Introduction (32 pages) 1.1 A Historical
More informationAnnouncements. Advanced Digital Integrated Circuits. Quiz #3 today Homework #4 posted This lecture until 4pm
EE241 - Spring 2011 dvanced Digital Integrated Circuits Lecture 20: High-Performance Logic Styles nnouncements Quiz #3 today Homework #4 posted This lecture until 4pm Reading: Chapter 8 in the owhill text
More informationEEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #1: Ultra Low Voltage and Subthreshold Circuit Design Rajeevan Amirtharajah University of California, Davis Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless
More informationLow-Power CMOS VLSI Design
Low-Power CMOS VLSI Design ( 范倫達 ), Ph. D. Department of Computer Science, National Chiao Tung University, Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.tw/~ldvan/ Outline Introduction
More informationLow-Power Digital CMOS Design: A Survey
Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with
More informationUNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
More informationFully Integrated Switched-Capacitor DC-DC Conversion
Fully Integrated Switched-Capacitor DC-DC Conversion Elad Alon In collaboration with Hanh-Phuc Le, Seth Sanders Berkeley Wireless Research Center University of California, Berkeley Multi-Core Chips Are
More informationEnergy Efficiency of Power-Gating in Low-Power Clocked Storage Elements
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements Christophe Giacomotto 1, Mandeep Singh 1, Milena Vratonjic 1, Vojin G. Oklobdzija 1 1 Advanced Computer systems Engineering Laboratory,
More informationOptimization of Overdrive Signoff
Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath VLSI CAD LABORATORY, UC San Diego UC San Diego / VLSI CAD Laboratory -1- Outline Motivation Design Cone
More informationHigh Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers
High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency
More informationECEN 720 High-Speed Links Circuits and Systems
1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.
More informationTo appear in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, February 2002.
To appear in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, February 2002. 3.5. A 1.3 GSample/s 10-tap Full-rate Variable-latency Self-timed FIR filter
More informationAccomplishment and Timing Presentation: Clock Generation of CMOS in VLSI
Accomplishment and Timing Presentation: Clock Generation of CMOS in VLSI Assistant Professor, E Mail: manoj.jvwu@gmail.com Department of Electronics and Communication Engineering Baldev Ram Mirdha Institute
More informationGeared Oscillator Project Final Design Review. Nick Edwards Richard Wright
Geared Oscillator Project Final Design Review Nick Edwards Richard Wright This paper outlines the implementation and results of a variable-rate oscillating clock supply. The circuit is designed using a
More informationHomework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!
EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback
More informationJack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More informationEDA Challenges for Low Power Design. Anand Iyer, Cadence Design Systems
EDA Challenges for Low Power Design Anand Iyer, Cadence Design Systems Agenda Introduction ti LP techniques in detail Challenges to low power techniques Guidelines for choosing various techniques Why is
More informationICS2510C. 3.3V Phase-Lock Loop Clock Driver. Integrated Circuit Systems, Inc. General Description. Pin Configuration.
Integrated Circuit Systems, Inc. ICS250C 3.3V Phase-Lock Loop Clock Driver General Description The ICS250C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology
More informationECEN 720 High-Speed Links: Circuits and Systems
1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by
More informationCOMPREHENSIVE ANALYSIS OF ENHANCED CARRY-LOOK AHEAD ADDER USING DIFFERENT LOGIC STYLES
COMPREHENSIVE ANALYSIS OF ENHANCED CARRY-LOOK AHEAD ADDER USING DIFFERENT LOGIC STYLES PSowmya #1, Pia Sarah George #2, Samyuktha T #3, Nikita Grover #4, Mrs Manurathi *1 # BTech,Electronics and Communication,Karunya
More informationNovel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy School of Electrical and Computer Engineering, Purdue University,
More informationComparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits
Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits P. S. Aswale M. E. VLSI & Embedded Systems Department of E & TC Engineering SITRC, Nashik,
More informationNanowire-Based Programmable Architectures
Nanowire-Based Programmable Architectures ANDR E E DEHON ACM Journal on Emerging Technologies in Computing Systems, Vol. 1, No. 2, July 2005, Pages 109 162 162 INTRODUCTION Goal : to develop nanowire-based
More informationEECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline
EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy
More informationImpact of Leakage on IC Testing?
Deep Sub-micron Test: High Leakage Current and Its Impact on Test; Cross-talk Noise Kaushik Roy Electrical & Computer Engineering Purdue University Impact of Leakage on IC Testing? Our Focus Higher intrinsic
More informationMitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu
More informationOpportunities and Challenges in Ultra Low Voltage CMOS. Rajeevan Amirtharajah University of California, Davis
Opportunities and Challenges in Ultra Low Voltage CMOS Rajeevan Amirtharajah University of California, Davis Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless sensors RFID
More informationCharacterization and Variation Modeling for 22FDX. Ning Jin Digital Design Methodology Team
Characterization and Variation Modeling for 22FDX Ning Jin Digital Design Methodology Team Agenda 1 2 3 4 Introduction to 22FDX Technology Library Characterization in Liberate and Variety Library Characterization
More informationA Low Power Single Phase Clock Distribution Multiband Network
A Low Power Single Phase Clock Distribution Multiband Network A.Adinarayana Asst.prof Princeton College of Engineering and Technology. Abstract : Frequency synthesizer is one of the important elements
More informationLow-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering
Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance
More informationLecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect
Lecture 04 CSE 40547/60547 Computing at the Nanoscale Interconnect Introduction - So far, have considered transistor-based logic in the face of technology scaling - Interconnect effects are also of concern
More informationA Survey of the Low Power Design Techniques at the Circuit Level
A Survey of the Low Power Design Techniques at the Circuit Level Hari Krishna B Assistant Professor, Department of Electronics and Communication Engineering, Vagdevi Engineering College, Warangal, India
More informationOverview ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES. Motivation. Modeling Levels. Hierarchical Model: A Full-Adder 9/6/2002
Overview ECE 3: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Logic and Fault Modeling Motivation Logic Modeling Model types Models at different levels of abstractions Models and definitions Fault Modeling
More informationAn Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS Technology
IJIRST International Journal for Innovative Research in Science & Technology Volume 2 Issue 10 March 2016 ISSN (online): 2349-6010 An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS
More informationDevelopment of a 20 GS/s Sampling Chip in 130nm CMOS Technology
Development of a 20 GS/s Sampling Chip in 130nm CMOS Technology 2009 IEEE Nuclear Science Symposium, Orlando, Florida, October 28 th 2009 Jean-Francois Genat On behalf of Mircea Bogdan 1, Henry J. Frisch
More informationFinFET-based Design for Robust Nanoscale SRAM
FinFET-based Design for Robust Nanoscale SRAM Prof. Tsu-Jae King Liu Dept. of Electrical Engineering and Computer Sciences University of California at Berkeley Acknowledgements Prof. Bora Nikoli Zheng
More informationDESIGNING OF SRAM USING LECTOR TECHNIQUE TO REDUCE LEAKAGE POWER
DESIGNING OF SRAM USING LECTOR TECHNIQUE TO REDUCE LEAKAGE POWER Ashwini Khadke 1, Paurnima Chaudhari 2, Mayur More 3, Prof. D.S. Patil 4 1Pursuing M.Tech, Dept. of Electronics and Engineering, NMU, Maharashtra,
More informationI DDQ Current Testing
I DDQ Current Testing Motivation Early 99 s Fabrication Line had 5 to defects per million (dpm) chips IBM wanted to get 3.4 defects per million (dpm) chips Conventional way to reduce defects: Increasing
More informationChapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li,
More informationCS250 VLSI Systems Design. Lecture 3: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing
CS250 VLSI Systems Design Lecture 3: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing Fall 2010 Krste Asanovic, John Wawrzynek with John Lazzaro and Yunsup Lee (TA) What do Computer
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationBridging the Gap between Dreams and Nano-Scale Reality
Bridging the Gap between Dreams and Nano-Scale Reality Ban P. Wong Design Methodology, Chartered Semiconductor wongb@charteredsemi.com 28 July 2006 Outline Deficiencies in Boolean-based Design Rules in
More informationHigh-speed Serial Interface
High-speed Serial Interface Lect. 9 Noises 1 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2 Sampling in Rx Interface applications
More informationSingle-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003 141 Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators Yuping Toh, Member, IEEE, and John A. McNeill,
More informationECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh
ECE 471/571 The CMOS Inverter Lecture-6 Gurjeet Singh NMOS-to-PMOS ratio,pmos are made β times larger than NMOS Sizing Inverters for Performance Conclusions: Intrinsic delay tp0 is independent of sizing
More informationMicroprocessor Design in the Nanoscale Era
Microprocessor Design in the Nanoscale Era Stefan Rusu Senior Principal Engineer Intel Corporation IEEE Fellow stefan.rusu@intel.com 2012 Stefan Intel Rusu Corporation July 2012 1 Agenda Microprocessor
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 24: Peripheral Memory Circuits
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 24: Peripheral Memory Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11
More informationLecture 8: Memory Peripherals
Digital Integrated Circuits (83-313) Lecture 8: Memory Peripherals Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 20 May 2017 Disclaimer: This course was prepared, in its
More informationLow Transistor Variability The Key to Energy Efficient ICs
Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc.
More information2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic
More informationDATE 2016 Early Reliability Modeling for Aging and Variability in Silicon System (ERMAVSS Workshop)
March 2016 DATE 2016 Early Reliability Modeling for Aging and Variability in Silicon System (ERMAVSS Workshop) Ron Newhart Distinguished Engineer IBM Corporation March 19, 2016 1 2016 IBM Corporation Background
More informationA Static Power Model for Architects
A Static Power Model for Architects J. Adam Butts and Guri Sohi University of Wisconsin-Madison {butts,sohi}@cs.wisc.edu 33rd International Symposium on Microarchitecture Monterey, California December,
More information1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)
CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,
More informationAn Interconnect-Centric Approach to Cyclic Shifter Design
An Interconnect-Centric Approach to Cyclic Shifter Design Haikun Zhu, Yi Zhu C.-K. Cheng Harvey Mudd College. David M. Harris Harvey Mudd College. 1 Outline Motivation Previous Work Approaches Fanout-Splitting
More informationLow Power VLSI Circuit Synthesis: Introduction and Course Outline
Low Power VLSI Circuit Synthesis: Introduction and Course Outline Ajit Pal Professor Department of Computer Science and Engineering Indian Institute of Technology Kharagpur INDIA -721302 Agenda Why Low
More informationPower Considerations in the Design of the Alpha Microprocessor
Power Considerations in the Design of the Alpha 21264 Microprocessor Michael K. Gowan, Larry L. Biro, Daniel B. Jackson Digital Equipment Corporation Hudson, Massachusetts 1. ABSTRACT Power dissipation
More information