Lecture 19: Design for Skew

Transcription

1 Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004

2 Outline Clock Distribution Clock Skew Skew-Tolerant Circuits Traditional Domino Circuits Skew-Tolerant Domino Circuits Slide 2

3 Clocking Synchronous systems use a clock to keep operations in sequence Distinguish this from previous or next Determine speed at which machine operates Clock must be distributed to all the sequencing elements Flip-flops and latches Also distribute clock to other elements Domino circuits and memories Slide 3

4 Clock Distribution On a small chip, the clock distribution network is just a wire And possibly an inverter for b On practical chips, the RC delay of the wire resistance and gate load is very long Variations in this delay cause clock to get to different elements at different times This is called clock skew Most chips use repeaters to buffer the clock and equalize the delay Reduces but doesn t eliminate skew Slide 4

5 Example Skew comes from differences in gate and wire delay With right buffer sizing, 1 and 2 could ideally arrive at the same time. But power supply noise changes buffer delays 2 and 3 will always see RC skew 3 mm g 3.1 mm 0.5 mm pf pf 0.4 pf Slide 5

6 Review: Skew Impact Ideally full cycle is available for work Skew adds sequencing overhead Increases hold time too F1 Q1 D2 Q1 t pcq Combinational Logic T c t pdq D2 t setup F2 t skew ( setup skew ) tpd Tc tpcq + t + t sequencing overhead F1 D2 Q1 F2 CL t t t + t cd hold ccq skew t skew t hold Q1 t ccq D2 t cd Slide 6

7 Cycle Time Trends Much of CPU performance comes from higher f f is improving faster than simple process shrinks Sequencing overhead is bigger part of cycle SpecInt Pentium Pentium II / III MHz Pentium Pentium II / III Fanout-of-4 (FO4) Inverter Delay (ps) V DD = V DD = 3.3 V DD = FO4 inverter delays / cycle Pentium Pentium II / III Process Slide 7

8 Solutions Reduce clock skew Careful clock distribution network design Plenty of metal wiring resources Analyze clock skew Only budget actual, not worst case skews Local vs. global skew budgets Tolerate clock skew Choose circuit structures insensitive to skew Slide 8

9 Clock Dist. Networks Ad hoc Grids H-tree Hybrid Slide 9

10 Clock Grids Use grid on two or more levels to carry clock Make wires wide to reduce RC delay Ensures low skew between nearby points But possibly large skew across die Slide 10

11 Alpha Clock Grids Alpha Alpha Alpha PLL g grid g grid Alpha Alpha Alpha Slide 11

12 H-Trees Fractal structure Gets clock arbitrarily close to any point Matched delay along all paths Delay variations cause skew A and B might see big skew A B Slide 12

13 Itanium 2 H-Tree Four levels of buffering: Primary driver Repeater Second-level clock buffer Gater Route around obstructions Repeaters Typical SLCB Locations Primary Buffer Slide 13

14 Hybrid Networks Use H-tree to distribute clock to many points Tie these points together with a grid Ex: IBM Power4, PowerPC H-tree drives sector buffers Buffers drive total of 1024 points All points shorted together with grid Slide 14

15 Skew Tolerance Flip-flops are sensitive to skew because of hard edges Data launches at latest rising edge of clock Must setup before earliest next rising edge of clock Overhead would shrink if we can soften edge Latches tolerate moderate amounts of skew Data can arrive anytime latch is transparent Slide 15

16 Skew: Latches 2-Phase Latches ( 2 ) tpd Tc tpdq sequencing overhead φ 2 D1 Q1 Combinational D2 Q2 Combinational D3 Logic 1 Logic 2 L1 L2 L3 Q3 t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew φ 2 T t t + t + t 2 ( ) c borrow setup nonoverlap skew Pulsed Latches cd hold pw ccq ( setup skew ) tpd Tc max tpdq, tpcq + t tpw + t t t + t t + t ( ) t t t + t sequencing overhead skew borrow pw setup skew Slide 16

17 Circuit Review circuits are slow because fat pmos load input gates use precharge to remove pmos transistors from the inputs Precharge: φ = 0 output forced high Evaluate: φ = 1 output may pull low A B C φ Y D Y A B C D A B C D Slide 17

18 Domino Circuits inputs must monotonically rise during evaluation Place inverting stage between each dynamic gate / static pair called domino gate Domino gates can be safely cascaded domino AND A B φ W dynamic NAND X static inverter Slide 18

19 Domino Timing Domino gates are 1.5 2x faster than static CMOS Lower logical effort because of reduced C in Challenge is to keep precharge off critical path Look at clocking schemes for precharge and eval Traditional schemes have severe overhead Skew-tolerant domino hides this overhead Slide 19

20 Traditional Domino Ckts Hide precharge time by ping-ponging between halfcycles One evaluates while other precharges Latches hold results during precharge T c t = T 2t pd c pdq Latch Latch t pdq t pdq Slide 20

21 Clock Skew Skew increases sequencing overhead Traditional domino has hard edges Evaluate at latest rising edge Setup at latch by earliest falling edge t = T 2t 2t pd c setup skew Latch Latch t setup t skew Slide 21

22 Time Borrowing Logic may not exactly fit half-cycle No flexibility to borrow time to balance logic between half cycles Traditional domino sequencing overhead is about 25% of cycle time in fast systems! Latch Latch t setup t skew Slide 22

23 Relaxing the Timing Sequencing overhead caused by hard edges Data departs dynamic gate on late rising edge Must setup at latch on early falling edge Latch functions Prevent glitches on inputs of domino gates Holds results during precharge Is the latch really necessary? No glitches if inputs come from other domino Can we hold the results in another way? Slide 23

24 Skew-Tolerant Domino Use overlapping clocks to eliminate latches at phase boundaries. Second phase evaluates using results of first No latch at phase boundary a φ 2 b c d φ 2 φ 2 a a b b c c Slide 24

25 Full Keeper After second phase evaluates, first phase precharges Input to second phase falls Violates monotonicity? But we no longer need the value Now the second gate has a floating output Need full keeper to hold it either high or low φ f H X weak full keeper transistors Slide 25

26 Time Borrowing Overlap can be used to Tolerate clock skew Permit time borrowing No sequencing overhead t overlap t borrow t skew t pd = T c φ 2 φ 2 φ 2 φ 2 Phase 1 Phase 2 Slide 26

27 Multiple Phases With more clock phases, each phase overlaps more Permits more skew tolerance and time borrowing φ 2 φ 3 φ 4 φ 2 φ 2 φ 3 φ 3 φ 4 φ 4 Phase 1 Phase 2 Phase 3 Phase 4 Slide 27

28 Clock Generation en φ 2 φ 3 φ 4 Slide 28

29 Summary Clock skew effectively increases setup and hold times in systems with hard edges Managing skew Reduce: good clock distribution network Analyze: local vs. global skew Tolerate: use systems with soft edges Flip-flops and traditional domino are costly Latches and skew-tolerant domino perform at full speed even with moderate clock skews. Slide 29