Trends and Challenges in VLSI Technology Scaling Towards 100nm

Transcription

1 Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation September 2001 Stefan Rusu 9/ Intel Corp. Page 1

2 Agenda VLSI Technology Trends Frequency and power trends Scaling Challenges Transistor scaling Interconnect scaling Capacitive and inductive coupling Leakage Summary Stefan Rusu 9/ Intel Corp. Page 2

3 Process Technology Evolution 1961 First Planar Integrated Circuit Two transistors 2001 Pentium 4 Processor 42 million transistors Stefan Rusu 9/ Intel Corp. Page 3

4 Moore s Law Electronics,, April 1965 Stefan Rusu 9/ Intel Corp. Page 4

5 Moore s Law - Today Number of transistors per integrated circuit doubles every two years Stefan Rusu 9/ Intel Corp. Page 5

6 SIA Technology Roadmap Characteristic Process Technology [nm] Logic Transistors [mil] Across-chip Clock Speed [MHz] Die area [sq. mm] Wiring Levels Stefan Rusu 9/ Intel Corp. Page 6

7 ITRS Roadmap Acceleration Continues FeatureSize(nm) / Year of Production ITRS 2000 Update Review December 2000 Stefan Rusu 9/ Intel Corp. Page 7

8 Processor Frequency Trend 10,000 Intel Processors Frequency Gate delays/clock 100 Pentium 4 Frequency [MHz] 1, Pentium II Pentium Pro Pentium III 10 Pentium Gate Delays / Clock 1 Frequency doubles each generation Number of gates per clock reduces by 25% Stefan Rusu 9/ Intel Corp. Page 8

9 Processor Core Vs. Bus Clock Core Clk Bus Clk DX2 486DX4 P-100 P-150 P-200 PII-300 PII-400 PIII-600 PIII-700 PIII-800 PIII-1G P4-1.5G P4-2.0G Clock Frequency (MHz) Processor Bus frequency is not keeping up with the processor core Stefan Rusu 9/ Intel Corp. Page 9

10 Processor Power Trend 100 Pentium II Pentium 4 Power (Watts) 10 Pentium Pro Pentium Pentium MMX Pentium III µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Lead processor power increases every generation Compactions provide higher performance at lower power Stefan Rusu 9/ Intel Corp. Page 10

11 Power Density Trend Watts Leakage Pwr Active Pwr Power Density 0.25µ 0.18µ 0.13µ 0.1µ Power Density (W/cm 2 ) Assumptions: 15mm die, 1.5x frequency increase per generation Stefan Rusu 9/ Intel Corp. Page 11

12 Voltage Scaling 10 Supply Voltage [V] 1 ~0.7X Scaling ~0.85X Scaling Year Stefan Rusu 9/ Intel Corp. Page 12

13 Transistor Physical Gate Length 1 0.5um 0.35um 0.25um Technology Node Micron um 130nm 0.18um 0.13um 90nm 65nm 70nm 45nm Transistor Physical Gate Length 50nm 30nm 20nm Year Source: Robert Chau, 6/2001 Stefan Rusu 9/ Intel Corp. Page 13

14 0.13µm m Process Technology 70nm Lgate NMOS transistor in production today Source: S. Tyagi, et.al., IEDM 2000 Stefan Rusu 9/ Intel Corp. Page 14

15 Transistor Physical Gate Length 1 0.5um 0.35um 0.25um Technology Node Micron um 130nm 0.18um 0.13um 90nm 65nm 70nm 45nm Transistor Physical Gate Length 50nm 30nm 20nm Year Source: Robert Chau, 6/2001 Stefan Rusu 9/ Intel Corp. Page 15

16 30nm Physical Gate Length Transistor For the 65nm technology node production 2005 Source: R. Chau, et.al., IEDM 2000 Stefan Rusu 9/ Intel Corp. Page 16

17 Transistor Physical Gate Length 1 0.5um 0.35um 0.25um Technology Node Micron um 130nm 0.18um 0.13um 90nm 65nm 70nm 45nm Transistor Physical Gate Length 50nm 30nm 20nm Year Source: R. Chau, 6/2001 Stefan Rusu 9/ Intel Corp. Page 17

18 Research Transistor with 20nm Physical Gate Length For the 45nm technology node research phase Source: R. Chau, et.al., SNW 2001 Stefan Rusu 9/ Intel Corp. Page 18

19 Oxide Thickness Scaling 5 Oxide Thickness [nm] Equivalent Oxide Thickness (Physical) T OX (Electrical) Technology Generation [um] Source: T. Ghani, VLSI Symposium, 2000 Stefan Rusu 9/ Intel Corp. Page 19

20 Atoms-Thin Gate Oxide Source: R. Chau, et.al., IEDM 2000 Stefan Rusu 9/ Intel Corp. Page 20

21 Moore s Law + 300mm Wafers = 4x advantage Moore s Law: From 0.18µm to 0.13µm = 2x output 300mm Wafers: From 200mm to 300mm = 2x output Combined output advantage: 4x output Stefan Rusu 9/ Intel Corp. Page 21

22 0.13µm m Production Ramp Six factories readying 0.13µm m production Plan to spend $7.5B on capital in 2001 Yields and volume exceeding expectations 0.13µm m products have been shipping since May Stefan Rusu 9/ Intel Corp. Page 22

23 Lithography Challenges 1 Lithography Wavelength Micron 0.1 Silicon Feature Size Year Stefan Rusu 9/ Intel Corp. Page 23

24 Extreme Ultraviolet Lithography EUV lithography uses extremely short wavelength light (20x shorter than today s lithography processes) Visible light 400 to 700 nm DUV lithography 193 and 248 nm EUV lithography 13 nm Will be used first in 2005 for critical lithography steps to produce 70 nm patterns World s First 6-inch EUV ETS Mask Stefan Rusu 9/ Intel Corp. Page 24

25 SRAM Cell Size Scaling SRAM Cell Size [sq.um] Technology Generation [um] SRAM cell size will continue to scale ~0.5x per generation Stefan Rusu 9/ Intel Corp. Page 25

26 Exploit Memory Power Efficiency 100 Power Density (W/cm 2 ) 10 Logic Memory µ 0.18µ 0.13µ 0.1µ Static memory has 10X lower active power density Lower leakage than logic Integrated L2 provides higher bandwidth and lower latency Stefan Rusu 9/ Intel Corp. Page 26

27 Example: Pentium III Processor Evolution 0.18µm m technology 256KB L2 28 million transistors 106 mm² die size 0.13µm m technology 512KB L2 44 million transistors 80 mm² die size Stefan Rusu 9/ Intel Corp. Page 27

28 Bit Line Delay Scaling Normalized delay Logic circuit delay Bit line delay (15% swing scaling) Bit line delay (constant swing) Technology generation [µm] Bit line swing limited by parameter mismatch & differential noise Cell stability degrades with Vt lowering Reducing number of rows per bitline approaching limit Stefan Rusu 9/ Intel Corp. Page 28

29 Process Fluctuations Die-to-Die Fluctuations Within-Die Fluctuations Systematic Random Resist Thickness Lens Aberrations Source: K. Bowman, et.al., ISSCC 2001 Random Placement of Dopant Atoms Stefan Rusu 9/ Intel Corp. Page 29

30 0.18µm m Al Interconnect Metal 6 Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 Transistors Stefan Rusu 9/ Intel Corp. Page 30

31 Wires Are Not Scaling Well Delay [ps] Process Generation [um] Gate Al wires + SiO2 Cu wires + lowk Gate + Al wires Gate + Cu wires Source: SIA NTRS projection Stefan Rusu 9/ Intel Corp. Page 31

32 0.13µm m Cu Interconnect Metal 6 Metal 5 Metal 4 Source: S. Tyagi, et.al., IEDM 2000 Metal 3 Metal 2 Metal 1 Transistors Stefan Rusu 9/ Intel Corp. Page 32

33 7 Metal Layers Number of Metal Layers Technology Generation [um] Stefan Rusu 9/ Intel Corp. Page 33

34 Metal Aspect Ratios 2 Average Aspect Ratio Technology Generation [um] Stefan Rusu 9/ Intel Corp. Page 34

35 Interconnect RC Delay vs. Pitch 40% lower RC delay by using Cu + FSG ILD Source: S. Tyagi, et.al., IEDM 2000 Stefan Rusu 9/ Intel Corp. Page 35

36 Routing a 70nm Processor M9 M8 Super-Fat Wiring Top 2 layers Global routing 25mm M7 M6 M5 M4 M3 M2 M1 Fat Wiring 2 metal layers Cluster-level routing Semi-Global Wiring 2 metal layers Unit-level routing Local Wiring 3 metal layers Block-level routing Stefan Rusu 9/ Intel Corp. Page 36

37 Noise Sources Capacitive Coupling Due to electric field Near field effect Measures resistance to a voltage change Inductive Coupling Due to magnetic field Far field effect Measures resistance to a current change Frequency dependent Stefan Rusu 9/ Intel Corp. Page 37

38 Inductive Noise 1E+02 1E+04 Impedance (Ohms/cm) 1E+01 1E+00 ωl R 1E-01 1E-02 1E+06 1E+07 1E+8 1E+9 Impedance (Ohms/cm) 1E+03 1E+02 1E+01 R ωl 1E+00 1E+08 1E+09 1E+10 1E+11 Frequency (Hz) Frequency (Hz) PCB (FR4) Signal Trace VLSI Metal Line Inductance of VLSI metal lines is becoming important at operating frequencies above 1GHz Stefan Rusu 9/ Intel Corp. Page 38

39 Effects of Capacitive Coupling Capacitive coupling can translate into a noise problem Aggressor Victim or a delay problem Aggressor Victim Stefan Rusu 9/ Intel Corp. Page 39

40 Worst Case Input Patterns far near victim near far C-only L-only C & L cancel C & L additive! Near attackers couple mostly by capacitance! Far attackers couple mostly by inductance! Lenz s law - a change in current will generate an opposing current which resists the change! Worst-case switching pattern when near and far attackers switch anti-phase Stefan Rusu 9/ Intel Corp. Page 40

41 Inductive Noise Impact on Delay RLC delay w/ far-attackers switching up Delay RC ONLY delay RLC delay w/ far-attackers switching down Coupling Coefficient! Capacitive noise effect on delay is modeled by coupling coefficient! Inductive noise affects delay too! Inductive noise can also decrease delay Stefan Rusu 9/ Intel Corp. Page 41

42 Skin Effect in VLSI Circuits 10.0 Al [µm] Skin depth [ [µm] µm 2.6µm 0.65µm 0.8µm Cu [µm] 0.26µm Frequency [GHz] 0.21µm Edge frequency is 5-9x 5 the clock frequency Stefan Rusu 9/ Intel Corp. Page 42

43 Sub-Threshold Leakage Sub-threshold leakage increases for lower channel lengths and lower V T s Stefan Rusu 9/ Intel Corp. Page 43

44 Estimated Power of a 15mm Processor Power (Watts) µm, 2V Leakage Active 0% 0% 0% 0% 1% 1% 1% 2% 3% Power (Watts) µm, 1.4V Leakage Active 0% 0% 1% 1% 2% 3% 5% 7% 9% Temp (C) Temp (C) Power (Watts) µm, 1V 26% 1% 2% 3% 5% 8% 11% 15% 20% Leakage Active Power (Watts) % 49% 56% 0.1µm, 0.7V 33% 26% 19% 6% 9% 14% Leakage Active Temp (C) Temp (C) Stefan Rusu 9/ Intel Corp. Page 44

45 Leakage Impact Ioff (na/µm) 10,000 1, µm 0.13µm 0.18µm 0.25µm Temp (C) Design issues: Dynamic circuits may fail Design workarounds needed to guarantee burn-in functionality Test issues: IDDQ testing may become ineffective Thermal-runaway runaway problems, especially at burn-in Stefan Rusu 9/ Intel Corp. Page 45

46 Conclusion We still have not found a fundamental barrier to extending Moore s law The challenges are Power and Efficiency Focus on dissipation, delivery, density VLSI technology scaling is expected to continue for the next decade Stefan Rusu 9/ Intel Corp. Page 46