Deep Trench Capacitors for Switched Capacitor Voltage Converters

Transcription

1 Deep Trench Capacitors for Switched Capacitor Voltage Converters Jae-sun Seo, Albert Young, Robert Montoye, Leland Chang IBM T. J. Watson Research Center 3 rd International Workshop for Power Supply on Chip Nov 17 th, 2012

2 Outline Motivation Switched-capacitor voltage converter with deep trench capacitor technology Design Tradeoffs for Efficiency and Current Density Chip floorplanning / Application Summary 2

3 Power Delivery w/ 2:1 Step Down C4 Today >1V R L ~1V Chip Proposal Reduce current delivery by 2x >2V R L ~2V 2:1 Chip ~1V I 2 R Loss Reduces by 4x LdI/dt Reduces by 2x Net improvement: 4x (including conversion) C4 current Reduces by 2x 3

4 Previous Work on On-Chip Voltage Conversion Efficiency [%] [3] [6] >90% Efficiency [1] [7] hybrid <10% μp Area* 50 1E Output Per Converter Area [A/mm 2 ] [8] [5] [2] [9] [4] On-chip C On-chip L On-package L Goal [1] Le, ISSCC10, 32nm [2] Ramadass, ISSCC10, 45nm [3] Kwong, ISSCC08, 65nm [4] Hazucha, JSSC05, 90nm [5] Wibben, JSSC08, 130nm [6] Abedinpour, ISSCC06, 180nm [7] Patounakis, JSSC04, 250nm [8] Kim, JSSC12, 130nm [9] Sturken, ISSCC12, 45nm *Assumption: 1V, 200W, 500mm 2 Typically 3 approaches : (1) linear (2) switched-capacitor (3) buck Linear regulator not suitable for high-voltage power delivery Difficult to achieve high efficiency & current density simultaneously 4

5 Why Switched-Capacitor Converters? High-voltage power delivery Offers strong benefits especially for high-current applications or when significant package loss exists Achievable by switched-capacitor voltage converters with fixed ratio step-down Linear regulator : no high-voltage delivery benefit Low-cost on-chip integration with existing technology Buck converter : on-chip inductor material with high-enough Q not quite there, external inductors not good for integration With dense deep trench capacitors, switched-capacitor converter can achieve high-efficiency and high current density 5

6 Outline Motivation Switched-capacitor voltage converter with deep trench capacitor technology Design Tradeoffs for Efficiency and Current Density Chip floorplanning / Application Summary 6

7 2:1 Switched-Capacitor Converter V in Q=CΔV in V in V out V out = ½ V in (1 Δ) I out = 2ΔCV in f V out V in Intrinsic efficiency = (1 Δ) non-overlapping clocks 7 VDD 0 VDD 0 Q=CΔV in V out Small Δ offset in V out generates current With traditional capacitor, cannot really achieve intrinsic efficiency or sufficient output current

8 Deep Trench Capacitor Technology High performance SOI CMOS Yields low loss switch Floating body FET with buried oxide isolation Facilitates stacking of thin-oxide devices for high voltage conversion Deep trench capacitor High density, low loss vs. MOS capacitor: Area efficiency: >25 better density Conversion efficiency: >10 better parasitics High-κ storage node dielectric introduced in 32nm, metal liner mitigates poly depletion 32nm SOI edram (Wang, IEDM 2009) 8

9 Scaling Trend of Deep Trench Capacitor IBM s embedded DRAM implemented with deep trench capacitor Since 180nm, cell size reduced ~60% every node Wang, IEDM 2009 TiN inner electrode 9 edram cell capacitance density scales well, path shown for 22nm New technology elements + modest increase in trench AR optimal storage capacitance

10 Multiple Conversion Ratios (3:1, 3:2, ) Ramadass, ISSSCC 2010 Le, ISSSCC 2010 Different conversion ratios, reconfigurable converters, hybrid conversion schemes are possible However, they require more area (than 2:1), not necessarily favorable in terms of current density for high-current microprocessors Depends on whether the application requires a continuously wide range of output voltages 10

11 Outline Motivation Switched-capacitor voltage converter with deep trench capacitor technology Design Tradeoffs for Efficiency and Current Density Chip floorplanning / Application Summary 11

12 2:1 Switched-Capacitor Converter Circuits V high -to-v mid Buffers Converter V high in Clock Level Shift in V mid Non-Overlapping Clock Generation V mid-to-gnd Buffers Using level shifters / stacked buffers, no thick-oxide devices required External supplies of negligible current for /* generation 12

13 2:1 Switched-Cap Single-Phase Design Point V out = ½*Vin*(1-Δ) frequency= f W V in V out C I out = 2*C*Vin*Δ*f Efficiency = 1-Δ-k*W*f Trade-off in efficiency, area, output current by selecting Vin, C, W, frequency, etc. Objective: high efficiency with that satisfies required output current for an application 13

14 Efficiency / Output Current Optimization Vin Iout requirement fixed C, Vout Design point For a certain application, following specs will be fixed Target supply voltage Required output current Allowable area for SC converters fixed flying cap Still, designers have freedom on the following to optimize efficiency Vin (Δ) Switch sizes Frequency Vin Need to keep balance between Δ losses and switching (W, freq.) losses 14

15 15 IBM Research Measurements of 45nm 2:1 SC Converter Efficiency [%] Freq/Cap- Limited Charging-Time Limited Frequency [MHz] I Load [A/mm 2 ] Efficiency [%] Chang, VLSI Symp I Load [A/mm 2 ] Output current is bounded by flying cap charge (when freq. is low), and RC of switch (when freq. is high) Achieved 90% efficiency (Δ~5%, clock losses ~5%) with 2.3A/mm 2 Higher current density achievable by trading off efficiency to-0.95V conversion 90% efficiency 2.3A/mm 2 Freq=100MHz V out [V]

16 Tradeoff: Efficiency vs. SC Area Once the output current requirement is set, spending more area for SC converters (flying capacitors) increases power efficiency But eventually saturates due to minimum switching loss and Δ-related loss 16

17 Outline Motivation Switched-capacitor voltage converter with deep trench capacitor technology Design Tradeoffs for Efficiency and Current Density Chip floorplanning / Application Summary 17

18 Interleaved Switched-Cap Converters Vdd_SCout Reduce output ripple Main processor clock could be tapped and divided for multiple phases 18 18

19 Chip Floorplanning tile tile One switched-capacitor tile consists of multiple interleaved SC converters Multiple switched-capacitor tiles could be placed across a processor Each tile has its own SC control, enable, duty cycle Output could be all tied together SC converters near hot spots would be turned on more frequently than idle spots 19

20 2-D / 3-D Implementation Options 2-D implementation: Allocate certain area for SC 3-D implementation: Interpose chip for voltage conversion/regulation Processor SC converters μc4 C4 Processor Interposer Substrate Processor Chip DT not necessary Interposer Chip Technology w/dt Implementation depends on system requirements, area availability 20

21 Fast Switched-Cap Strategy for Processors Open-loop operation If SC is fully ON, Vdd varies linearly with load current SC could be turned on with a certain duty cycle depending on output load current Closed-loop regulation DT flying capacitors also act as decoupling caps for Vin and Vdd Needs accurate reference voltage Overall closed-loop latency is critical for noise reduction Input voltage noise largely handled against load fluctuations 21 Ramadass JSSC10, Kim JSSC12

22 Another Application Stacked I/O Stacked I/O for low voltage signaling Inputs swing 0 to V DD V DD In0 In0 Driver V DD I/O load US Patent Application # US 2011/ Sense Amplifier Out0 C ~V dd /2 I/O swings V DD to V DD /2 I/O swings 0 to V DD /2 Outputs swing 0 to V DD In1 In1 Sense Amplifier Out1 Voltage Converter Driver I/O load deep trench capacitor 22

23 Summary High-voltage power delivery is beneficial to reduce power distribution losses, which could be achieved with switched-capacitor downconversion Deep trench capacitors enable switched-capacitor converter to achieve high efficiency and high output current Clear scaling path is shown for deep trench capacitors towards 22nm and beyond Design tradeoff exists between efficiency, area, output current DT-based switched-capacitor circuits offer solutions for highlyefficient voltage regulation modules for various applications 23

24 Thank you! 24