TO ENABLE an energy-efficient operation of many-core

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1 1654 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER /3 and 1/2 Reconfigurable Switched Capacitor DC DC Converter With 92.9% Efficiency at 62 mw/mm 2 Using Driver Amplitude Doubler Toru Sai, Member, IEEE, Yoshitaka Yamauchi, Student Member, IEEE, Hajime Kando, Tatsuya Funaki, Takayasu Sakurai, Fellow, IEEE, and Makoto Takamiya, Senior Member, IEEE Abstract A 2/3 and 1/2 reconfigurable switched capacitor (SC) dc dc converter is developed for a per-core dynamic voltage scaling of many-core microprocessors. The power conversion efficiency and the output power density of the SC dc dc converter in 2/3 mode is degraded, because full-swing and half-swing drivers for power transistors are mixed and the resistive loss of the power MOSFETs with the half-swing drivers is large. To solve the problem, a fully integrated driver amplitude doubler (DAD) is proposed. In DAD, the gate amplitude of the power MOSFETs is increased from half-swing to full-swing by generating a 1/3 input voltage sampled from a flying capacitor. In the fabricated 2.7-V input SC dc dc converter mounting four 100-nF 0402 (0.4 mm 0.2 mm 0.2 mm) multilayer ceramic chip capacitors on 180-nm CMOS die achieves the highest efficiency of 92.9% at the output power density of 62 mw/mm 2 in the published step-down SC dc dc converters. Index Terms Switched capacitor (SC), DC-DC converter, stepdown, driver amplitude doubler (DAD), multilayer ceramic chip capacitor (MLCC), power density. Fig. 1. η vs. PD of state-of-the-art step-down DC-DC converters. I. INTRODUCTION TO ENABLE an energy-efficient operation of many-core microprocessors, a fine-grained per-core dynamic voltage scaling is required [1]. As the number of the cores increases, the required number of the power supply voltages (V DD s) also increases. Integrated voltage regulators (IVRs) are the solution to generate multiple V DD s on a chip, because increasing the number of off-chip voltage regulators is not practical. Key metrics of IVRs are the power conversion efficiency (η), the output power (P OUT ), the form factor, the output power density (PD) (=P OUT / area), and the cost. The design target of this brief is to develop an IVR with (1) η>90%, (2) PD> 50mW/mm 2, and (3) alowcost bulk CMOS process. The conventional IVRs, however, Manuscript received August 28, 2017; revised October 4, 2017; accepted October 5, Date of publication October 12, 2017; date of current version October 29, This work was supported by Murata Manufacturing Company, Ltd. This brief was recommended by Associate Editor H.-J. Chiu. (Corresponding author: Toru Sai.) T. Sai, Y. Yamauchi, T. Sakurai, and M. Takamiya are with the Institute of Industrial Science, University of Tokyo, Tokyo , Japan ( sai@iis.u-tokyo.ac.jp). H. Kando is with the Innovative Technology Development Department, Murata Manufacturing Company Ltd., Shiga , Japan. T. Funaki is with the JISSO Technology Development Department, Murata Manufacturing Company Ltd., Shiga , Japan. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCSII do not satisfy the design target. Fig. 1 shows η and PD of the state-of-the-art step-down DC-DC converters with the switching frequency (f SW ), the output voltage (V OUT ), and the output current (I OUT ) including both buck converters and switched-capacitor (SC) DC-DC converters. The design target of this brief is shown. In the fully integrated buck converter [2], η of 72% is comparable to η = 67% of an ideal LDO and η is too low due to the low quality factor (Q = 4.5) of the on-chip inductor. In the buck converter with on-interposer inductor [3], the lack of the scalability of inductor [2] is a problem in IVRs, though both η = 90% and PD = 2.6W/mm 2 satisfy the design target. In the fully integrated SC DC-DC converters using the bulk CMOS process, η = 79.76% [4], 81% [8], and PD = 1.3mW/mm 2 [5] do not satisfy the design target, which indicates the tradeoff between η and PD. In the fully integrated SC DC-DC converters using the deep trench capacitor process [6], η = 90% and PD = 3.71W/mm 2 are achieved. This approach does not satisfy the design target, because the deep trench capacitor process is not low-cost and not generally available. In the SC DC-DC converters with off-chip capacitors, PD = 1.0mW/mm 2 [7] do not satisfy the design target. To achieve the design target, in this brief, a 2/3 and 1/2 reconfigurable SC DC-DC converter mounting four 100-nF 0402 (0.4mm 0.2mm 0.2mm) multilayer ceramic chip capacitors (MLCCs) on 180-nm CMOS die is developed c 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 SAI et al.: 2/3 AND 1/2 RECONFIGURABLE SC DC DC CONVERTER WITH 92.9% EFFICIENCY AT 62mW/mm 2 USING DAD 1655 Fig. 3. Proposed driver amplitude doubler (DAD). Fig. 4. Gate/source/drain voltages of all power transistors in conventional SC DC-DC converter in 2/3 mode. Fig. 2. (a) Proposed 2/3 and 1/2 reconfigurable SC DC-DC converter. (b) Timing chart of conventional and proposed converter in 2/3 mode. for the dynamic voltage scaling. The developed SC DC-DC converter with the proposed fully-integrated driver amplitude doubler (DAD) achieved η = 92.9% and PD = 62mW/mm 2 at the input voltage (V IN )of2.7v,v OUT of 1.71V, and I OUT of 100mA. II. SC DC-DC CONVERTERS WITH DRIVER AMPLITUDE DOUBLER A. Gate Amplitude in 2/3 SC DC-DC Converters In this chapter, the problem of the conventional 2/3 SC DC-DC converter is explained. Then, a new SC DC-DC converter with the proposed DAD is introduced. Fig. 2 (a) shows a circuit schematic of the proposed 2/3 and 1/2 reconfigurable SC DC-DC converter with two flying capacitors (C FLY1 and C FLY2 ). In this brief, V IN is 2.7V and V OUT is 1.8V and 1.35V in 2/3 and 1/2 mode, respectively, because all nine power transistors are 1.8-V core transistors in 180-nm CMOS process. Fig. 2(b) shows a timing chart of the conventional and the proposed SC DC-DC converter in 2/3 mode. In the conventional SC DC-DC converter, the amplitude Φ 1H and Φ 2H is 0.9V, because DAD in Fig. 2(a) is not used and V X is connected to V OUT. In contrast, in the proposed SC DC-DC converter, the amplitude Φ 1H and Φ 2H is doubled to 1.8V, because V X of 0.9V is generated by the proposed DAD shown in Fig. 3. Figs. 4 and 5 show gate/source/drain voltages of all power transistors in the conventional and the proposed SC DC-DC converter in 2/3 mode, respectively. The conventional SC DC-DC converter is based on [4]. In the conventional SC DC-DC converter in Fig. 4, the resistive loss of M 1,M 2,M 5, and M 6 is large, because V GS of M 1,M 2,M 5, and M 6 is 0.9V due to the 0.9-V amplitude Φ 1H and Φ 2H. Thus, four power transistors (M 1,M 2,M 5, and M 6 ) are weak ON out of the working seven power transistors (M 1,M 2,M 4,M 5,M 6,M 8, and M 9 ). Fig. 6 shows a simulated V GS dependence of ON resistance of pmosfet. When V GS is reduced from 1.8V to 0.9V, the ON resistance increases to x3, which degrades η and PD. To achieve both high η and high PD, the full-swing (=1.8-V amplitude) V GS is the primary design goal. In the proposed SC DC-DC converter in Fig. 5, the resistive loss of M 1,M 5, and M 6 is reduced, because V GS of M 1,M 5, and M 6 is doubled to 1.8V because of the 1.8-V amplitude Φ 1H and Φ 2H thanks to DAD, thereby achieving higher η and PD than the conventional SC DC-DC converter.

3 1656 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018 Fig. 7. Simulated C X1 or C X1 + C X2 dependence of V X. Fig. 5. Gate/source/drain voltages of all power transistors in proposed SC DC-DC converter in 2/3 mode. Fig. 6. Simulated V GS dependence of ON resistance of pmosfet for power transistor. B. Proposed Driver Amplitude Doubler How to generate V X of 0.9V is explained in Fig. 5. Both C FLY1 and C FLY2 are implemented with off-chip capacitors, while both C X1 and C X2 are implemented with on-chip MOS gate capacitors. DAD with and without C X2 block is discussed. In DAD without C X2 block, V X is 0.9V in Φ 2 phase, because V X is connected to V 1 of 0.9V. In Φ 1 phase, V X goes above 0.9V, because the charge (Q 1 ) from the non-overlap clock generator to drive the gate voltage of the power transistors (M 1, M 2,M 5, and M 6 ) from 2.7V to 0.9V is injected to V X.In DAD without C X2 block, V X in Φ 1 phase is shown as, V X = C X1V 1 + C G V IN, (1) where C G is the total gate capacitance of the power transistors (M 1,M 2,M 5, and M 6 ), C G V IN is the charge amount of C G in Φ 2 phase. Because V 1 is equal to 1/3 V IN,Eq.(1) is rewritten as, 1 3 V X = V IN. (2) Fig. 8. Simulated waveforms of V OUT, V X, 1H with C X2. When C G is zero, V X is equal to 1/3 V IN. Actually, however, C G is not neglected and V X is above 1/3 V IN (= 0.9V). When V X goes above 0.9V, M 7 will be turned on, which is not acceptable. Fig. 7 shows the SPICE simulated C X1 dependence of V X. To obtain V X of 0.9V, large C X1 is required and the die area overhead is increased, which is not acceptable. To prevent the rise of V X and the large area overhead of C X1, DAD with C X2 block is proposed. In DAD with C X2 block, in Φ 2 phase, C X1 is charged to 0.9V and C X2 is charged to 0V. V X in Φ 1 phase is shown as, V X = C X1V 1 + C X2 0V + C G V IN = C X1 + C X2 + C G 1 3 V IN. (3) C X1 + C X2 + C G When C X2 is designed to be equal to 2 C G, V X is equal to 1/3 V IN, which achieves the design target. Fig. 8 shows the simulated waveforms of V OUT, V X, and Φ 1H of Fig. 5 with C X2 block at I OUT = 100mA, f SW = 5MHz. The voltage V X samples V 1 by C X1 in Φ 2 phase then holds V 1 to 0.9V in Φ 1 phase thanks to DAD with C X2 block. Fig. 7 shows the simulated C X1 + C X2 dependence of V X. C X1 is fixed to 416pF and C X2 is varied. To obtain V X of 0.9V, the total required capacitance (C X1 + C X2 ) is reduced by 84%, because C X2 is pre-charged to 0V instead of 0.9V. Thanks to the C X2 block, the area overhead of C X1 + C X2 is reduced. III. MEASURED RESULTS Fig. 9 shows a die photo and a layout of the 2/3 and 1/2 reconfigurable SC DC-DC converter directly mounting four 100-nF 0402 (0.4mm 0.2mm 0.2mm) MLCCs (GRM022R60G104ME15) on 180-nm CMOS die. In Fig. 2(a), all nine power transistors are 1.8-V core transistors and other

4 SAI et al.: 2/3 AND 1/2 RECONFIGURABLE SC DC DC CONVERTER WITH 92.9% EFFICIENCY AT 62mW/mm 2 USING DAD 1657 Fig. 9. Die photo and layout of reconfigurable SC DC-DC converter. Fig. 10. Die photo of reconfigurable SC DC-DC converter on PCB. Fig. 12. Measured clock frequency dependence of efficiency in (a) 2/3 mode and (b) 1/2 mode at different I OUT. Fig. 11. Thermal shock test. block also use 3.3-V I/O transistors. Die size is 3.3mm by 1.8mm and the core area is 2.1mm by 1.3mm. Four MLCCs areusedforc IN, C FLY1, C FLY2, and C OUT. C X1 of 416pF and C X2 of 69pF are implemented on the die. V IN is fixed to 2.7V. Fig. 10 shows a die mounted on PCB. The mounting of MLCCs on the silicon die is also reported in [9], however, the reliability of the mounting may be an issue, because the coefficients of thermal expansion of MLCCs and the silicon are different. To verify the reliability of the mounting, the thermal shock testing is done using the thermal shock chamber (Espec TSA-71H-W). Fig. 11 shows the thermal profile of the one cycle of the thermal shock testing specified in the testing standard (JIS C [10]). η of three SC DC-DC converters in 2/3 mode and I OUT of 100mA before and after the 101-cycle thermal shock are measured and compared. The measured η change is very small (Sample 1: η = 92.88% to 92.96%, Sample 2: η = 93.08% to 93.14%, and Sample 3: η = 92.87% to 92.99%), indicating that the mounting of MLCCs on the silicon die is reliable. Fig. 13. Measured V OUT dependence of efficiency in 2/3 and 1/2 mode with varied clock frequency at I OUT = 10mA. Fig. 12 shows the measured clock frequency dependence of η in 2/3 and 1/2 mode at different I OUT. In 2/3 mode and I OUT of 100mA, the peak η of 92.9% is obtained at 4MHz and V OUT of 1.71V, achieving P OUT of 171mW and PD of 62mW/mm 2. In 2/3 mode and I OUT of 10mA, the peak η of 94.6% is obtained at 600kHz and V OUT of 1.75V, achieving P OUT of 17.5mW and PD of 6.4mW/mm 2. In 1/2 mode and I OUT of 100mA, the peak η of 92.7% is obtained at 4MHz and V OUT of 1.28V, achieving P OUT of 128mW and PD of 47mW/mm 2.In 1/2 mode and I OUT of 10mA, the peak η of 94.5% is obtained at 500kHz and V OUT of 1.31V, achieving P OUT of 13.1mW and PD of 4.8mW/mm 2.Fig.13 shows the measured V OUT dependence of η in 2/3 and 1/2 mode with varied clock frequency at

5 1658 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018 TABLE I COMPARISON WITH STATE-OF-THE-ART STEP DOWN SC DC-DC CONVERTERS Fig. 14. Measured I OUT dependence of efficiency in 2/3 and 1/2 mode. Fig. 15. Measured V OUT and Clk at I OUT = 100mA in 2/3 mode. IV. CONCLUSION The 2/3 and 1/2 reconfigurable 2.7-V input SC DC-DC converter mounting four 100-nF 0402 MLCCs on 180-nm CMOS die is developed for IVRs. The reliability of the mounting of MLCCs on the silicon die is measured and verified. Thanks to the proposed fully-integrated DAD, the SC DC-DC converter in 2/3 mode at V OUT of 1.71V and I OUT of 100mA achieved the highest η of 92.9% at PD = 62mW/mm 2 in the published step-down DC-DC converters. REFERENCES Fig. 16. Measured V OUT and Clk at I OUT = 100mA in 1/2 mode. I OUT = 10mA. The operation of the 2/3 and 1/2 reconfigurable SC DC-DC converter is demonstrated. Fig. 14 shows the measured I OUT dependence of η of the proposed 2/3 and 1/2 reconfigurable SC DC-DC converter at 5MHz. In 2/3 mode, the peak η of 93.3% is obtained at I OUT of 70mA and V OUT of 1.74V, achieving P OUT of 122mW and PD of 45mW/mm 2. In 1/2 mode, the peak η of 92.8% is obtained at I OUT of 90mA and V OUT of 1.30V, achieving P OUT of 117mW and PD of 43mW/mm 2. Figs. 15 and 16 show the measured waveforms of V OUT and Clk of the SC DC-DC converter in 2/3 and 1/2 mode, respectively. V IN is 2.7V and f SW is 5MHz. The peak-to peak spike noise are 127mV and 83mV in 2/3 and 1/2mode, respectively. Table I shows the comparison with the state-of-the-art step-down SC DC-DC converters. The proposed SC DC-DC converter using the low-cost bulk CMOS process and MLCCs achieved the highest η of 92.9% at PD = 62mW/mm 2 in the published step-down DC-DC converters, achieving the design target. [1] S. Zhang, N. R. Shanbhag, and P. T. Krein, System-level optimization of switched-capacitor VRM and core for sub/near-vt computing, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 9, pp , Sep [2] P. Kumar et al., A0.4V 1V 0.2A/mm 2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS, in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, USA, 2015, pp [3] N. Kurd et al., 5.9 Haswell: A family of IA 22nm processors, in Proc. IEEE Int. Solid State Circuits Conf., San Francisco, CA, USA, 2014, pp [4] H.-P. Le, S. R. Sanders, and E. Alon, Design techniques for fully integrated switched-capacitor DC DC converters, IEEE J. Solid-State Circuits, vol. 46, no. 9, pp , Sep [5] N. Butzen and M. Steyaert, 12.2 A 94.6%-efficiency fully integrated switched-capacitor DC DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution, in Proc. IEEE Int. Solid State Circuits Conf., San Francisco, CA, USA, 2016, pp [6] T. M. Andersen et al., 4.7 A sub-ns response on-chip switched-capacitor DC DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS, in Proc. IEEE Int. Solid State Circuits Conf., San Francisco, CA, USA, 2014, pp [7] L. G. Salem and P. P. Mercier, A battery-connected 24-ratio switched capacitor PMIC achieving 95.5%-efficiency, in Proc. IEEE Symp. VLSI Circuits, Kyoto, Japan, 2015, pp. C340 C341. [8] G. V. Piqué, A 41-phase switched-capacitor power converter with 3.8mV output ripple and 81% efficiency in baseline 90nm CMOS, in Proc. IEEE Int. Solid State Circuits Conf., San Francisco, CA, USA, 2013, pp [9] C. Schaef, E. Din, and J. T. Stauth, 10.2 A digitally controlled 94.8%-peak-efficiency hybrid switched-capacitor converter for bidirectional balancing and impedance-based diagnostics of lithium-ion battery arrays, in Proc. IEEE Int. Solid State Circuits Conf., San Francisco, CA, USA, 2017, pp [10] Japanese Standard Association, Environmental Testing-Part 2-14: Tests-Test N: Charge of Temperature, Japanese Standard JIS :2001, accessed: Aug. 28, [Online]. Available: