Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Transcription

1 Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations

2 OUTLINE Background FinFET Future Roadmap

3 Keeping up w/ Moore s Law Source: ITU, Mark Lipacis, Morgan Stanley Research

4 MOSFET Fundamentals - Metal Oxide Semiconductor Field-Effect Transistor - 2 types - NMOS & PMOS -> CMOS - 2 Modes Depletion & Enhancement - Current between S-D is controlled by gate voltage S. Tyagi et al., IEDM 2005

5 CMOS Scaling To comply with Moore s Law to maintain Cost-Performance, - Shrink feature size: ArF Immersion Double/Quad patterning EUV - Increase wafer size: 200mm 300mm 450mm 90 nm node T.Ghani et al., IEDM nm node S. Tyagi et al., IEDM nm node K. Mistry et al., IEDM nm node P. Packan et al., IEDM Gate length have not scaled proportionately with device pitch. - Performance enhanced by other methods. - Strained channel regions to increase µ eff. - High-k gate dielectric and metal gate electrodes to increase C eff.

6 On/Off Current Ratio 10-3 I DS (A/µm) G VS (V) - Greater the capacitance coupling between Gate and Channel, better control over the channel. - MOSFET becomes a resistor at very small channel lengths and Drain competes to control the channel. T Liu, VLSI Technology short course, 2012

7 On/Off Current Ratio Leakage Path - Reducing EOT not enough. - Gate cannot control the leakage current paths deep into the bulk that is far from the gate. T Liu, VLSI Technology short course, 2012

8 Body Leakage L g = 25 nm, T ox = 1.5 nm, V DS = 0.7 V, V gs = 0V 5 nm 7.5 nm 10 nm Leakage Current Density [A/cm 2 ] - Much of leakage flows >5nm from the surface Y-K. Choi et al., IEEE Eletron Device Letters, p. 254, 2000

9 New structures Ultra-Thin Body (UTB) SOI wafer Double-Gate (DG) - To eliminate the leakage in the body, get rid of it UTB, DG. - I off is suppressed because gate controls a thinner body from more than one side. - Swing & Vt less sensitive to Lg and Vd. - Body doping can be eliminated. - Less influence of random dopant fluctuations, No impurity scattering. - Higher drive current because of higher carrier mobility and lower leakage. - Lower Vdd and Power consumption.

10 Leakage in DG FET L g = 25 nm, T ox,eq = 12 Å, V DS = 0.7 V 10 nm 20 nm Leakage Current Density [A/cm 2 ] I off = 2.1 na/µm I off = 19µA/µm T Liu, VLSI Technology short course, 2012

11 Double-Gate MOSFET types L. Geppert, IEEE Spectrum, 2002

12 Double-Gate FinFET - Gates wrap around a narrow Si fin. - Current flow parallel to wafer surface. - Double gate or Tri gate. L. Geppert, IEEE Spectrum, 2002

13 Hole Mobility Comparison - Double Gate FET has higher hole mobility because of lower transverse electric field. L. Geppert, IEEE Spectrum, 2002

14 First N-channel FinFET (1998) - First successful n-channel with Lg ~20nm successfully fabricated.

15 First P-channel FinFET (1999)

16 Independent Gate Operation - Double-gate FET with isolated gate electrode allows independent biasing. - One gate for switching and the other for Vth control. T Liu, VLSI Technology short course, 2012

17 Challenges to be solved - Vth adjustment - Gate work function tuning is required. - Fringing capacitances between gate and top and bottom of source/drain. - Parasitic resistance. - Uniform S/D doping is difficult conventional implantation. - Variability and uniformity. - Fin width is critical in performance. - For undoped channel, work function is dominant.

18 MOSFET to FinFET and so on - The Gate-All-Around (GAA) structure provides the greatest capacitive coupling between the gate and the channel.

19 Future FinFETs

20 Summary - The initiative of FinFET was to develop self-aligned double-gate MOSFET to improve gate control to suppress I off and drain induced barrier lowering (DIBL) for gate lengths < 25 nm. - FinFET are viable new sub 22nm transistors. - Such multi-gate MOSFET structures provide a way to lower power and improved performance.

21 Thank You.