Decoupling Capacitance

Transcription

1 Decoupling Capacitance Nitin Bhardwaj ECE492 Department of Electrical and Computer Engineering

2 Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling with effective distance Effective radii of on-chip decaps Decaps in multi-power distribution system On Package Decoupling capacitance platform for substrates, sockets and interposers Noise driven in-package decap optimization Summary References

3 Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling with effective distance Effective radii of on-chip decaps Decaps in multi-power distribution system On Package Decoupling capacitance platform for substrates, sockets and interposers Noise driven in-package decap optimization Summary References

4 Target impedance characteristics Target impedance is falling at an alarming rate Hierarchical decoupling *L.D Smith et al., Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology, IEEE Transactions on Advanced Packaging, Vol. 24, Issue 3, pp , August 1999

5 Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling with effective distance Effective radii of on-chip decaps Decaps in multi-power distribution system On Package Decoupling capacitance platform for substrates, sockets and interposers Noise driven in-package decap optimization Summary References

6 Decap budget based on noise estimation Shortest path between the source and sink offers highly accurate simultaneous switching noise (SSN) estimation. Place decaps around Hot Spots Reduce the current flow by 1/ θ where noise at module k is θ times the tolerable noise limit Decap at module k is only responsible for providing the switching current of module k S. Zhao, K. Roy, and C.-K Koh, Decoupling Capacitance Allocation and Its Application to Power Supply Noise Aware Floorplaning. IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol 21, No. 1, pp , January 2002

7 White space allocation scheme White space (WS) allocation using linear programming Decap budget for each circuit module is converted to the area of silicon required to fabricate the decap where C ox is the unit area cap. Problem of white space allocation can be formulated as a set of following constraints, where S is the total WS allocated, x (j) k be the amount of WS allocated to circuit module j from WS module k, N k = {j: module j is adjacent to WS module k}, H is the isolated WS module with area A k S. Zhao, K. Roy, and C.-K Koh, Decoupling Capacitance Allocation and Its Application to Power Supply Noise Aware Floorplaning. IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol 21, No. 1, pp , January 2002

8 Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling with effective distance Effective radii of on-chip decaps Decaps in multi-power distribution system On Package Decoupling capacitance platform for substrates, sockets and interposers Noise driven in-package decap optimization Summary References

9 Decap modeling with effective distance The goal of decap placement and sizing is to find: Location of the blocks and assignment of whitespace to blocks Thickness of decap so as to satisfy power supply noise and leakage constraints Previous scheme assigns decaps to adjacent blocks only Introduce concept of effective distance to make use of nonadjacent white-space for decap allocation Eric Wong, Jacob Minz and Sung Kyu Lim, Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction. IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol 21, No. 1, pp , January 2002

10 Decap allocation and sizing algorithm Decap planning algorithm White space detection algorithm Longest path tree calculation based on vertical constraint graph Decap allocation and sizing algorithm Generalized network flow to solve min-cost max-flow Eric Wong, Jacob Minz and Sung Kyu Lim, Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction. IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol 21, No. 1, pp , January 2002

11 Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling with effective distance Effective radii of on-chip decaps Decaps in multi-power distribution system On Package Decoupling capacitance platform for substrates, sockets and interposers Noise driven in-package decap optimization Summary References

12 Allocation strategy based on effective radius Based on target impedance Z target, Based on charge time: On chip decap should satisfy both effective radii criteria *M. Popovich and E. G. Friedman, " Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp , April/May 2006

13 Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling with effective distance Effective radii of on-chip decaps Decaps in multi-power distribution system On Package Decoupling capacitance platform for substrates, sockets and interposers Noise driven in-package decap optimization Summary References

14 Impedance of PDS with multiple voltages To shift the antiresonance to a higher frequency Place a smaller decoupling capacitor in parallel Decrease the total ESL of the system On chip ESR (effective series resistance) On Chip ESL (effective series inductance) *M. Popovich and E. G. Friedman, " Decoupling Capacitors for Power Distribution Systems with Multiple Power Supply Voltages Proceedings of the IEEE International SOC Conference, pp , September 2004

15 Voltage Transfer Function of multi-pds Voltage transfer function Kv is: where V dd1 is a lower voltage supply, r is the allowed ripple, V dd2 is higher voltage supply Overshoot free voltage response depends on total ESR of decap, Magnitude of voltage transfer function is strongly dependent on ESL, decreasing with smaller ESL *M. Popovich and E. G. Friedman, " Decoupling Capacitors for Multi-Voltage Power Distribution Systems, IEEE Transactions On VLSI Systems, Vol. 14., No. 3, March 2006.

16 Noise coupling for PDS with decap For frequencies smaller than break frequency both decap and ESL should be decreased Conversely for frequencies ranging from break frequency to infinity, both the ESL and decap should be increased *M. Popovich and E. G. Friedman, " Decoupling Capacitors for Multi-Voltage Power Distribution Systems, IEEE Transactions On VLSI Systems, Vol. 14., No.3, March 2006

17 Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling with effective distance Effective radii of on-chip decaps Decaps in multi-power distribution system On Package Decoupling capacitance platform for substrates, sockets and interposers Noise driven in-package decap optimization Summary References

18 System decoupling loops for PCB mounted decaps Topside cap Suffers from via loop inductance Expensive solutions: adding capacitance directly to the substrate, resort to high density interconnect technologies such as microvias, blind vias, and stepped vias Josh G. Nickel, Joseph F Rosenberger, Decoupling Capacitance Platform for Substrates, Sockets and Interposers, DesignCon 2005

19 Decap loop with CapCore Interposer Shown 10x lower improvement in the power delivery impedance,as seen from the die, for frequencies upto 400Mhz Josh G. Nickel, Joseph F Rosenberger, Decoupling Capacitance Platform for Substrates, Sockets and Interposers, DesignCon 2005

20 View of interposer assembly Fig: Die/Substrate is at the top, with a top cover next, followed by capacitor core, signal pins, finally the interposer body Decoupling is moved closer to the die demonstrating less inductance This scheme demonstrates improvement in power delivery and decoupling CapCore Interposer body Josh G. Nickel, Joseph F Rosenberger, Decoupling Capacitance Platform for Substrates, Sockets and Interposers, DesignCon 2005

21 Agenda Background On-Chip Algorithms for Decap sizing and placement Based on Noise Estimation Decap Modeling with Effective Distance Effective Radii of On-Chip Decaps Decaps in Multi-Power Distribution System On Package Decoupling Capacitance Platform for Substrates, Sockets and Interposers Noise driven in-package decap optimization Summary References

22 Noise Driven In-Package Decap Optimization Developed a model to minimize the cost of the decap in package under the constraint of noise in the PDS Assumptions possible locations for chip I/O ports and decaps are predefined before optimization the impedance matrix is given values of frequency dependent impedance of decap at the sample frequencies are pre-computed Considered two noise metrics Time domain metric Impedance metric Noise at the port i induced by the switching at port j, the noise component at the kth frequency sampling point Jun Chen, Lei He, Noise Driven In Package Decoupling Capacitor Optimization for Power Integrity, Proceeding of the 2006 International Symposium on Physical Design, February 2006

23 Optimal distribution for noise driven approach where α and β are weights for the noise and cost resp. α is chosen to be much larger than β so that noise constraint can be achieved. Distribution for noise driven approach Jun Chen, Lei He, Noise Driven In Package Decoupling Capacitor Optimization for Power Integrity, Proceeding of the 2006 International Symposium on Physical Design, February 2006

24 Comparison of different approaches Different types of decaps considered Results of noise driven approach Decaps are concentrated along the I/O rings Cost of solution is 3X smaller than the solution of impedance based approach. Results of impedance driven approach Impedance as a noise metric leads to large over-design Results of optimal distribution Best location of decap may not be closest to chip can be distributed around the chip and across the planes Jun Chen, Lei He, Noise Driven In Package Decoupling Capacitor Optimization for Power Integrity, Proceeding of the 2006 International Symposium on Physical Design, February 2006

25 Agenda Background On-Chip Algorithms for Decap sizing and placement Based on Noise Estimation Decap Modeling with Effective Distance Effective Radii of On-Chip Decaps Decaps in Multi-Power Distribution System On Package Decoupling Capacitance Platform for Substrates, Sockets and Interposers Noise driven in-package decap optimization Summary References

26 Summary Discussed on-chip decap allocation and placement algorithms On-Chip decap in multi power distribution system Noise coupling in power distribution system Decoupling capacitance platform for substrates, sockets and interposers On-Package decap optimization for power integrity

27 . References L.D Smith et al., Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology, IEEE Transactions on Advanced Packaging, Vol. 24, Issue 3, pp , August 1999 S. Zhao, K. Roy, and C.-K Koh, Decoupling Capacitance Allocation and Its Application to Power Supply Noise Aware Floorplaning. IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol 21, No. 1, pp , January 2002 Eric Wong, Jacob Minz and Sung Kyu Lim, Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction. IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol 21, No. 1, pp , January 2002 M. Popovich and E. G. Friedman, " Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp , April/May 2006 *M. Popovich and E. G. Friedman, " Impedance Characteristics of Decoupling Capacitors in Multi-Power Distribution Systems," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp , December Jun Chen, Lei He, Noise Driven In Package Decoupling Capacitor Optimization for Power Integrity, Proceeding of the 2006 International Symposium on Physical Design, February 2006 Jun Chen, Lei He, Noise Driven In Package Decoupling Capacitor Optimization for Power Integrity Josh G. Nickel, Joseph F Rosenberger, Decoupling Capacitance Platform for Substrates, Sockets and Interposers, DesignCon 2005 M. Popovich and E. G. Friedman, " Decoupling Capacitors for Power Distribution Systems with Multiple Power Supply Voltages Proceedings of the IEEE International SOC Conference, pp , September 2004