PC accounts for 353 Cory will be created early next week (when the class list is completed) Discussions & Labs start in Week 3

Transcription

1 EE141 Fall 2005 Lecture 2 Design Metrics Admin Page Everyone should have a UNIX account on Cory! This will allow you to run HSPICE! If you do not have an account, check: pub/jpg/how-to-get-named-acct.jpg PC accounts for 353 Cory will be created early next week (when the class list is completed) Discussions & Labs start in Week 3 If you have not signed-in on the class roster, please do so after the lecture. EE141 2

2 Getting Started with HSPICE Run the simulator on your input file: hspice filename.sp > filename.lis Use the waveform viewer to see the output: awaves Musts: Input files must have the extension.sp for the waveform viewer to work The input file must have.options POST=2 specified Online help: hspice/hspice.pdf (10MB, 1953 pages, do not print!) The SPICE Book by Andrei Vladimirescu EE141 3 Netlist Format Models of nonlinear elements Circuit netlist Control statements Analysis The input files are case insensitive. The first line is always a comment. Other lines are commented with a leading * or $ All nonlinear devices must have a.model statement. EE141 4

3 Also Important Models: ~ee141/models/g25.mod BJT model for Homework 1: npn.mod 0.25µm CMOS models: g25.mod Machines to log-in to {cory, quasar, c199}.eecs EE141 5 Last Lecture Last lecture Moore s Law Challenges in digital IC design in the next decade Today s lecture Review of Moore s Law Design metrics EE141 6

4 What Happened over 30 Years? ,300 transistors 108 KHz operation ~15,000 x 42 M transistors 1.5 GHz operation Comparison (automotive): Travel from San Francisco to New York in 13 sec! EE141 7 Moore s Law in Microprocessors Transistors (MT) X growth in 1.96 years! Pentium 4 Pentium Pro (P6) Pentium (P5) 486 (P4) 386 (P3) 286 (P2) (P1) Year Source: S. Borkar (Intel) Transistors on Lead Microprocessors double every 2 years EE141 8

5 Moore s Law Logic Density 1000 Logic Transistors/mm 2 Logic Density i860 Pentium II (R) 486 Pentium Pro (R) Pentium (R) 2x trend Source: Intel 1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Shrinks and compactions meet density goals New micro-architectures drop density EE141 9 Die Size Growth 100 Die size (mm) Pentium Pro 486 Pentium ~7% growth per year ~2X growth in 10 years Year Source: S. Borkar (Intel) Die size grows by 14% to satisfy Moore s Law EE141 10

6 Frequency Frequency (Mhz) Doubles every 2 years Pentium 4 Pentium Pro Pentium Year Source: S. Borkar (Intel) Lead Microprocessor frequency doubles every 2 years EE Processor Power 100 Max Power (Watts) Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX? µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Source: Intel Lead processor power increases every generation Compactions provide higher performance at lower power EE141 12

7 Power will be a Problem Power (Watts) KW 5KW 1.5KW 500W Pentium Pro Pentium Year Source: S. Borkar (Intel) Power delivery and dissipation will be prohibitive EE Productivity Trends 10,000,000 10,000 Complexity Logic Transistor per Chip(M) 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. 58%/Yr. compounded Complexity growth rate x x x x x x x Today x 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity EE141 14

8 Summary Technology scaling by 0.7 per generation # of transistors/die doubles every 2 years can integrate 2x more functions per chip cost of a function decreases 2x Main problem: power delivery and dissipation How to design more and more complex chips? Designer productivity does not double every 2 years Need to understand different levels of abstraction EE Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+ EE141 16

9 2010 Outlook Performance 2x / 2 years 1 T instructions/s GHz clock Complexity No of transistors: 1 Billion Die area: 40mm x 40mm Power 10kW! Leakage: 1/3 of total Power P. Gelsinger, µprocessors for the New Millennium, ISSCC 2001 EE Outline Design Metrics Design Metrics Cost Reliability Speed Power EE141 18

10 Cost of Integrated Circuits NRE (Non-Recurrent Engineering) costs fixed design time and effort, mask generation independent of sales volume / number of products one-time cost factor indirect costs (the company overhead) R&D, manufacturing equipment etc. Recurrent costs variable silicon processing, packaging, test proportional to volume proportional to chip area EE NRE Cost is Increasing EE141 20

11 Total Cost Cost per IC cost per IC = variable cost per IC + fixed cost volume Variable cost cost of die + variable cost = cost of die test + cost of final test yield packaging EE Die Cost Wafer Single die cost of die = cost of wafer dies per wafer* die yield Going up to 12 (30cm) From: EE141 22

12 Yield Number of good chips per wafer Y = 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield π Dies per wafer = ( wafer diameter/2) die area 2 π wafer diameter 2 die area EE Defects defects per unit area die area die yield = 1+ α α 3, complexity of mfg. process defects per unit area = 0.5 to 1 /cm 2 cost of die = f (die area) 4 α EE141 24

13 Some Examples (1994) Chip 386DX 486 DX2 Power PC 601 HP PA 7100 DEC Alpha Super Sparc Pentium Metal layers Line width Wafer cost $900 $1200 $1700 $1300 $1500 $1700 $1500 Def./ cm Area mm Dies/ wafer Yield 71% 54% 28% 27% 19% 13% 9% Die cost $4 $12 $53 $73 $149 $272 $417 Wafer cost Die cost = Dies per wafer Die yield EE Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law) Today: ~10,000 transistors/ (~100n$ / transistor) EE141 26

14 Outline Design Metrics Cost Reliability Speed Power EE Reliability Noise in Digital ICs i(t) v(t) V DD Inductive coupling Capacitive coupling Power and ground noise Noise sources Internal (~ signal swing) External (not related to signal levels) EE141 28

15 DC Operation: Voltage Transfer Characteristic V(out) V OH f V(out)=V(in) V OH = f(v OL ) V OL = f(v OH ) V M = f(v M ) V M Switching Threshold V OL V OL V OH V(in) Nominal Voltage Levels EE Mapping between Analog and Digital Signals 1 V OH V IH V(out) V OH Slope = -1 Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V(in) EE141 30

16 Definition of Noise Margins 1 V OH V OL NM H Undefined Region NM L V IH V IL Noise margin high: NM H = V OH V IH Noise margin low: NM L = V IL V OL 0 Gate Output Gate Input (Stage M) (Stage M+1) EE Noise Budget Allocates gross noise margin to expected sources of noise Sources power supply offset cross talk interference timing Differentiate between fixed and proportional noise sources EE141 32

17 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions Output impedance of the driver Input impedance of the receiver EE Regenerative Property out out v 3 f (v) v 3 finv(v) v 1 v 1 finv(v) v 3 f (v) v 2 v 0 in v 0 v 2 in Regenerative Non-Regenerative EE141 34

18 Regenerative Property A chain of inverters v 0 v 1 v 2 v 3 v 4 v 5 v 6 Simulated response 5 V (Volt) 3 1 v 0 v 1 v t (nsec) EE Fan-In and Fan-Out N M Fan-out N Fan-in M EE141 36

19 ( V ) V o u t The Ideal Gate V(out) g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V(in) EE An Old-Time Inverter NM L V M 1.0 NM H V in (V) EE141 38

20 Outline Design Metrics Cost Reliability Speed Power EE Performance: Delay Definitions V in 50% t p t = plh + t 2 phl t V out t phl t plh 90% 50% 10% t t f t r EE141 40

21 Technology Characterization: Ring Oscillator for t p v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N EE Performance: FO4 Inverter Measures quality of design across different technology generations d EE141 42

22 A First-Order RC Network R v out Step response: v in C v out ( t) = (1 e t τ ) v in Propagation delay: Delay: 0.69 RC 90% point: 2.2 RC t p = ln 2 τ = 0. 69RC Important model matches delay of inverter EE Outline Design Metrics Design Metrics Cost Reliability Speed Power EE141 44

23 Power Dissipation Instantaneous power p ( t ) = v ( t ) i ( t ) = V Peak power P peak = V dd i peak Average power 1 P avg = T ) dd i supply V T ( t) t+ T t+ T dd p( t dt = t isupply t () t dt EE Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P avg t p Energy-Delay Product (EDP) = quality metric of gate = E t p EE141 46

24 A First-Order RC Network vin R v out C L E cap 1 = E E cap T E0 1 = p( t) dt = V T T () t dt = V C V () t in i L out dt = C = T T = () = V dd 1 pcap( t) dt Vout ( t) icap t dt CL Vout () t dvout = CL L V 2 V 2 EE Next Lecture Manufacturing Technology EE141 48