Energy Efficient Circuit Design and the Future of Power Delivery

Transcription

1 Energy Efficient Circuit Design and the Future of Power Delivery Greg Taylor EPEPS 2009

2 Outline Looking back Energy efficiency in CMOS Side effects Suggestions Conclusion 2

3 Looking Back Microprocessor scaling has been a topic of interest both at EPEP and to the IC design community in general MOS scaling helps set our expectations for the future Microprocessors tend to bound the high power density edge of the product space 3

4 EPEP 2003 In his Architecting Interconnect address, Peter Hofstee identified the major challenges facing microprocessors: Software inertia I/O bandwidth Power delivery Cooling The future is simpler architecture and more cores 4

5 SPI 2004 In my Design Challenges of the 90 nm Pentium 4 Processor address highlighted similar issues: Power delivery Cooling Variation Gate leakage But scaling will continue 5

6 Power density vs CD 1000 Rocket Nozzle Nuclear Reactor 100 W/c cm Hot Plate Pentium II processor i386 i486 Pentium 4 processor Core 2 Duo processor Pentium III processor Pentium Pro processor Pentium processor Atom Processor 10 1 CD (µm)

7 Energy Efficiency in CMOS CMOS power is determined by C, V, f: Power ~ CV 2 f + I leak V Process technology can improve C Reducing V reduces performance Delay ~ C * Vcc/( /(Vcc V t ) α But it reduces power even faster I leak is also a function of V 7

8 Frequency and Power Measurements Maximum m Frequency (MHz) nm CMOS, 50 C Supply Voltage (V) From: A 320mV 56µW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS ISSCC 08 Tot tal Power (mw) 8

9 Energy-Efficiency Efficiency Measurements Ene ergy Efficiency (G GOPS/Watt) mV 65nm CMOS, 50 C 9.6X Supply Voltage (V) From: A 320mV 56µW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS ISSCC 08 Leakage Power (mw) Active 9

10 10 Voltage Scaling Voltage (V) x/gen CD (nm) Voltage scaling has slowed on recent technologies This is the technology maximum voltage 10

11 Side Effects Reduced voltage operation increases sensitivity to temperature and within die variation RDF sensitivity of state elements is increased requiring redesign or larger sizes SRAM Vmin tends to increase on more aggressive technologies Combinatorial delay variation is increased 11

12 Maxim mum Frequency (MHz) Temperature Induced Variations nm CMOS 110 C 50 C ±2X 0 C 320mV Typical Die Measurements Frequency variation across C Frequency variation across C: ±5% Supply Voltage (V) Increases from ±5% at 1.2V to ±2X at 320mV 12

13 Normali ized Distribution Low Voltage Process Variations nm CMOS Monte Carlo Simulations, 50 C 1.2V ±18% Frequency variation across fast-slow slow skews 320mV ±2X Normalized Frequency Frequency variation across fast-slow slow skews: Increases from ±18% at 1.2V to ±2X at 320mV 13

14 Frequency (MHz) Supply Voltage Compensation nm CMOS, 320mV Typical Die 23 3MHz Temperature ( C) Frequency (MHz) nm CMOS, 320mV, 50 C Adjust supply voltage to maintain constant performance ±50mV adjustment about 320mV: Nominal 23MHz performance sustained across C and fast-slow slow skews MHz Slow Typical Fast Process Skew 14

15 Other Side Effects Very low power delivery impedance Granularity: Each core may differ Stability of state elements: Vmin Some invention needed Test Adaptation to performance, Vmin Slowest low voltage operation is at cold Do we need to operate across the supply range? 15

16 Suggestions Take advantage of many cores Use fine grained power management to overcome within die variations Power VR VRVR VRVR VRVR VRVR VR Core Core Core Core Core Core On die/pkg, point of load regulation Adaptation is a test challenge I/O 16

17 How Will This Change Power Delivery? Regulator inefficiency moves on die + Under the big heat sink But the hot spot gets hotter + Reducing voltage wherever possible reduces overall power 17

18 How Will This Change Power Delivery? Eliminate multiple regulators from the motherboard + Fewer components + Higher voltage, lower current requirements 18

19 How Will This Change Power Delivery? Regulators are constant power loads Which means negative input impedance + Power supply and package designers still have interesting work to do 19

20 How Will This Change Power Delivery? Regulators will be needed inside the die/package Need to deal with high voltages and precision analog electronics on microprocessors + New power management opportunities will arise 20

21 Conclusion Power delivery, cooling, and variation are still challenges for many core chips Power efficient performance has become a key processor metric Operation at very low supply voltage offers significant improvement in power efficiency These combine well with the previously identified many core direction 21

22 Conclusion (cont) Low voltage operation significantly exacerbates within die variation Distributed, on die supply regulation can compensate for this variation Bringing new design, manufacturing, and test challenges 22

23 Thank You