A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping

Transcription

1 A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping Jie Gu, Hanyong Eom and Chris H. Kim Department of Electrical and Computer Engineering University of Minnesota, Minneapolis 1

2 Outline Introduction to resonant supply noise Proposed switched decap circuit Simulated supply noise suppression Test chip implementation Supply noise measurement results Conclusion 2

3 IC Power Supply: Underdamped RLC Network On-Chip Power Grid N. Na, IBM, ECTC 2004 Resonant noise exhibits large magnitude and long duration Causes timing violation, clock skew and reliability issue Excited by µp loop operation or sudden current spike 3

4 Previous Passive Damping Techniques Add on-chip decap Add on-chip resistance Q = 1 R wire L C G. Ji, et al., Intel, T. Adv. Packaging, 2005 Increase R and C to bring down the Q factor Decap consumes large area and gate leakage Resistive damping worsens IR drop 4

5 Previous Active Damping Techniques J. Xu et al., Intel, ISSCC 2007 Detect resonant noise and clamp the overshoot 1mA static current per 3mA load Hard to control trip points under PVT variation Only compensates voltage overshoot 5

6 Previous Active Damping Techniques M. Ang et al., Sun Microsystems, ISSCC 2000 Switching decaps to boost the total charge 5mA quiescent current per regulator Limited swing and PVT sensitivity in opamp 6

7 Principle of Switched Decap Circuit Q swdecap =0.5C V dd +C V dd /2 Q pdecap =2C V dd 5 13X charge boosting factor (i.e. Q swdecap /Q pdecap ) 7

8 Proposed Digital Switched Decap Digital resonant detection circuit Simple implementation for digital ICs Low static power Programmable V SW, PVT insensitive design 8

9 Bandpass and PVT Insensitive Design RC circuit & delay line realize bandpass filter 8mV worst-case V SW variation 9

10 Adjustability of Switching Threshold V SW V SW can be adjusted to avoid unnecessary switching V SW is approximately proportional to R value R implemented using a programmable MOSFET array 10

11 Simulated Switched Decap Performance Resonance is suppressed by 7dB More than 8X decap boost for resonant damping 11

12 Simulated First-droop Regulation 0.13μm, 1.2V Both magnitude and oscillation time are reduced for first-droop noise 6X+ decap boost compared with passive decap 12

13 Test Chip Organization 0.13μm, 1.2V Two types of noise generation circuits Selection of swdecap value: 100pF, 200pF, 300pF On-chip sensor to measure differential noise 13

14 Resonance Generation Logic Creates harmonics at resonant frequency 14

15 Supply Noise Measurements 640MHz clock gated by 1/16 5.5dB noise reduction using 200pF swdecap f res at 40MHz lower than expected due to package inductance 15

16 Frequency Domain Measurements 9.8dB suppression using 300pF swdecap No significant impact on non-resonant frequency noise 16

17 Adjusting Switching Threshold Noise magnitude more sensitive to swdecap value than V SW 17

18 Comparison with Passive Damping Swdecap Value Resonant Suppression Equiv. Passive Decap Decap Boost Equiv. Damp. Resistance 100pF 2.2dB 500pF 5X 0.1Ω 200pF 5.5dB 1500pF 7.5X 0.4Ω 300pF 9.8dB 3500pF 11X 1Ω 5 11X boost over passive decaps Equivalent to 0.1-1Ω resistive damping Passive resistor aggravates IR drop 18

19 Performance Comparison Active Damping Ckt.* This work Technology 90nm 130nm Static Current 2.42mA 0.54mA Load Current suppressed 8.71mA (3X I static ) 33mA (61X I static ) Regulator Area 59x20μm 2 190x220μm 2 First Droop Regulation No (including 300pF) Yes Analog Opamp Yes No * J. Xu et al., Intel, ISSCC

20 Die Photograph and Chip Summary Technology Quiescent Current Regulation Frequency Regulator Area (w/o decap) Regulator Area (w/ 300pF decap) Total Die Area 0.13μm Logic CMOS 0.54mA MHz 100μmx70μm 190μmx220μm 0.9mmx1.8mm 9X less static current compared with prev. swdecap design Swdecap serves as passive decap under norm. condition Up to 11X decap boost compared with passive decap Negligible power consumed for decap switching (1.2%) 20

21 Conclusions Resonant supply noise impacts circuit performance and reliability A switched decap circuit is proposed Low power resonant detection circuit Digital-friendly implementation Programmable and PVT insensitive switching threshold 0.13μm test chip implemented 5 11X boost in effective decap value Up to 9.8dB resonant noise suppression 9X reduction in static current compared with previous switched decap design 21