UPC. 6. Switching noise avoidance. 7. Qualitative guidelines for onchip Power Distribution Network design. 8. References

Transcription

1 6. Switching noise avoidance 7. Qualitative guidelines for onchip Power Distribution Network design 8. References

2 Switching noise avoidance: design Packages: Inductance dominates at high frequency Package decaps: effects of ESL, ESR On-chip capacitance (circuit + decaps): resonance Typical frequency response

3 Switching noise avoidance: design Power/ground pin assignment (Moll04) rule: as many pairs as possible, close together

4 Switching noise avoidance: design Differential signaling (LVDS: low voltage differential signaling) smaller voltage swing: reduced power and less noise Controlled skewing of output drivers Output buffer design: no overlapping current IN OUT

5 Qualitative guidelines for PDN design 1. Define your maximum allowed supply voltage degradation td = K α V V ( ) V TH dtd / t d αv = 1 < 0 dv / V V VTH Example: For this rechnology, 5% of decrease in V means 10% of increase in delay

6 Qualitative guidelines for PDN design 2. Define the V/GND ring and stripes minimum width according to: W α F 2 H WBV V f or W min = track I AVG J max 3. Put intra-block decaps close to noise sources (buffers, FF) 4. Use separated V/ground pins for core and I/O 5. Put V/ground pins in pairs close together 6. Limit the maximum numbers of outputs per I/O V /ground pair N F V t LCV 2 r 7. Design the inter-block decaps according to the described procedure

7 Several basic references B. Garben, R. Frech, J. Supper, M.F. MacAllister, Frequency Dependencies of Power Noise, IEEE Transactions on Advanced Packaging, Vol 25, No 2, May 2002, pp M. Shoji, High Speed Digital Circuits, Addison Wesley Q. K. Zhu, Power Distribution Network Design for VLSI, Wiley 2004 Y. Kanno et al., Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power multi-cpu Processor, ISSCC 2006, paper 29.4 A V. Mezhiba, E. G. Friedman, Power Distribution Networks in High Speed Integrated Circuits, Kluwer 2004 C-S Yen, Z. Fazarinc, R. L. Wheeler, Time Domain Skin-Effect Model for Transient Analysis of Lossy Transmission Lines, Proceedings of the IEEE, Vol. 70, No 7, July 1982, pp C.R. Paul, Analysis of Multiconductor Transmission Lines, Wiley 1994 J. Rius, M. Meijer, A High-Frequency Non-Quasi-Static Analytical Model Including Gate Leakage Effects for On-Chip Decoupling Capacitors, IEEE Transactions on Advanced Packaging, Vol 29, No 1, February 2006, pp L. D. Smith, Decoupling Capacitors for CMOS Circuits, IEEE 1994 S. Zhao, K. Roy, C-K Koh, "Decoupling Capacitance Allocation and its Application to Power-Supply Noise-Aware Floorplanning", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems. vol. 21, no. 1, pp , H. Su, S. S. Sapatnekar, R. Nassif, Optimal Decoupling Capacitor Sizing and Placement for Standard-Cell Layouts, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 4, April 2003, pp M. Ang, R. Salem, A. Taylor, An On-Chip Voltage Regulator Using Switched Decoupling Capacitors, Proceedings of the IEEE International Sold-State Circuits Conference, pp , 2000 Y. Chen, H. Li, K. Roy, C-K Kho, Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies, IEEE Custom Integrated Circuits Conference, 2005, pp J. Gu, R. Harjani, C. H. Kim, Distributed Active Decoupling Capacitors for On-Chip Supply Noise Cancellation in Digital VLSI Circuits, 2006 Symposia on VLSI and Circuits F. W. Grover, Inductance Calculations, Van Nostrand 1946 (reedited Dover, 2004). H. Veendrick, Deep Sub-micron CMOS ICs From Basic to ASICs, (2 Ed), Springer, 2000