An Efficient Hybrid Voltage/Current mode Signaling Scheme for On-Chip Interconnects

Transcription

1 An Efficient Hybrid Voltage/Current mode Signaling Scheme for On-Chip Interconnects M. Kavicharan, N.S. Murthy, and N. Bheema Rao Abstract Conventional voltage and current mode signaling schemes are unable to meet the speed requirements and power specifications in deep submicron technologies. The challenges posed by aggressive interconnect scaling forces VLSI circuit designers to look for alternative signaling techniques at nanometre technology nodes. Voltage mode signaling is very slow while current mode signaling suffers from serious static power dissipation problem. This paper presents a novel hybrid voltage/current mode VLSI interconnect signaling scheme which addresses the above problems. In which, both the proposed interconnect driver and receiver circuits are controlled by an efficient Schmitt trigger based control circuit which generates control signals based on input data transitions. These circuits switch from voltage mode to current mode for high data rates thus reducing the delay and dynamic power dissipation significantly. Performance comparison shows that the proposed hybrid scheme is 2 to 2.5 times faster than existing voltage mode schemes for the data rates more than 400 Mbps. It is also observed from the simulation results that the power dissipation and the power delay product (minimum energy) of the proposed scheme are much better than those of voltage and current mode schemes for data rates of >20 Mbps. Keywords Current mode, Delay, Hybrid mode, Power, Power delay product, Schmitt trigger, Voltage mode, VLSI Interconnect. I. INTRODUCTION S the technologies are scaling down, the performance of Aon-chip global interconnects has become a bottleneck in modern VLSI chips. The conventional signaling schemes [1]- [4] such as voltage-mode are not able to meet the speed requirements and power specifications of future technology generations. Hence, these specifications force designers to look for alternative signaling techniques for addressing interconnects scaling problems. Voltage mode with repeaters insertion scheme for driving long interconnects was a popular scheme to reduce delay, but increases significant power This work was sponsored by the MHRD, Govt. of India as a Research Project on Modeling and Noise Reduction in VLSI Interconnect Structures in the DSM Regime. M. Kavicharan is pursuing his Ph.D in the Dept. of ECE at the National Institute of Technology, Warangal, India. (phone: ; kavicharan@nitw.ac.in). N. S. Murthy is a senior Professor at the National Institute of Technology, Warangal, India. ( nsm@nitw.ac.in). N. Bheema Rao is is a Assoc. Professor in the Dept. of ECE at the National Institute of Technology, Warangal, India. ( nbr.rao@gmail.com). dissipation in VLSI circuits. The delay dependence on the line length changes from quadratic to linear [1], but power dissipated by repeater circuits increases linearly with line length [5]. With aggressive interconnect down scaling, line length increases leading to more number of repeaters which further increases the power dissipation. As an alternative to voltage mode signaling with repeaters, current-mode signaling was developed and validated for SRAM circuits [6]-[8]. Later current mode scheme was improved by [9]-[13] for better performance. The conventional current mode scheme signal propagation can be up to three times faster than voltage mode scheme [14]. The significant reduction of delay in current mode signaling is due to loading of the line with low impedance receiver which shifts the system dominant pole [15]. In general, an important advantage of current mode signaling over voltage mode signaling is that, its dynamic power dissipation component can be significantly reduced as a result of smaller voltage swings in the interconnect [3]. However, the major drawback with conventional current mode scheme is the static power consumption at low data rates. Hence, current mode scheme is generally suitable only for long buses carrying high activity data. In ideal voltage mode signaling, driver drives an open circuited interconnect, which causes the output to follow input. In the case of current mode signaling, load is a short circuited interconnect (ideally zero) and hence there exists a continuous current path. This leads to static power dissipation, which limits its use in short interconnects or low data rates, hence voltage mode is better at lower data rates [16]. In addition, it has also been observed that [17], current mode signaling consumes even more power than voltage mode with repeaters. This is the motivation to develop a novel hybrid voltage/current mode circuit which offers the advantages of both voltage mode and current mode for low and high data rates respectively. Repeater less signaling over 10mm line using the proposed hybrid scheme is presented in this paper, which is the major difference from another hybrid scheme [18]. This paper presents an adaptive bandwidth approach using a hybrid voltage/current mode circuit which operates in current mode for high input data rates otherwise in voltage mode with much reduction in static power dissipation. The performance of the proposed hybrid scheme is compared with voltage mode ISBN:

2 and current mode circuits in terms of 50% delay and power consumption. Another important metric for design of all electronic circuits is power delay product, which indicates the degree of energy dissipation in a circuit. Hence, power delay product as a figure of merit should have minimum value for good design. It has been found that, out of existing voltage and current mode schemes, the proposed hybrid scheme has better power delay product for input data rates of above 20 Mbps. The rest of the paper is organised as follows. Section 2 presents a brief discussion on voltage and current mode interconnects in an attempt to clear the basic idea of various modes. In section 3, the proposed hybrid voltage/current-mode scheme is discussed along with Schmitt trigger based control circuit. Section 4 compares the performance of proposed scheme with current mode scheme and voltage mode schemes. Conclusions are drawn in section 5. II. VOLTAGE MODE VS CURRENT MODE The generalised distributed RLC model of voltage/current mode interconnect is shown in Fig.1. The unit length Resistance, Capacitance and Inductance are represented as R, C and L respectively, and dl is denoted as length of each lumped section. The driver is modelled as an inverter with an output capacitance of C s and receiver is approximated as a parallel combination of R L and C L respectively. Input signal employs random input data of Non-return-to-zero (NRZ) format. b III. HYBRID VOLTAGE/CURRENT MODE SCHEME Driver Interconnect Receiver Fig. 2 Block diagram of proposed hybrid voltage/current-mode Scheme The block diagram of the proposed hybrid voltage/currentmode scheme for global interconnects is shown in Fig.2. It consists of driver and receiver circuits with input and control signals. The necessary control signals are generated by Schmitt trigger based control circuit. The same control signals should be given to both the driver and receiver circuits with proper timing synchronization. The driver and receiver circuits operate in two modes (voltage-mode and current-mode) based on control signals (, b ). If the control signals are =1 and b =0 the circuit operates in current-mode for high data rates otherwise in voltage-mode for low data rates. A. Control signal generation circuit b V out C s Rdl Ldl Cdl Rdl Gdl Ldl Cdl Gdl R L V out C L M1 M2 C M3 M4 M5 M7 b Driver Receiver Fig. 1 Generalised distributed RLC model of voltage/current mode interconnect. M6 M8 According to signaling point of view, both voltage and current-mode driver circuits are similar and drive distributed model of RLC interconnect. On the other hand, current mode receiver offers low impedance load while voltage mode receiver provides a high impedance capacitive termination [15]. Fig.1 shows that, for a voltage mode receiver of load capacitance C L, addition of a parallel low impedance resistance R L will change its operation to current mode. Fig. 3 control signal generation circuit Fig.3 shows schematic of control signal generation circuit, which generates control signals ( and b ) based on input data transitions. The circuit consists of an inverter based charge pump and a Schmitt trigger [19]. The conventional Schmitt Trigger complete design is presented by Filanovsky and Baltes [20]. The circuit is designed such that for higher input data rates the control signal is high and for slowly varying signals control signal is low, depending on the duration of the input pulse width. If the voltage across capacitor is zero, transistors M5 and M6 are OFF and M3 and M7 are in linear mode of operation hence, the control voltage = Vdd. When the capacitor voltage rises above V tn, M6 becomes ON and M8 source node voltage starts decreasing, it causes M5 to be ON and control ISBN:

3 voltage starts decreasing. For fast data activity, the capacitor does not have enough time to charge/discharge hence, the capacitor voltage remains below threshold voltage V tn, leading to =. Similarly for slow variation of input data activity, the capacitor voltage and feedback transistors ensure to be below V tn. Thus, for small variation in input data activity the control voltage signal is low otherwise high. Control voltage must be high before the high frequency input signals are applied such that current mode operation (low impedance load) can be invoked at the driver and receiver circuits without delay. In the absence of input data transitions or low data rate signals control voltage can be automatically discharged to low such that power dissipation is minimized in voltage mode operation. The charging time of control signal defines the setup time which ensures the input data signal transitions must be stable before the stable state of control voltage. B. Hybrid voltage/current-mode Driver Circuit C. Hybrid voltage/current-mode Receiver Circuit The hybrid voltage/current-mode receiver circuit is shown in Fig. 5, consists of a voltage mode receiver, diode connected M22 and M23 transistors followed by a low gain amplifier (an inverter with gain A~25). The receiver operates in voltage mode and current mode depending on =0 and 1 respectively. In voltage mode the receiver operates in full swing mode whereas in current mode the receiver input voltage swings around the switching threshold of the diode connected inverter. The inverter acts as a low gain amplifier and will generate full swing voltage levels at the output. Driver Interconnect M17 M18 M19 V out b M21 M22 M23 M25 Vout M26 M9 M13 b M20 M24 b M10 M11 M12 b M14 M15 M16 Interconnect Fig. 4 Hybrid voltage/current-mode Driver circuit Receiver Fig. 4 shows the schematic of hybrid voltage/current mode driver circuit. Transmitter section has two drivers: voltage mode driver and current mode driver. Left half of the hybrid voltage/current mode driver circuit consists of M9 PMOS switch, an inverter and M12 NMOS switch connected in series. When is low M9 is ON and the inverter (M10- M11) operates in voltage-mode, forcing the line to operate in full-swing voltage mode due to the high input impedance of the inverter. For higher data rates when is high, activates the right half of the driver circuit and operates in current-mode with low swing (Fig. 7). This causes the dynamic power dissipation of current mode operation to be lower than voltage mode full swing operation. When is high, M13 NMOS gives weak high and M16 PMOS gives weak low. Hence, the voltage swing on the wire can be reduced. Depending on the control signals, input data can be transmitted either through left half voltage mode driver or right half current mode driver. Fig. 5 Hybrid voltage/current-mode Receiver circuit The diode connected inverter and inverter as an amplifier are designed such that switching threshold is constant. In current mode the driver voltage swings around switching threshold of diode connected inverter, which is shown in Fig. 7. The output data V out follows the input data with a delay of 0.5 ns for current mode operation of hybrid scheme, whereas in voltage mode the obtained delay is 1.31 ns. IV. SIMULATION RESULTS The operation of the proposed hybrid voltage/current mode scheme was simulated in 180nm CMOS technology for of 1.8V. The presented schemes were designed for the line length of 10mm with typical line dimensions using predictive technology model (PTM) [21] of 180nm technology. The per unit length interconnect parameters were extracted using the field solver TCAD Raphael and are presented as follows: R=42.5Ω/cm, L=2.311 nh/cm, C=17.43 pf/cm, G=0.443S/cm and R s = Ω/cm. The simulation results of voltage mode, current mode [23] and proposed hybrid voltage/current mode are obtained using HSPICE W-element method. As per release of HSPICE, at high frequency operation the imaginary term of the skin effect has been added for accurate frequency response. The frequency dependent resistance including skin effect is given by R(f ) = R + Rs (1 + j) f where R is the DC resistance and R s is the skin effect resistance. ISBN:

4 Table1. Performance Mbps (wire length=10 mm) of various schemes Scheme Delay (ns) Power (µw) Power Delay product(ns-µw) Voltage-Mode Voltage-Mode with Repeaters [22] Current-Mode [23] Proposed hybrid scheme Table1 shows the performance comparison between the various schemes for 10 mm line at low data rate of 20 Mbps. In this case hybrid voltage/current mode scheme switches to voltage mode scheme at low data rates and hence the advantage of zero static power is utilised. As compared to other schemes the delay and power dissipation of proposed scheme are approaching voltage mode scheme. The power delay product of the proposed hybrid voltage/current scheme is much less than the voltage mode scheme with repeaters [22], current mode scheme [23] and almost equal to simple voltage mode scheme. Table2. Performance Mbps (wire length=10 mm) of various schemes Scheme Delay (ns) Power (µw) Power Delay product(ns- µw) Voltage mode Voltage mode with repeaters[22] Current mode[23] Proposed hybrid scheme Fig. 6 Simulated waveforms of input signal, control signal, Receiver input signal and Output signal of voltage mode interconnect operation when control voltage=0. Fig. 6 shows an input data stream ( ), control voltage ( ), voltage mode driver output and the output data of proposed scheme. As stated earlier, for slow input data activities the control voltage is set as low and operates in voltage mode. The proposed scheme operates in voltage mode and the driver output is having large swing which is in contrast with the current mode driver output small swing, as shown in Fig. 7. Table2 shows the performance comparison between the various schemes for 10mm line at high input data rate of 400 Mbps. In this case hybrid voltage/current mode scheme switches to current mode and hence the advantage of high speed operation is utilized at high data rate. Increasing the data rate to 400 Mbps yields better improvements in relative performance for the proposed scheme approximately 2.5 times decrease in delay over the voltage mode scheme [1] and approximately half of the power is saved when compared with the above schemes. Furthermore, the power delay product as a figure of merit is much better when compared with other schemes. Fig. 7 Simulated waveforms of input signal, Control voltage, Driver output and Output signal of current mode interconnect operation when control voltage=1. Fig. 7 shows an input data stream ( ), control voltage ( ), current mode driver output and the output data of proposed scheme. For high data rates of input, the output of control signal is set as high and operates in current mode. From the Fig. 7 it is clear that, the driver output voltage of current mode scheme has low swing of 0.2 V when compared with voltage mode driver output full swing of 1.8 V results in lower delay. ISBN:

5 the proposed hybrid voltage/current mode scheme as compared to others, which is the prime requirement in high performance VLSI systems. Fig. 8 Simulated waveforms of input data, control voltage, its inversion and output data of hybrid voltage/current mode circuit. Fig.8 shows an arbitrary input data stream ( ), control voltage ( ), inverted control voltage (b ) and the resultant output data of proposed scheme. These control signals and b are generated using Schmitt trigger based control circuit (Fig. 3). It is apparent that for low data rates (20 Mbps) the generated control signal is low and for higher data rates (500 Mbps) the inverted control signal is low, thus ensuring the voltage and current mode operations respectively. The obtained output of proposed hybrid circuit follows the input with negligible attenuation. Fig. 9 Comparison between the voltage mode, current mode and proposed hybrid voltage/current mode interconnect schemes for Power delay product vs Data rate. Fig.9 shows the power delay product of various schemes for multiple input data rates. It is noticed that the proposed scheme is much better for high data rate applications (>20 Mbps). Power delay product of proposed hybrid voltage/current mode outperforms the existing voltage and current mode schemes. At higher data rates, the power delay product of full-swing voltage mode and low swing current mode signaling are likely to become more dominant as seen from Fig. 9. The minimum power delay product is achieved for V. CONCLUSIONS The proposed hybrid voltage/current-mode scheme combines the benefits of voltage-mode and current-mode techniques. The circuit switches to voltage mode or current mode based on the control signal which is input data dependent. At lower data rates the circuit operates in voltagemode scheme whereas it switches to current-mode scheme for higher data rates, thus it includes the advantages of both voltage mode (zero static power consumption) and current mode (for high speed operation). At data rate of 400 Mbps, the proposed scheme has approximately 2.5 times decrease in delay over the voltage mode scheme and approximately half of the power is saved when compared with the presented schemes. For the data rates of >20 Mbps, the proposed hybrid voltage/current mode circuit power delay product is better than the existing schemes. The proposed scheme also provides an alternative solution for the placement-constrained repeater inserted wires. REFERENCES [1] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Company, Reading, MA [2] Y.I. Ismail, E.G. Friedman, Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect, in 1998 Proc. IEEE ASIC., pp [3] Adler and E. G. Friedman, Repeater design to reduce delay and power in resistive interconnect, IEEE Trans. Circuits Syst. I, vol. 45, pp , May [4] K. Banerjee, A. Mehrotra, A power-optimal repeater insertion methodology for global interconnects in nanometer designs, IEEE Trans. Electron. Devices, 49 (11) [5] Atul Maheshwari and Wayne Burleson, Current sensing techniques for global interconnects in very deep submicron (VDSM) CMOS, IEEE Computer Society Workshop on VLSI, [6] E. Seevinck, P. van Beers, and H. Ontrop, Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM s, IEEE J. Solid-State Circuits, vol. 26, pp , Apr [7] M. Izumikawa and M. Yamashina, A current direction sense technique for multiport SRAM s, IEEE J. Solid-State Circuits, vol. 31, pp , Apr [8] T. Blalock and R. Jaeger, A high-speed sensing scheme for 1T dynamic RAM s utilizing the clamped bit-line sense amplifier, IEEE J. Solid-State Circuits, vol. 27, pp , Apr [9] A. Katoch, H. Veendrick, and E. Seevinck, High speed current-mode signaling circuits for on-chip interconnects, in IEEE International Symposium on Circuits and Systems, (ISCAS), May 2005, Kobe Japan, vol. 4, pp [10] A. Maheshwari and W. Burleson, Differential current-sensing for onchip interconnects, IEEE Transactions on Very Large Scale Integration Systems, vol. 12, no. 12, pp , Dec [11] R. Bashirullah, L. Wentai, and R. K. Cavin, Current-mode signaling in deep submicrometer global interconnects, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp , June [12] Tuuna S, Nigussie E, Isoaho J, Tenhunen, H., Modeling of Energy Dissipation in RLC Current-Mode Signaling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.6, pp.1146,1151, June ISBN:

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