REVIEW ON DIFFERENT LOW DROP-OUT VOLTAGE REGULATOR TOPOLOGY

Transcription

1 REVIEW ON DIFFERENT LOW DROP-OUT VOLTAGE REGULATOR TOPOLOGY Samim Jesmin 1, Mr.Sandeep Singh 2 1 Student, Department of Electronic and Communication Engineering Sharda University U.P, India 2 Assistant Professor, Department of Electronic and Communication Engineering Sharda University U.P, India ABSTRACT: This paper provide a review paper on various Low Dropout (LDO) Voltage Regulator Topology.LDO s must meet the future demand of the portable devices like mobile, pagers, camera recorders and laptops. To design a low drop-out voltage regulator which meet the modern system on chip (SoC) solution and fulfills the power management module required for commercial application it is necessary to study the literature work done before. Various techniques have been proposed to improve the performance parameters like the dropout voltage, load regulation, PSRR, low quiescent currents, fast transient response, have a vital importance in designing of LDO regulator. Furthermore, capacitorless LDO, overcomes the load transient response and ac stability problem. With advancement of future technology, regulator can be proposed with the selection of lower order of nm technology. Keywords: Low Drop-Out Voltage Regulator, Low Power, Low quiescent current, PSR, capacitor-less LDO [1] INTRODUCTION The increasing demand of low power supply as well as low power consumption for high speed portable devices like cellular phones, computer laptops, notebook, etc. is increasing continuously. Conventional LDO regulator requires a large off-chip capacitor in the range of μf to ensure stability [1-2].Therefore output-capacitor-less LDO regulators (OCL-LDO) are preferred for on-chip applications. The voltage regulators are a fundamental block in the power supplies of most all electronic equipment. Low dropout (LDO) voltage regulator is a series linear voltage regulator that regulates the output voltage even when the supply voltage is very small. The term series comes from the Samim Jesmin and MR. Sandeep Singh 1

2 REVIEW ON DIFFERENT LOW DROP-OUT VOLTAGE REGULATOR TOPOLOGY fact that the power transistor is connected in series between the input and output terminal of the regulator [3].This input-output voltage differential is called dropout voltage. The device that uses a low dropout voltage regulator provide a stable output voltage with good noise performance and less power consumption compared to switching regulators to drive small sub-circuit. The parameter of low drop-out regulator is discussed where- Ii, Vi Input current and input voltage Io,Vo Output current and output voltage. A. Dropout Voltage: It is defined as the minimum difference between the input and output voltage below which the circuit ceases to regulate against further reductions in input voltage; this point occurs when the input voltage approaches the output voltage.input voltage is equal to the sum of the output voltage and the dropout voltage. Vdropout = VDD-VOUT = Io Ron B. Quiescent Current or Ground Current: Quiescent current, or ground current, is the difference between input and output currents. Minimum quiescent current is necessary for maximum current efficiency. Quiescent current is defined by- Iq =Ii Io C. Efficiency: The efficiency of a LDO regulator is limited by the quiescent current and input/output voltage as follows: Efficiency = [IoVo/ (Io+Iq) Vi] 100 High efficiency of LDO regulator can be achieved if the drop out voltage and quiescent current must be minimized. In addition, the voltage difference between input and of LDO regulators accounts for the efficiency. D. Load Regulation: It is a measure of the circuit s ability to maintain the specified output voltage under varying load conditions. Load regulation is defined as- Load Regulation = ΔVo/ΔIo E. Line Regulation: Line regulation is a measure of the circuit s ability to maintain the specified output voltage with varying input voltage. Line regulation is defined as- Line regulation=δvo/δvi This paper discusses various designs of LDO with different structure of error amplifier and buffer stage. Each design has some improved factor as compared with other. Some of the designs have focused on decreasing the drop-out voltage, quiescent current. This paper gives 2

3 the brief information regarding various LDO designs and compares them on the basis of drop-out voltage, efficiency, PSRR, quiescent current. This paper is organized as follows: section 2 describes the different LDO designs, section 3 describes results and discussion, and section 4 describes the conclusion. [2] LDO DESIGNS A.CONVENTIONAL LDO REGULATOR Fig. 1 shows the basic topology. Various implementations of LDO comprises of a pass transistor, feedback network and error amplifier where the design of the amplifier varies depending on the performance requirements. Low drop-out voltage regulators is one of common applications of operational amplifiers. A voltage reference circuit is used with the op-amp to generate a regulated voltage (vout). If voltage reference is stable with the change in temperature, vout is a function of the ratio of resistors [4-5]. Figure 1. Conventional LDO B. DIFFERENT CIRCUIT TOPOLOGIES USED TO DESIGN LDO S 1. BUFFER BASED LDO A buffer based LDO [6] that exploits the frequency response dependence of the circuit on load-current to minimize the quiescent current flow. The output current capabilities of mos power transistors are enhanced and drop-out voltages are decreased for the given device size. Two significant contributions are the current efficient buffer and current boosted pass device, make the low-voltage design useful for battery powered circuits. Both these techniques take advantage of the availability of a sense element that provides a linearly load dependent Samim Jesmin and MR. Sandeep Singh 3

4 REVIEW ON DIFFERENT LOW DROP-OUT VOLTAGE REGULATOR TOPOLOGY current. The resulting circuit takes maximum advantage of the transistors utilized to yield low component count and low overall ground current. The current boosting technique is implemented in applications requiring low switch-on resistors, i.e., dc-dc converters. 2. CAPACITOR-LESS LDO A capacitor-less LDO [7]which is a solution to the present bulky external capacitor lowdropout (LDO) voltage regulators with an external capacitor less LDO architecture. The large output capacitor of the conventional LDO s is removed for battery power system integrated for system-on-chip (SoC) applications. The compensation scheme is presented that provides both a fast transient response and full range alternating current (ac) stability. It removes the large external capacitor, while guaranteeing stability under all operating conditions using 0.35µm CMOS technology. Removing the large off-chip output capacitor also reduces the board real estate and the overall cost of the design and makes it suitable for SoC designs. The two major design considerations 1) small over/under shoots during transients and 2) the regulator s stability. To solve these issues, a compensating left-hand plane (lhp) zero is introduced in the proposed design. The proposed regulator consumes not only low power, but it provides a low dropout voltage and fast settling time. SoC designs would benefit from the reduced board real estate, pin count, and cost achievable with the proposed off-chip capacitor less full CMOS LDO regulator. 3. FEED-FORWARD RIPPLE CANCELLATION TECHNIQUE A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique [8] achieves a high power-supply rejection (PSR) over a wide frequency range. Kelvin connection is also used to increase the gain bandwidth of the LDO that allows for faster transient performance. It enables the design for high supply currents and low quiescent current consumption. The topology provided a robust design when the process, temperature and bonding inductance variations are considered. The FFRC can be extended to any existing LDO architecture to yield a high PSR for a wide range of frequencies. In addition, it was shown that kelvin connection at the output helps to increase the GBW of the LDO without affecting the stability at heavy loads. 4. DIGITALLY CONTROLLED LOW-DROPOUT REGULATOR WITH FAST- TRANSIENT AND AUTO TUNING ALGORITHMS 4

5 A digitally controlled [9] low-dropout voltage regulator (LDO) can perform fast transient and auto tuned voltage. As there are still several arguments regarding the digital implementation on the LDO s. The digital compensation scheme is demonstrated to solve the ESR zero problem when a small output capacitor is employed. Digital scheme allows more types of compensation to be implemented in the design flow.to ensure the transient performance; several operating uncertainties should be taken care of by an autonomous manner. Therefore, two auto tuning methods to handle the uncertainty problem were discussed. The first auto tuning method is to adjust the charge-balance current by controlling the driving voltage of the power MOSFET during the transient time. The second auto tuning function is to automatically assign proper initial values for the compensator for avoiding ringing at output voltage. Also the d-ldo is robust when it is operating under the conditions of low supply voltage and wide supply voltage variation. One of the drawbacks in the digital control is the power consumption issue as power consumption of the digital controller is higher than that of the analog controller. [3] RESULT AND DISCUSSION From literature review, it is observed that different researchers have designed different topologies of low drop-out regulator by applying different methodologies.various techniques to enhance the transient response of the LDO regulators and to deal with stability issues and power management problems. Efficiency obtained with mentioned LDO architectures is about 98%.The LDO architectures in [1] provide current efficiency of 99.94% respectively. It is seen that nm technology proves to be better in achieving required performance specifications. The capacitor based LDO has large external capacitor that can be removed allowing for greater power system integration for system-on-chip (SoC) applications that require a sound compensation scheme for both the transient response and the alternating current (AC) stability. Presently, in some applications, the external capacitor used is quite large (10 μf), but capacitor less architectures [3] have been proposed and form a significant part of current CMOS LDO design literature. The advanced power management unit (PMU) concept inside the SoC scheme inspires the digital control potential for the design of a novel low quiescent current LDO regulator that is capable to perform fast transient. An error amplifier structure to improve load regulation of low voltage, low-dropout regulators can be employed. The FFRC technique can be extended to any existing LDO architecture to yield a high PSR for a wide range of frequencies [3]. A LDO regulator using a output transconductance error amplifier with an adaptive transient accelerator achieve fast transient Samim Jesmin and MR. Sandeep Singh 5

6 REVIEW ON DIFFERENT LOW DROP-OUT VOLTAGE REGULATOR TOPOLOGY response, low quiescent current, and high PSR under a wide range of operating conditions. If in the rail-to-rail output stage of the error amplifies, a power noise cancellation mechanism is formed; the size of the power MOS transistor can be minimized [1]. [4] CONCLUSION Comparing different circuit topologies for designing LDO regulator, it is seen that, all LDO specifications constrain each other. It is difficult to improve all of them simultaneously because of various trade-off. As the various performance matrices such as minimization of drop-out voltage, low power, low operating voltages, low quiescent currents, fast transient response, high PSR and high packing density have a vital importance in designing of LDO regulator, future LDO should beware of all these matrices. The capacitor less LDO architecture is good in overcoming the typical load transient and ac stability issues. Furthermore, the designing can be possible with digital implementation and programmability can be added to become suitable for more applications. Also future nm technology offers more advantages in achieving most of the performance specifications so considering the advancement of future technology, regulator can be proposed with the selection of lower order of nm technology to fulfill targeted demands. REFERENCES [1] Sau Siong Chong, and Pak Kwong Chan, A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push Pull Composite Power Transistor IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 11, November [2] Bob Wolbert Micrel s Guide to Designing with Low-Dropout Voltage Regulators, Micrel s Semiconductor, Revised Edition, December [3] G.A.Rincon-Mora, Analog IC design with low drop-out regulator, Mc Grew Hill, 2nd Edition. [4] S.Franco, Design with operational amplifier and analog integrated circuit, Mc Grew Hill, 4 th Edition. [5] P.R.Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuit,New York:John Wiley & Sons.Inc [6] Gabriel A. Rincon-Mora, and Phillip E. Allen, Fellow, A LowVoltage, Low Quiescent Current, Low Drop-Out Regulator IEEE Journal of Solid-state Circuits, vol. 33, no.1, pp.36-44, January [7] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, Full on-chip CMOS Low-Dropout Voltage Regulator, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp , Sep

7 [8] M. El-Nozahi, A. Amer, J. Torres, K. Entesari, and E. SanchezSinencio, High PSR low drop-out regulator with feed-forward ripple cancellation technique, IEEE J. Solid-State Circuits, vol. 45, no. 3, pp , Mar [9] Yen-Chia Chu and Le-Ren Chang-Chien, Digitally Controlled Low-Dropout Regulator with Fast- Transient and Autotuning Algorithms IEEE Transactions on Power Electronics, vol. 28, no. 9,pp , September [10] P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design Oxford University Press, 2nd edition Author: Samim Jesmin, completed B.E from Gauhati University,Assam and is a student of M.TECH in Sharda University in department of in Electronic and communication VLSI. MR. Sandeep Singh is Assistant Professor in Sharda University in department of in Electronic and communication Samim Jesmin and MR. Sandeep Singh 7