CMOS fast-settling time low pass filter associated with voltage reference and current limiter for low dropout regulator

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1 CMOS fast-settling time low pass filter associated with voltage reference and current limiter for low dropout regulator Wonseok Oh a), Praveen Nadimpalli, and Dharma Kadam RF Micro Devices Inc., 6825 W. Galveston Dr. Chandler, AZ, U.S.A a) Abstract: In this work, a fast turn-on settling low dropout regulator (LDO) with current limiter is presented. Dynamically operating the proposed current limiter using a decent current comparator protects the IC from any damage when an overload condition occurs or the output of the regulator is shorted. A novel low pass filter associated with voltage reference circuit, which provides highly filtered reference voltage and fast settling time, is implemented to minimize output noise due to voltage reference noise. The LDO with proposed low pass filter and current limiter has been implemented in a 0.6 µm n-well CMOS process. The LDO dissipates 65 µa quiescent current at 150 ma full load condition and its output noise is nv/ Hz at 100 Hz. Turnon settling time of the LDO is 45 µsec and threshold current of the current limiter is set to 230 ma of output load current. Keywords: low-dropout regulator, current limiter, low pass filter, noise Classification: Integrated circuits References [1] C. Lin and Q.-Y. Feng, Design of current limiting circuit in low dropout linear voltage regulator, Microw. Conf. Proc., APMC Asia- Pacific Conf. Proc., vol. 2, pp Dec [2] O. Moreira-Tamayo, A high current low dropout regulator with dual output stage and dual control loop, 48th Midwest Symp. Circuits Syst., vol. 2, pp , [3] C. K. Chava and J. Silva-Martinez, A Frequency Compensation Scheme for LDO Voltage Regulators, IEEE Trans. Circuits Syst. I, vol. 51, no. 6, pp , June [4] H. Lee, P. K. T. Mok, and K. N. Leung, Design of Low-Power Analog Driver Based on Slew-Rate Enhancement Circuit for CMOS Low-Dropout Regulators, IEEE Trans. Circuits Syst. II, vol. 52, no. 9, pp , Sept

2 1 Introduction As the mobile electronic market is growing continuously, power management ICs are an essential building block in battery-operated products. There are five to seven low dropout regulators (LDOs) in recent power management ICs. Each regulator provides a different supply line to a different chipset. The LDO has several benefits such as high power supply rejection (PSR) and good load and line regulation. LDOs also include a protection circuit such as a current limiter to protect ICs from damage when an overload condition occurs or the output of the regulator is shorted [1, 2]. A current limiter should have low power consumption and occupy a small area. Each LDO needs an independent current limiter since each LDO has different current capability in power management ICs. The Current limiter for the LDO should not have any effect on regulation when output current is smaller than threshold current. When the current limiter detects an overload condition, the LDO s feedback loop is broken and the LDO is out of regulation. The current limiter should provide a fast response and low power consumption with no effect on the LDO characteristics. In addition, conventional LDOs utilize highly filtered voltage references at their inputs and bypass capacitors at their outputs in order to minimize output noise on the voltage reference which is the dominant noise source of LDOs since noise and cross-coupling on the power supply line for RF circuitry plays a dominant role in RF transceiver noise budget [3, 4]. This required large capacitor, especially the capacitor at the input requires gigantic values, more than 1 µf, which can not be integrated and therefore causes an increase in board area. It results in high product cost as well as slow turn-on time. This paper proposes a fast settling time low pass filter associated with voltage reference and current limiter for LDO applications. To achieve a low noise characteristic for the LDO, the novel low pass filter which provides a highly filtered voltage reference and fast turn-on time, is implemented. To protect ICs from overflowing current and innovative current limiting circuit utilizing the current mode comparison technique is implemented. 2 Fast settling time low pass filter for voltage reference Fig. 1 (a) shows a block diagram of a typical LDO regulator, which consists of an error amplifier, a pass device, a high resistance feedback network and an output capacitor C o. The PMOS regulation FET at the output is configured in common-source configuration. The input referred noise of the regulation FET, S n,p (f), can be ignored because of its high transconductance value and the large geometry of the device. The input referred noise power spectral density (PSD) of the error amplifier is denoted by S n,e (f), and total output noise of the voltage reference is defined by S n,ref (f). Total output noise spectral d ensity of the LDO system S n,o (f) is represented by ( S n,o (f) =(S n,ref (f)+s n,e (f)) 1+ R ) S n,r2 R 2 ( R1 R 2 ) 2 + S n,r1. (1) 1596

3 From (1), one of most critical noise contributors of LDOs is reference noise S n,ref (f). Its flicker (1/f) noise is the most dominant noise source of LDOs at low frequencies. Assume that the desired noise spectral density of the LDO at 100 Hz is 500 nv/ Hz, the desired output voltage of the LDO is 2.8 V and the reference input voltage is V. This desired specification requires the LDO to have around a gain stage, which is implemented by resistor networks (R 1 and R 2 ). Then, assume that the LDO itself provides 100 nv/ Hz at 100 Hz. Therefore, spot noise of the reference circuit should not exceed 175 nv/ Hz at the same frequency. This means the reference circuit also requires a low noise profile at low frequencies. To suppress output noise of LDOs due to voltage reference, a low pass filter (LPF) is followed by the reference circuit, at the expense of increasing setting time and board area due to large filter capacitor. To solve this issue, a fast settling time LPF is required without a large filter capacitor. Fig. 1 (b) shows the concept of the proposed LPF associated with reference circuit. It consists of a bandgap voltage reference, buffer, comparator, and LPF composed of MOS transistors M2-M3 and C filter. Fig. 1 (c) shows the schematic of the comparator, bias circuit and delay block associated with the LPF. The key operation of the proposed reference circuit depends on the comparator which enables the LPF. First, M1 sets the gate voltage of M3 by V b so that M3 always operates in the subthreshold region and generates high resistance. The designed two inverters have a high threshold voltage (V th ) near 1.15 V, which drives M9. When V BG is less than V th of inverter, V BG en Fig. 1. (a) Block diagram of a typical LDO regulator depicting major noise contributors, (b) Block diagram of proposed reference circuit with LPF. (c) VBG detect and delay and bias circuit. 1597

4 is high and V BG d is close to ground. So, the comparator output (V c )is low. M2 operates in the triode region and generates a small resistance. The corner frequency of the LPF is located at higher frequencies and it provides fast settling time since total resistance of M2 and M3 is almost same as that of M2. After a few µsec delays, V BG is higher than V th,v BG en is low, then V BG d is close to the supply. So comparator output (V c )goestohigh. M2 is off and M3 still operates in the subthreshold region. M3 generates very high resistance and sets the corner frequency of LPF at lower frequencies without reference voltage variation since both resistance of M2 and M3 are a high value. Thus, a highly filtered reference voltage with fast setting time is achieved. 3 Current limiter for low dropout regulator (LDO) The current limiter should protect the IC from any damage when an overload condition occurs or the output of the regulator is shorted. In order to prevent the LDO from overflow current, a current limiter is implemented. Fig. 2 shows the block diagram of the LDO with proposed current limiter. As seen Fig. 2 (a), the operating concept of the proposed current limiter is described as follow; first the proposed current limiter senses the current (I sense ), which is the ratio of output current. This sensed current is compared to reference current (I ref ), then, generates control signal (V CL ). When I sense is smaller than I ref,v CL goes to high and M pull-up device is off and the LDO operates in the normal condition. When I sense is larger than I ref,v CL goes low and M pull-up turns on. V PG returns to a high level to prevent the LDO from an overload condition. The LDO is implemented with a simple current mirror amplifier (Error amp), pass device (MP) and feedback network resistors. To assure stability, RC miller compensation is adopted between the gate of the pass device and the output of regulator. Fig. 2 (b) shows the schematic of the proposed current limiter. As seen Fig. 2 (a), sensing device MPS is L times smaller than pass device MP. These two devices share the gate-source voltage and operate as a current mirror. The sensing current (I sense ) is L times smaller than the load current Fig. 2. (a) Block Diagram of LDO with Current Limiter. (b) Schematic of proposed current limiter. 1598

5 (I ref ), that is 1/L*I load. However, drain-source voltage mismatch causes the variation of sensing current over load current. To minimize the difference between I out and I sense, the current sensing utilizes a regulated current mirror which is composed of M14-M17. Two resistors (RB) are added to minimize voltage difference of the Vout and I sense node which is the drain of sensing device (MPS) as seen in Fig. 2 (a). This sensing current is copied to one input (M13) of the current comparator and compared with the reference current of the other input (M12). Then, the output of the comparator generates a control signal (V CL ), which controls the pull-up device (M pull-up) in Fig. 2 (a). A small magnitude of current is forced into the current comparator through M11a and M11b which acts like a start- up circuit. To maintain accuracy the same amount of current is subtracted through devices M9a and M9b. When I sense current is higher than I ref,m pull-up device is turned on and V PG signal is the high voltage level to prevent MP device from flowing a higher current than the threshold current. This novel current comparator gives faster response with low current consumption than a conventional voltage reference due to its operation in current mode. Fig. 3. (a) Turn-on settling time response of LDO with proposed LPF and discrete RC filter (b) Measured LDO output noise comparison with proposed LPF and discrete RC (10 uf) filter at 150 ma load current (c) Current limiter operation associated with LDO (d) Micrograph of the LDO with proposed LPF and current limiter. 1599

6 4 Experimental result The proposed fast settling LPF and current limiter associated with LDO are designed and fabricated in a 0.6 µm digital CMOS process with three layers of metal. The designed LDO with proposed low pass filter and current limiter is designed to source a nominal output current of 150 ma. With the help of a highly filtered bandgap reference, the output noise of the LDO is quite small which makes it a suitable supply line for RF applications. Fast settling time of the reference voltage results in a fast turn-on time for the LDO. To protect the LDO from overflow current, a current limiter is implemented Fig. 3 (a) shows the turn-on settling time response of designed the LDO with the proposed LPF compared to a discrete LPF. The achieved turn-on settling time of the LDO is 45 µsec. This settling time is around 220 times faster than that of the RC filter which utilized an off-chip 2.2 µf filter capacitor. Output noise and PSR of the LDO is measured at the full load condition. Fig. 3 (b) shows the measured output noise spectrums of two LDOs. Each LDO is exactly same circuit except for the LPF: one is the proposed LPF and the other is a conventional R-C (10 µf) LPF. The output noise spectral density with the proposed LPF is measured to be nv/ Hz at 100 Hz. The output noise spectral density of the conventional LPF at 40 Hz to 100 Hz ranges is around 0.5 uv/ Hz higher than the proposed one. The reason is corner frequency of the conventional LPF is a little bit higher than that of the proposed LPF, even with huge capacitor (10 µf). Fig. 3 (c) shows the current limiter operation associated with LDO. Threshold current of current limiter is 230 ma. This result shows the LDO goes out of regulation when load current is higher than threshold current and is completely shut down Table I. Summary of the measured performance. 1600

7 near 300 ma. Fig. 3 (d) shows the micrograph of the LDO associated with the proposed LPF and current limiter. The area of the designed LDO with the proposed LPF and current limiter is 228 µm 820 µm. Table 1 shows the summary of the measured performance of the LDO associated with proposed LPF and current limiter. 5 Conclusions A fast settling time low pass filter associated with voltage reference and current limiter for low noise LDO is presented. With fast settling time and a highly filtered low pass filter associated with the voltage reference, the designed LDO achieved low noise and fast turn-on settling time characteristics. The current limiter prevents the LDO from driving overflow current to protect ICs. 1601

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