BASICS: TECHNOLOGIES. EEC 116, B. Baas

Transcription

1 BASICS: TECHNOLOGIES EEC 116, B. Baas 97

2 Minimum Feature Size Fabrication technologies (often called just technologies) are named after their minimum feature size which is generally the minimum gate length For example, 0.13 µm where 1 µm = 1 micrometer = m = 1 micron = 1000 nanometers gate or transistor length top view EEC 116, B. Baas 98

3 Major Technology Nodes Mostly just the primary representative technology nodes with sqrt(2) scaling are shown. Others exist, e.g. 40 nm Area scaling assumes perfect scaling with the minimum feature size which is only approximate DSM = Deep Submicron Technology Approx. Year Relative Area 1.00 µm µm µm µm µm µm µm nm nm nm 2007 H nm 2010 H nm Aug nm Toshiba flash nm ~ nm Jan 2015, Intel i nm 2017? nm?? - EEC 116, B. Baas 99

4 Technology Scaling Linear dimension shrinks by 0.7x/technology generation Every generation can integrate 2x more functions per chip Chip cost does not increase significantly Cost of a function decreases by 2x each generation But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction EEC 116, B. Baas 100

5 Challenges in DSM Digital Design Min. Feat. Size Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution 1/(Min. Feat. Size) Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. EEC 116, B. Baas 101

6 ABSTRACTION OF COMPLEXITY EEC 116, B. Baas 102

7 Abstraction of Design Complexity Design complexity Typically tens of transistors in analog circuits Each is normally hand crafted along with placement and wiring Hundreds of transistors Each can be hand crafted Thousands to 100s of thousands of transistors Must find regularity in structure and exploit it (re-use cells) Ex: memory Millions to billions of transistors Must find high-level regularity in structure and exploit it (reuse modules and subsystems) Ex: System on Chip (SOC) EEC 116, B. Baas 103

8 Design Abstraction Levels SYSTEM FUNCTIONAL UNIT, or MODULE + GATE CIRCUIT S n+ G DEVICE n+ D EEC 116, B. Baas 104

9 Levels Abstraction of Design Devices and Wires Complexity Circuits, for example simulated by Spice Gates, for example simulated by a digital simulator Modules and functional units (e.g., adder, memory, etc.) Sub-systems (e.g., processor, display driver, network interface, etc.) Methods to abstract complexity Sophisticated Computer-Aided-Design (CAD) tools Standard cell libraries EEC 116, B. Baas 105

10 Hierarchical Abstraction Example: While designing at the gate level, we do not consider the circuit inside each gate A C A B B C AND AND AND OR OR Carry-Out EEC 116, B. Baas 106

11 Why Should We Learn About Circuits and Layout Then? The best designers can: Build model abstractions Understand limitations of models Wire or interconnect performance Changes with technology scaling Abstractions limit maximum attainable performance and energy-efficiency Multi-disciplinary view needed Troubleshooting Malfunctions are often at interfaces: Interfaces between modules Unexpected interactions between levels of abstraction; e.g., an abstracted module was used in a way never anticipated EEC 116, B. Baas 107

12 Examples of Design Aspects that Clock distribution Defy Hierarchy Skew in the timing of active clock edges between different clock signals Worst case result: unfixable faults due to signals passing through two registers in one clock cycle Power distribution Sufficient current handling is required for proper operation Adequate noise suppression in the power and ground grids Worst case result: unfixable faults due to power and ground grid droops resulting in outcomes such as: Memory element erasure Unacceptably slow performance (critical in real-time systems) EEC 116, B. Baas 108