CS 6135 VLSI Physical Design Automation Fall 2003

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1 CS 6135 VLSI Physical Design Automation Fall

2 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) Office hours: M56R5 or by appointment Web site: 2

3 Course Information (Cont d) Material: technical papers selected from major EDA (Electronic Design Automation) conference proceedings and journals Grading Policy: Homework: 40% One test: 30% One project: 30% 3

4 Project Pick a research-oriented problem (either an existing one or a pioneering one) in the physical design area. Develop and implement your own algorithm(s); do comparative studies with other existing methods (if there are any). Schedule 1-page proposal due: November 20, 2003 project presentation: to be determined report due: January 5, 2004 You are always welcome to discuss with me about your project during office hours or by appointment. 4

5 Physical Design Physical design is the process of converting a circuit netlist into a geometric description (i.e., determining where to put components and how to connect them). The description is used to manufacture a chip. Objectives: area, performance, and power, etc. Constraints: components may not be too close, and wires cannot cross, etc. 5

6 Computer-Aided Design (CAD) Physical design is very complicated: Millions of components Multiple objectives Multiple constraints Chip designers need help from CAD tools. 6

7 Course Objectives Understanding the problems arising in the physical design of VLSI circuits. Understanding various CAD algorithms for automating the physical design process. 7

8 Course Topics Introduction Partitioning Floorplanning & Placement Routing Other topics 8

9 Target Audience Students who want to be: VLSI CAD Engineers & Researchers Development and Implementation of CAD tools VLSI Designers Designing VLSI chips using CAD tools 9

10 Expected Background Digital Systems Algorithms (or Data Structures) Programming Languages such as C or C++ 10

11 Related Conferences/Journals Major Conferences: - IEEE/ACM Int l Conference on Computer-Aided Design (ICCAD) - ACM/IEEE Design Automation Conference (DAC) - ACM Int l Symposium on Physical Design (ISPD) - Asia and South Pacific Design Automation Conference (ASP-DAC) - Design, Automation and Test in Europe (DATE) - IEEE Int l Symposium on Circuits and Systems (ISCAS) - ACM Int l Symposium on Field Programming Gate Arrays (FPGA) - Others: IEEE Int l Conference on Computer Design (ICCD); IEEE Custom Integrated Circuits Conference (CICC); IEEE Int l ASIC/SOC Conference Major Journals: - IEEE Transactions on Computer-Aided Design (TCAD) - ACM Transactions on Design Automation of Electronic Systems (TODAES) - IEEE Transactions on VLSI Systems (TVLSI) - INTEGRATION: The VLSI Journal - IEEE Transactions on Circuits and Systems (TCS) - IEEE Transactions on Computers (TC) 11

12 Related Books N. Sherwani, Algorithms for VLSI Physical Design Automation, 3rd Edition, Kluwer Academic Publishers, S. M. Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice, McGraw-Hill, M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI Physical Design, McGraw-Hill,

13 Milestones for IC Industry 1947: Bardeen, Brattain & Shockley invented the transistor, foundation of the IC industry. 1952: SONY introduced the first transistor-based radio. 1958: Kilby invented integrated circuits (ICs). 1965: Moore s law. 1968: Noyce and Moore founded Intel. 1971: Intel announced 4-bit 4004 microprocessors (2300 transistors). 1976/81: Apple/IBM PC. 1985: Intel began focusing on microprocessor products. 1987: TSMC was founded. 1991: ARM introduced its first embeddable RISC IP core. 1996: Samsung introduced 1G DRAM. 1998: IBM Austin Res. Lab announced 1GHz experimental microprocessor. 1999/earlier: System-on-chip (SOC) methodology/applications. Intel P-III has 10 million transistors. Semiconductor/IC: #1 key field for advancing into 2000 (Business Week, Jan. 1995). 13

14 VLSI Design Considerations Several conflicting considerations Design complexity: large number of devices/transistors Performance: optimization requirements for high performance Time-to-market: about a 15% gain for early birds Cost: die area, packaging, testing, etc Others: power consumption, noise, reliability, etc 14

15 Moore s Law: Predicting Technology Trends Logic capacity doubles per IC at regular intervals (1965). Logic capacity doubles per IC every 18 months (1975). 15

16 Semiconductor Technology Roadmap Source: Semiconductor Industry Association (SIA), USA, Nov Deep submicron technology: node (feature size) < Current design challenges: complexity (devices & interconnects), noise, power, SOC methodology, test, timing & function verification. Additional challenges beyond 2005: 3D layout, signal skew, design convergence, embedded system, system test, heterogeneous system verification. 16

17 Problems with Future Technology Designs are too complicated to be handled manually Solutions: CAD Hierarchical design Design reuse 17

18 Traditional VLSI Design Cycle 1. System specification 2. Functional design 3. Logical synthesis 4. Circuit design 5. Physical Design 6. Fabrication 7. Packaging Other tasks involved: function/timing verification, etc. 18

19 Traditional VLSI Design Flow 19

20 20

21 Traditional VLSI Design Flow (Cont d) 21

22 Tasks in Physical Design 1. Circuit partitioning 2. Floorplanning, and placement 3. Routing (global and detailed) 4. Compaction 5. Extraction and Verification 22

23 Physical Design Flow 23

24 Design Styles Restricting design styles to reduce complexity. Choosing design style according to design time, performance, size and cost, etc. 24

25 Design Styles (Cont d) 25

26 Design Styles (Cont d) Full-Custom Without any constraints Standard Cell A library of cells of equal height A design consisting of rows of cells Gate Array A design consisting of an array of identical prefabricated gates/cells Routing layers being fabricated on top of the wafer Field Programmable Gate Array (FPGA) Pre-fabricated cells and interconnects Programmable cells and interconnects 26

27 SSI/SPLD Design Style 27

28 Full Custom Design Style 28

29 Standard Cell Design Style 29

30 Gate Array Design Style 30

31 FPGA Design Style Illustrated by a symmetric array-based FPGA: 31

32 FPGA Design Process Illustrated by a symmetric array-based FPGA: 32

33 Comparisons of Design Styles 33

34 Comparisons of Design Styles (Cont d) 34

35 Design-Style trade-offs 35

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