ESE 570: Digital Integrated Circuits and VLSI Fundamentals

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 12, 2016 VLSI Design and Variation Penn ESE 570 Spring 2016 Khanna

2 Lecture Outline! Design Methodologies " Hierarchy, Modularity, Regularity, Locality! Implementation Methodologies " Custom, Semi-Custom (cell-based, array-based)! Design Quality " Variation! Packaging Penn ESE 570 Spring 2016 Khanna 2

3 Three Domain View of VLSI Design Flow at One Level FUNCTIONAL DESIGN Verilog/Spectre Verilog/Cadence Verilog/Spectre Extract Parasitic Elements LAYOUT VERIFICATION 1. Design Rule Check (DRC) 2. Layout Versus Schematic (LVS) Check 3. Post layout simulation (PLS) SPICE Spectre (Spectre) Cadence (Virtuoso) PLS 3

4 Y-Chart Penn ESE 570 Spring 2016 Khanna 4

5 Design Strategies! Metrics for Design Success: " Performance Specs " logical function, speed, power, area " Time to Design " engineering cost and schedule " Ease of Test Generation and Testability " engineering cost, manufacturing cost, schedule! Design is a continuous tradeoff to achieve performance specs with adequate results in the other metrics Penn ESE 570 Spring 2016 Khanna 5

6 Structured Design Strategies! Strategies common for complex hardware and software projects " Hierarchy: Subdivide the design in several levels of submodules " Modularity: Define sub-modules unambiguously and well defined interfaces " Regularity: Subdivide to max number of similar submodules at each level " Locality: Max local connections, keeping critical paths within module boundaries Penn ESE 570 Spring 2016 Khanna 6

7 Modularity! Adds to the hierarchy and regularity! Unambiguous functions! Well defined beahvioural, structural, and physical interfaces! Enables modules to be individually designed and evaluated! Eg. 4b Adder Penn ESE 570 Spring 2016 Khanna 7

8 Hierarchical & Modular 4-bit Adder add4 c add add add add b a + s sum carry sum carry sum carry sum carry c a b c b a co sum carry s co nand inor nor nand nor nand nor nand n v 8

9 Hierarchical & Modular Layout b[3:0] a[3:0] c0 + add co3 s[3:0] b[3] a[3] b[2] a[2] b[1] a[1] b[0] a[0] (0,0) c0 add[3] add[2] add[1] add[0] co3 (100,400) s[3] (100,300) s[2] (100,200) s[1] (100,100) s[1] (0,100) (0,75) (0,25) (0,0) add1 Cell (50,100) b[i] c[i] add[i] a[i] co[i] (50,0) s[i] (100,100) (100,50) (100,0) add4 Module Penn ESE 570 Spring 2016 Khanna 9

10 Floorplanning: Map Structural into Physical Unused die area -> inefficient layout Structural Hierarchy 1 mapped poorly into Physical Hierarchy. Better mapping! Miss-mappings between Structural and Physical Hierarchies usually avoided by using automatic layout system. Penn ESE 570 Spring 2016 Khanna 10

11 Regularity! Design the chip reusing identical modules, circuits, devices.! Regularity can exist at all levels of the design hierarchy " Circuit Level: Uniform transistor sizes rather than manually optimizing each device " Logic Level: Identical gate structures rather than customize every gate " Architecture Level: construct architectures that use a number of identical sub-structures Penn ESE 570 Spring 2016 Khanna 11

12 Locality (Physical)! TIME LOCALITY: modules are synchronized by common clock. " Critical timing paths are kept within module boundaries " Place modules to minimize large or global inter-module signal routes " Take care to realize robust clock generation and distribution " Signal routes between modules with large physical separation need sufficient time to traverse route " Replicate modules, if necessary, to alleviate delay issues caused by long intermodule signal routes. Penn ESE 570 Spring 2016 Khanna 12

13 Implementation Methodologies Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Compiled Cells Ma cro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Penn ESE 570 Spring 2016 Khanna

14 CMOS Chip Design Options Design Time and Cost Decreasing (for a given application) Performance Increasing, Die Area Decreasing, Power Dissipation Increasing (for a given application) Penn ESE 570 Spring 2016 Khanna 14

15 Prewired Arrays Categories of prewired arrays (or field-programmable devices):! Fuse-based (program-once)! Non-volatile EPROM based! RAM based Penn ESE 570 Spring 2016 Khanna

16 Array-Based Programmable Logic I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array I 3 I 2 I 1 I 0 Programmable OR array I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array Programmable AND array Fixed AND array Programmable AND array O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 PLA PROM PAL Indicates programmable connection Indicates fixed connection

17 Programming a PROM 1 X 2 X 1 X 0 : programmed node NA NA f 1 f 0

18 Field-Programmable Gate Arrays Fuse-based FPGA Features Configurable I/O Configurable Logic Programmable Interconnect/routing I/O Buffers Program/Test/Diagnostics Vertical routes I/O Buffers I/O Buffers Rows of logic modules Routing channels I/O Buffers Penn ESE 570 Spring 2016 Khanna

19 Field-Programmable Gate Arrays RAM-based CLB CLB Horizontal routing channel switching matrix Interconnect point CLB CLB Vertical routing channel Penn ESE 570 Spring 2016 Khanna

20 Standard-Cells Based Design! Predominant custom design style! Standardization is achieved at the logic or function level! Specific designs for each gate are developed and stored in a software database of cell library " Bahavioural, structural, and physical domain descriptions per cell! Layout is usually automatically placed and routed using CAD software Penn ESE 570 Spring 2016 Khanna 20

21 Standard Cell Library Contents! SSI logic " nand, nor, xor, inv, buffers, latches, registers! MSI logic " each gate can have multiple implementations to provide proper drive for different fan-outs, eg. standard size, 2x, 4x " decoders, encoders, adders, comparators! Datapath " ALUs, register files, shifters! Memories " RAM, ROM! System level " multipliers, microcontrollers Penn ESE 570 Spring 2016 Khanna 21

22 Cell-based Design (or standard cells) Feedthrough Cell Logic Cell Rows of Cells Functional Module (RAM, multiplier, ) Routing Channel Routing channel requirements are reduced by presence of more interconnect layers Penn ESE 570 Spring 2016 Khanna

23 Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies Penn ESE 570 Spring 2016 Khanna

24 Automatic Cell Generation Random-logic layout generated by CLEO cell compiler (Digital) Penn ESE 570 Spring 2016 Khanna

25 Design Quality! Achieve specifications (static and dynamic)! Die Size! Power dissipation! Testability! Yield and Manufacturability! Reliability Penn ESE 570 Spring 2016 Khanna 25

26 Variation Types!! Many reasons why variation occurs and shows up in different ways Scales of variation "! Wafer-to-wafer, die-to-die, transistor-to-transistor Correlations of variation " Systematic, spatial, random (uncorrelated) Penn ESE 570 Spring Khanna 26

27 Source: Noel Menezes, Intel ISPD2007 Penn ESE 570 Spring Khanna 27

28 Random Transistor-to-Transistor! Random dopant fluctuation! Local oxide variation! Line edge roughness! Etch and growth rates! Transistors differ from each other in random ways Penn ESE 570 Spring Khanna 28

29 Impact! Changes parameters " W, L, t OX, V th! Change transistor behavior " W? " L? " t OX? I DS = µ n C OX " $ # W L %) ' ( V & GS V T )V DS V 2 DS + * 2,. - Penn ESE 570 Spring Khanna 29

30 V th 65nm [Bernstein et al, IBM JRD 2006] Penn ESE 570 Spring Khanna 30

31 Impact of V th Variation?! Higher V th? " Not drive as strongly " I d,vsat (V gs -V th ) " Performance? Penn ESE 570 Spring Khanna 31

32 Impact Performance! V th # I ds # Delay (R on * C load ) Penn ESE 570 Spring Khanna 32

33 Impact of V th Variation?! Lower V th? " Not turn off as well # leaks more # I DS = I S "% W $ L & ( e ' # % $ V GS V T nkt / q & (# ' 1 e % $ # V DS & % ( $ kt / q ' & ( 1+ λv DS ' ( ) Penn ESE 570 Spring Khanna 33

34 Variation! See a range of parameters " L: L min L max " V th : V th,min V th,max Penn ESE 570 Spring Khanna 34

35 Variation! Margin for expected variation! Must assume V th can be any value in range " Speed # assume V th slowest value I on,min =I on (V th,max ) I d,vsat (V gs -V th ) Probability Distribution V TH Penn ESE 570 Spring Khanna 35

36 Variation! See a range of parameters " L: L min L max " V th : V th,min V th,max! Validate design at extremes " Work for both V th,min and V th,max? " Design for worst-case scenario Penn ESE 570 Spring Khanna 36

37 Margining! Also margin for " Temperature " Voltage supply " Aging: end-of-life Penn ESE 570 Spring Khanna 37

38 Process Corners! Many effects independent! Many parameters! With N parameters, " Look only at extreme ends (low, high) " How many cases?! Try to identify the {worst,best} set of parameters " Slow corner of design space, fast corner! Use corners to bracket behavior Penn ESE 570 Spring Khanna 38

39 Simple Corner Example 350mV What happens at various corners? Vthp 150mV 150mV Vthn 350mV Penn ESE 570 Spring Khanna 39

40 Process Corners! Many effects independent! Many parameters! Try to identify the {worst,best} set of parameters " E.g. Lump together things that make slow " Vthn, Vthp, temperature, Voltage " Try to reduce number of unique corners " Slow corner of design space! Use corners to bracket behavior Penn ESE 570 Spring Khanna 40

41 Range of Behavior! Still get range of performances! Any way to exploit the fact some are faster? Probability Distribution Delay Penn ESE 570 Spring Khanna 41

42 Speed Binning Probability Distribution Sell Premium Sell nominal Sell cheap Discard Delay Penn ESE 570 Spring Khanna 42

43 Design Quality! Testability " generation of good test vectors " design of testable chip! Yield and Manufacturability " functional yield " parametric yield! Reliability " threshold variation " premature aging " power and ground bouncing " ESD/EOS -> can compensate in padframe " noise and crosstalk Penn ESE 570 Spring Khanna 43

44 Packaging Technology Penn ESE 570 Spring Khanna 44

45 Package Bonding Techniques Penn ESE 570 Spring Khanna 45

46 Parasitics in an Electronic Package PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Penn ESE 570 Spring Khanna 46

47 Summary of Package Types 47

48 Admin! HW 7 and 8 graded by Friday! EC graded by Monday! Final Project " Design memory (SRAM) " EC for best figure of merits (FOM = Area*Power*Delay 2 ) " # of points depends on teams reported " Can propose extra work for extra credit " Due 4/26 (last day of class) " Everyone gets an extension until 5/6 (day of final exam) " Keep an eye on Piazza for useful information and updates on project handout for clarity Penn ESE 570 Spring 2016 Khanna 48

49 Final Project Schedule! Posted now! April 11 th report teams to instructor! April 14 th extra credit proposals due to instructor! April 26 th final report due " Must be submitted via Canvas! May 6 th extension for reports (also day of final)! All deadline times are midnight that day Penn ESE 570 Spring 2016 Khanna 49

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