Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction

Transcription

1 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30,

2 What is this book all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits i with respect to different quality metrics: cost, speed, power dissipation, and reliability 2

3 Digital it Integrated t Circuits it Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures 3

4 Introduction ti Why is designing digital ICs different today than it was before? Will it change in future? 4

5 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost:? 7,470 5

6 ENIAC - The first electronic computer (1946) EE141 Integrated Digital Circuits2nd 6 Introduction

7 The Transistor Revolution First transistor Bell Labs,

8 The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola

9 Intel 4004 Micro-Processor transistors 1 MHz operation 9

10 Intel Pentium (IV) microprocessor 10

11 Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months 11

12 Moore s Law NCTION LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FU Electronics, April 19,

13 Evolution in Complexity 13

14 Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 Pentium III 10,000 Pentium II Pentium Pro 1,000 i486 Pentium 100 i Source: Intel Projected 14 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

15 Moore s law in Microprocessors Transis stors (MT T) X growth in 1.96 years! 486 P6 Pentium proc Transistors on Lead Microprocessors double every 2 years Year 15 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

16 Die Size Growth 100 Die size (m mm) P6 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law 16 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

17 Frequency Mhz) Freq quency ( Doubles every 2 years 286 P6 Pentium proc Year Lead Microprocessors frequency doubles every 2 years 17 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

18 Power Dissipation 100 Po ower (Wa atts) P6 Pentium proc Year Lead Microprocessors power continues to increase 18 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

19 Power will be a major problem P ower (W Watts) Pentium proc 5KW 18KW 1.5KW 500W Year Power delivery and dissipation will be prohibitive 19 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

20 Power density ) (W/cm2 Density Power Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp 20 Digital EE141 Integrated Circuits 2nd Courtesy, Intel Introduction

21 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) 21

22 Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability ty etc. and There s a Lot of Them! 22

23 Productivity Trends 10,000,000 10, ,000,000 (M) Complex xity Transistor r per Chip 1,000,000 1, , , Logic 1, Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 10,000,000 ty f -Mo. 1,000, ,000 10,000 1, Productivit Trans./Staff P (K) T Source: Sematech Complexity outpaces design productivity 23 Digital EE141 Integrated Circuits 2nd Courtesy, ITRS Roadmap Introduction

24 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases eases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction 24

25 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE n+ D 25

26 Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function 26

27 Cost of Integrated t Circuits it NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area 27

28 NRE Cost is Increasing 28

29 Die Cost Single die Wafer Going up to 12 (30cm) From 29

30 Cost per Transistor cost: -per per-transistor Fabrication capital cost per transistor (Moore s law)

31 Yield Dies per wafer = No. of good chips per wafer Y = 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield π ( wafer diameter/2) 2 π wafer diameter die area 2 die area 31

32 Defects die yield = df defects per unit area die area 1+ α α is approximately 3 α die cost = f (die area) 4 32

33 Some Examples (1994) Chip Metal Line Wafer Def./ Area Dies/ Yield Die layers width cost cm 2 mm 2 wafer cost 386DX $ % $4 486 DX $ % $12 Power PC $ % $ HP PA $ % $73 DEC Alpha $ % $149 Super Sparc $ % $272 Pentium $ % $417 33

34 Reliability Noise in Digital Integrated Circuits i(t) V DD v(t) DD Inductive coupling Capacitive coupling Power and ground noise 34

35 DC Operation Voltage Transfer Characteristic V(y) V OH f V(y)=V(x) VOH = f(vol) VOL = f(voh) VM = f(vm) V M Switching Threshold V OL V OL V OH V(x) Nominal Voltage Levels 35

36 Mapping between analog and digital signals 1 V OH V IH V out V OH Slope = -1 Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V in 36

37 Definition of Noise Margins "1" V OH V OL NM H NM L V IH Undefined Region V IL Noise margin high Noise margin low "0" Gate Output Gate Input 37

38 Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources 38

39 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; 39

40 Regenerative Property out out v 3 f (v) v 3 fin v(v) v 1 v 1 finv(v) v 3 f (v) v 2 v 0 in Regenerative v 0 v 2 in Non-Regenerative 40

41 Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters 5 V (Vo olt) 3 1 v 0 v 1 v 2 Simulated response t (nsec) 41

42 Fan-in and Fan-out N M Fan-out N Fan-in M 42

43 The Ideal Gate V out g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V in 43

44 An Old-time Inverter NM L 3.0 (V) V out V M NM H V in (V) 44

45 Delay Definitions V in 50% t t t t phl t plh V out 90% 50% 10% t t f t r 45

46 Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N 46 p

47 A First-Order RC Network R v out v in C t p = ln (2) τ = 0.69 RC Important model matches delay of inverter 47

48 Power Dissipation i Instantaneous power: p(t)=v(t)i(t)=v = = supply i(t) Peak power: P peak = V supply i peak Average power: 1 P ave = ) T V t+ T supply t+ T p( t dt = t t T i supply ( t) dt 48

49 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p 49

50 A First-Order RC Network R v out v in C L E 0 1 T T Vdd = Pt ()dt = V dd i supply ()dt t = V dd C L dv out = C L V 2 dd E cap T T Vdd = P cap ()dt t = V out i cap ()dt t = C L V out dv out = C 2 L 2 V dd 50

51 Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective p on the challenges and potential solutions is the purpose of this book Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipationi 51