VLSI Design I; A. Milenkovic 1

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1 What is this course all about? CPE/EE 427, CPE 527 VLSI Design I L0: Introduction, Design Metrics Aleksandar Milenkovic ( ) Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability 8/9/2005 VLSI Design I; A. Milenkovic 2 Digital Integrated Circuits Why does it matter? Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures 8/9/2005 VLSI Design I; A. Milenkovic 8/9/2005 VLSI Design I; A. Milenkovic 4 A Brief History 947: First Transistor at Bell Lab [John Bardeen and Walter Brattain] 958: First Integrated circuit at Teas Instruments [Jack Kilby] 965: Moore s Law, Intel [Gordon Moore] 994: Integrated circuits became $00B/year business 200: Industry manufactured 0 8 (one quintillion) transistors (200M per human being) 8/9/2005 VLSI Design I; A. Milenkovic 5 The First Computer The Babbage Difference Engine (82) 25,000 parts cost: 7,470 8/9/2005 VLSI Design I; A. Milenkovic 6 VLSI Design I; A. Milenkovic

2 ENIAC - The first electronic computer (946) The Transistor Revolution Vacuum tube based digital computer The Giant Brain as labeled by the press ENIAC facts Occupied,800 sq. feet Weighted 0 tons 8000 vacuum tubes Application: calculate firing tables for World War II artillery guns First transistor Bell Labs, 948 8/9/2005 VLSI Design I; A. Milenkovic 7 8/9/2005 VLSI Design I; A. Milenkovic 8 The First Integrated Circuits Bipolar logic 960 s ECL -input Gate Motorola 966 IC Evolution SSI Small Scale Integration (early 970s) contained 0 logic gates MSI Medium Scale Integration logic functions, counters LSI Large Scale Integration first microprocessors on the chip VLSI Very Large Scale Integration now offers 64-bit microprocessors, complete with cache memory (L and often L2), floating-point arithmetic unit(s), etc. 8/9/2005 VLSI Design I; A. Milenkovic 9 8/9/2005 VLSI Design I; A. Milenkovic 0 IC Evolution Bipolar technology TTL (transistor-transistor logic), 962; higher integration density ECL (emitter-coupled logic), 974; high-performance MOS (Metal-oide-silicon) although invented before bipolar transistor (925, 95), was initially difficult to manufacture nmos (n-channel MOS) technology developed in late 970s required fewer masking steps, was denser, and consumed less power than equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market. aluminum gates for replaced by polysilicon by early 980 CMOS (Complementary MOS): n-channel and p-channel MOS transistors => lower power consumption, simplified fabrication process Intel 4004 Introduction date: November 5, 97 Clock speed: 08 KHz Number of transistors: 2,00 (0 microns) Bus width: 4 bits Addressable memory: 640 bytes Typical use: calculator, first microcomputer chip, arithmetic manipulation 8/9/2005 VLSI Design I; A. Milenkovic 8/9/2005 VLSI Design I; A. Milenkovic 2 VLSI Design I; A. Milenkovic 2

3 0.8-micron process technology (2,.9,.8,.7,.6,.5, and.4 GHz) Introduction date: August 27, 200 (2,.9 GHz);...; November 20, 2000 (.5,.4 GHz) Level Two cache: 256 KB Advanced Transfer Cache (Integrated) System Bus Speed: 400 MHz SSE2 SIMD Etensions Transistors: 42 Million Typical Use: Desktops and entrylevel workstations 0.-micron process technology (2.5, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 52 KB Advanced Transistors: 55 Million Pentium 4 8/9/2005 VLSI Design I; A. Milenkovic Introduction date: Mid 2002 Caches: 2KB L, 256 KB L2, MB L (on-chip) Clock: GHz Transistors: 22 Million Area: 464mm 2 Typical Use: High-end servers Future versions: 5GHz, 0.-micron technology Intel s McKinley 8/9/2005 VLSI Design I; A. Milenkovic 4 Moore s Law Moore s Law In 965, Gordon Moore noted that the number of transistors on a chip doubled every 8 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 8 months LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 9, /9/2005 VLSI Design I; A. Milenkovic 5 8/9/2005 VLSI Design I; A. Milenkovic 6 Evolution in Compleity Transistor Counts K,000,000 00,000 0,000, Billion Transistors Pentium III Pentium II Pentium Pro i486 Pentium i Source: Intel Projected 8/9/2005 VLSI Design I; A. Milenkovic 7 8/9/2005 VLSI Design I; A. Milenkovic 8 VLSI Design I; A. Milenkovic

4 Moore s law in Microprocessors Die Size Growth Transistors (MT) X growth in.96 years! P6 Pentium proc Transistors on Lead Microprocessors double every 2 years 8/9/2005 VLSI Design I; A. Milenkovic 9 Die size (mm) P6 486 Pentium proc ~7% growth per year ~2X growth in 0 years Die size grows by 4% to satisfy Moore s Law 8/9/2005 VLSI Design I; A. Milenkovic 20 Frequency (Mhz) Frequency Doubles every 2 years P6 Pentium proc Lead Microprocessors frequency doubles every 2 years 8/9/2005 VLSI Design I; A. Milenkovic 2 Power Dissipation 00 P6 Pentium proc Power (Watts) Lead Microprocessors power continues to increase 8/9/2005 VLSI Design I; A. Milenkovic 22 Power (Watts) Power will be a major problem Pentium proc 8KW 5KW.5KW 500W Power delivery and dissipation will be prohibitive 8/9/2005 VLSI Design I; A. Milenkovic 2 Power Density (W/cm2) Power density Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc Power density too high to keep junctions at low temp 8/9/2005 VLSI Design I; A. Milenkovic 24 VLSI Design I; A. Milenkovic 4

5 Technology Directions: SIA Roadmap Not Only Microprocessors Feature size (nm) Logic trans/cm 2 6.2M 8M 9M 84M 80M 90M Cost/trans (mc) #pads/chip Clock (MHz) Chip size (mm 2 ) Wiring levels Power supply (V) High-perf pow (W) Cell Phone Units Digital Cellular Market (Phones Shipped) M 86M 62M 260M 45M (data from Teas Instruments) Small Power Signal RF RF Power Management Analog Baseband Digital Baseband (DSP + MCU) 8/9/2005 VLSI Design I; A. Milenkovic 25 8/9/2005 VLSI Design I; A. Milenkovic 26 Why Scaling? Design Abstraction Levels Technology shrinks by 0.7/generation With every generation can integrate 2 more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2 But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Eploit different levels of abstraction + S n+ SYSTEM MODULE GATE CIRCUIT DEVICE G D n+ 8/9/2005 VLSI Design I; A. Milenkovic 27 8/9/2005 VLSI Design I; A. Milenkovic 28 Microscopic issues ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Tech Major Design Challenges Compleity M Tr. 20 M Tr. 2 M Tr. 0 M Tr. Frequency 400 MHz 500 MHz 600 MHz 800 MHz Macroscopic issues time-to-market design compleity (millions of gates) high levels of abstractions design for test reuse and IP, portability systems on a chip (SoC) tool interoperability Yr. Design Staff Size $90 M $20 M $60 M $60 M 8/9/2005 VLSI Design I; A. Milenkovic Staff Costs 0,000,000 0,000 Compleity Logic Transistor per Chip (M),000,000,000 00, ,000 0, Productivity Trends Logic Tr./Chip Tr./Staff Month %/Yr. compounded Compleity growth rate 2%/Yr. compound Productivity growth rate 8/9/2005 VLSI Design I; A. Milenkovic Source: Sematech 00,000,000 0,000,000,000,000 00,000 0,000, Compleity outpaces design productivity Courtesy, ITRS Roadmap Productivity (K) Trans./Staff - Mo. VLSI Design I; A. Milenkovic 5

6 Fundamental Design Metrics Functionality Cost NRE (fied) costs - design effort RE (variable) costs - cost of parts, assembly, test Reliability, robustness Noise margins Noise immunity Performance Speed (delay) Power consumption; energy Time-to-market 8/9/2005 VLSI Design I; A. Milenkovic Cost of Integrated Circuits NRE (non-recurring engineering) costs Fied cost to produce the design design effort design verification effort mask generation Influenced by the design compleity and designer productivity More pronounced for small volume products Recurring costs proportional to product volume silicon processing also proportional to chip area assembly (packaging) test Fied cost Cost per IC = Variable cost per IC + Volume 8/9/2005 VLSI Design I; A. Milenkovic 2 NRE Cost is Increasing Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law) /9/2005 VLSI Design I; A. Milenkovic 8/9/2005 VLSI Design I; A. Milenkovic 4 Silicon Wafer Recurring Costs Single die Wafer Variable cost = Cost of Die cost die = + Testing cost + Packaging cost Final test yield Cost of Dies per wafer wafer Die yield From Going up to 2 (0cm) 8/9/2005 VLSI Design I; A. Milenkovic 5 8/9/2005 VLSI Design I; A. Milenkovic 6 VLSI Design I; A. Milenkovic 6

7 Dies per Wafer Yield Dies per wafer π (Wafer diameter/2) = Die area 2 π Wafer diameter 2 Die area Die yield Defects per unit area Die area = Wafer yield + α α is approimately 4 die cost = f (die area) α 8/9/2005 VLSI Design I; A. Milenkovic 7 8/9/2005 VLSI Design I; A. Milenkovic 8 Eamples of Cost Metrics (994) Yield Eample Chip 86DX 486DX2 PowerPC 60 HP PA 700 DEC Alpha Super SPARC Pentium Metal layers 2 4 Line width Wafer cost $900 $200 $700 $00 $500 $700 $500 Defects /cm Area (mm 2 ) Dies/ wafer Yield 7% 54% 28% 27% 9% % 9% Die cost $4 $2 $5 $7 $49 $272 $47 Eample #: 20-cm wafer for a die that is.5 cm on a side. Solution: Die area =.5.5 = 2.25cm2. Dies per wafer =.4(20/2)2/ /(22.5)0.5=0. Eample #2 wafer size of 2 inches, die size of 2.5 cm2, defects/cm2, α = (measure of manufacturing process compleity) 252 dies/wafer (remember, wafers round & dies square) die yield of 6% 252 6% = only 40 dies/wafer die yield! Die cost is strong function of die area proportional to the third or fourth power of the die area 8/9/2005 VLSI Design I; A. Milenkovic 9 8/9/2005 VLSI Design I; A. Milenkovic 40 Functionality and Robustness Prime requirement IC performs the function it is designed for Normal behavior deviates due to variations in the manufacturing process (dimensions and device parameters vary between runs and even on a single wafer or die) presence of disturbing on- or off-chip noise sources Noise: Unwanted variation of voltages or currents at the logic nodes 8/9/2005 VLSI Design I; A. Milenkovic 4 i(t) Reliability Noise in Digital Integrated Circuits v(t) Inductive coupling Capacitive coupling Power and ground noise from two wires placed side by side inductive coupling current change on one wire can influence signal on the neighboring wire capacitive coupling voltage change on one wire can influence signal on the neighboring wire cross talk 8/9/2005 VLSI Design I; A. Milenkovic 42 V DD from noise on the power and ground supply rails can influence signal levels in the gate VLSI Design I; A. Milenkovic 7

8 Eample of Capacitive Coupling Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology Black line quiet Red lines pulsed Glitches strength vs technology Pulsed Signal 0.2m CMOS 0.6m CMOS 0.25m CMOS 0.5m CMOS From Dunlop, Lucent, /9/2005 VLSI Design I; A. Milenkovic 4 Static Gate Behavior Steady-state parameters of a gate static behavior tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances. Digital circuits perform operations on Boolean variables {0,} A logical variable is associated with a nominal voltage level for each logic state V OH and 0 V OL V() V(y) Difference between V OH and V OL is the logic or signal swing V sw V OH =! (V OL ) V OL =! (V OH ) 8/9/2005 VLSI Design I; A. Milenkovic 44 V(y) V OH = f (V IL ) DC Operation Voltage Transfer Characteristic f V() V(y) V(y)=V() V OH = f(v OL ) V OL = f(v OH ) V M = f(v M ) Mapping between analog and digital signals The regions of acceptable high and low voltages are delimited by VIH and VIL that represent the points on the VTC curve where the gain = - (dvout/dvin) V OH V IH V OH Slope = - Switching Threshold Undefined Region V M V OL = f (V IH ) V IL Slope = - V IL V IH V() 0 V OL V OL V IL V IH 8/9/2005 VLSI Design I; A. Milenkovic 45 8/9/2005 VLSI Design I; A. Milenkovic 46 Definition of Noise Margins For robust circuits, want the 0 and intervals to be as large as possible V DD V DD The Regenerative Property A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level V OH "" v 0 v v 2 v v 4 v 5 v 6 NM H = V OH -V IH Noise Margin High V IH Undefined Noise Margin Low Region V IL NM L = V IL -V OL V OL "0" Gnd Gnd Gnd Gate Output Gate Input Large noise margins are desirable, but not sufficient 8/9/2005 VLSI Design I; A. Milenkovic 47 V (volts) v 5 2 v 0 v t (nsec) 8/9/2005 VLSI Design I; A. Milenkovic 48 VLSI Design I; A. Milenkovic 8

9 ( V ) o u t V Conditions for Regeneration v 0 v v 2 v v 4 v 5 v 6 v v v 2 f(v) v = f(v 0 ) v = finv(v 2 ) v 0 finv(v) Regenerative Gate 8/9/2005 VLSI Design I; A. Milenkovic 49 v v v 0 finv(v) v 2 f(v) Nonregenerative Gate To be regenerative, the VTC must have a transient region with a gain greater than (in absolute value) bordered by two valid zones where the gain is smaller than. Such a gate has two stable operating points. Noise Immunity Noise margin epresses the ability of a circuit to overpower a noise source noise sources: supply noise, cross talk, interference, offset Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity epresses the ability of the system to process and transmit information correctly in the presence of noise For good noise immunity, the signal swing (i.e., the difference between V OH and V OL ) and the noise margin have to be large enough to overpower the impact of fied sources of noise 8/9/2005 VLSI Design I; A. Milenkovic 50 Directivity Fan-In and Fan-Out A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs) Fan-out number of load gates connected to the output of the driving gate gates with large fan-out are slower N Key metrics: output impedance of the driver and input impedance of the receiver ideally, the output impedance of the driver should be zero input impedance of the receiver should be infinity Fan-in the number of inputs to the gate gates with large fan-in are bigger and slower M 8/9/2005 VLSI Design I; A. Milenkovic 5 8/9/2005 VLSI Design I; A. Milenkovic 52 The Ideal Inverter The ideal gate should have infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp An Old-time Inverter NM L g = - R i = R o = 0 Fanout = V M NM H NM H = NM L = VDD/ (V) 8/9/2005 VLSI Design I; A. Milenkovic 5 8/9/2005 VLSI Design I; A. Milenkovic 54 VLSI Design I; A. Milenkovic 9

10 Delay Definitions Delay Definitions input waveform Propagation delay? input waveform 50% Propagation delay t p = (t phl + t plh )/2 t t phl t plh t 90% output waveform signal slopes? output waveform 50% signal slopes t t f 0% t r t 8/9/2005 VLSI Design I; A. Milenkovic 55 8/9/2005 VLSI Design I; A. Milenkovic 56 Modeling Propagation Delay Model circuit as first-order RC network v in R C v out v out (t) = ( e t/τ )V where τ = RC Time to reach 50% point is t = ln(2) τ = 0.69 τ Power and Energy Dissipation Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates supply line sizing (determined by peak power) P peak = V dd i peak battery lifetime (determined by average power dissipation) p(t) = v(t)i(t) = V dd i(t) P avg = /T p(t) dt = V dd /T i dd (t) dt packaging and cooling requirements Two important components: static and dynamic Time to reach 90% point is t = ln(9) τ = 2.2 τ Matches the delay of an inverter gate 8/9/2005 VLSI Design I; A. Milenkovic 57 E (joules) = C L V 2 dd P 0 + t sc V dd I peak P 0 + V dd I leakage f 0 = P 0 * f clock P (watts) = C L V dd2 f 0 + t sc V dd I peak f 0 + V dd I leakage 8/9/2005 VLSI Design I; A. Milenkovic 58 Power and Energy Dissipation Propagation delay and the power consumption of a gate are related Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors the faster the energy transfer (higher power dissipation) the faster the gate For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant Power-delay product (PDP) energy consumed by the gate per switching event An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is Energy-delay product (EDP) = power-delay 2 Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this course Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation 8/9/2005 VLSI Design I; A. Milenkovic 59 8/9/2005 VLSI Design I; A. Milenkovic 60 VLSI Design I; A. Milenkovic 0