Jan Rabaey, «Low Powere Design Essentials," Springer tml

Transcription

1

2

3 Jan Rabaey, «e Design Essentials," Springer tml Dimitrios Soudris, Christian Piguet, and Costas Goutis, Designing CMOS Circuits for Low POwer, Kluwer Academic Publishers, Sept A. Chandrakasan and R. Brodersen, CMOS Design, Kluwer Academic Publishers, 1995 J. Rabaey and M. Pedram, Ed., Design Methodologies, Kluwer Academic Publishers, 1995 Design Course 2

4 High Volume Manufacturing Technology Node (nm) Integration Capacity (10 9.T) Delay = CV/I scaling Σχήμα 4: Επερτόμενες τετνολογίες κατασκεσής ολοκληρωμένων κσκλωμάτων. Energy/Logic Op scaling ~0.7 >0.7 Delay scaling will slow down >0.3 5 >0.5 >0.5 Energy scaling will slow down Variability Medium High Very High [Shekhar Borkar, Intel

5 Emerging Technologies for fabricating integrated systems Design Course 4

6 To present low power estimation and optimization design methodologies and techniques at all design levels: System/Behavioral Level Architecture/Register-Transfer Level Logic Level Circuit/Transistor Level Aspects from System-On-Chip Design Course 5

7 Power is the rate at which energy is delivered or exchanged» electrical energy is converted to heat energy during operation Power Dissipation - rate at which energy is taken from the source (V dd ) and converted into heat Design Course 6

8 Large Market of Portable devices e.g. laptops, mobile phones Achieve larger transistor integration Teraflops Research Chip contains 1.9 bimillion transistors Need for green computers 10% of total electrical energy consumed by PCs Design Course 7

9 Battery Technology Improvements Design Course 8

10 Power Evolution over Technology Generations Design Course 9

11 Design Course 10

12 Design Course

13 Design Course 12

14 Design Course 13

15 Design Course 14

16 Design Course 15

17 Design Course 16

18 Design Course 17

19 Reduce chip capacitance through process scaling ==> Expensive Reduce Voltage levels from 5V 3.3V 2V ==> Industry is hard to move (microprocessors, memory,...) Better Circuit Techniques ==> Gated clocks, Power-Down of non-operational units Example: IBM 80 MHz PowerPC RISC (3 3.3V) Power Management Logic determines activity on per cycle basis Clocks of idle blocks are turned off 12-30% savings Doze - Nap and Sleep mode (5 mw) Design Course 18

20 Pentium-1: 15 Watt (5V - 66MHz) Pentium-2: 8 Watt (3.3V- 133 MHz) Design Course 19

21 Design Course 20

22 Year Feature size (nm) Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) #pads/chip Clock (MHz) Chip size (mm 2 ) Wiring levels Power supply (V) High-perf pow (W) Battery pow (W) Design Course 21

23 Design Course 22

24 The power consumption in digital CMOS circuits P avg = P dynamic + P short-circuit + P leakage Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage (Static) Leaking diodes and transistors Design Course 23

25 2 dynamic L dd P C V N f where V DD supply voltage, C L capacitance, N is the average number of transitions per clock cycle, and f frequency operation V dd V dd V dd Charging current IN OUT OUT OUT C L C L C L Discharging current (a) (b) (c) Design Course 24

26 Dynamic Power Consumption (2) For technologies up to 0.35 m, the dynamic consumption is about 80% of the total consumption Goal ===> reduce dynamic power consumption reduction capacitance reduction of supply voltage reduction of frequency reduction of switching activity or combination of above factors Design Course 25

27 Power = Energy/transition * transition rate = C L * V dd 2 * f 0 1 = C L * V dd 2 * P 0 1 * f = C EFF * V dd 2 * f Power Dissipation is Data Dependent Function of Switching Activity C EFF = Effective Capacitance = C L * P 0 1 Design Course 26

28 Power Consumption is Data Dependent Example: Static 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=1) = 1/4 P(0 1) = P(Out=0).P(Out=1) = 3/4 1/4 = 3/16 C EFF = 3/16 * C L Design Course 27

29 The short circuit power, is caused by the direct path from the power supply to ground, during the transition phase where K is a constant that depends on the transistor sizes and the technology, Vt is the threshold voltage of the nmos and pmos transistors, is the rise or fall time of the input signal, N is the average number of transitions in the inverter s output, and f is the clock frequency. 3 Pshort circuit K ( Vdd 2Vt ).. N. f Design Course 28

30 the reverse-bias diode leakage at the transistor drains and the sub-threshold current through an turnedoff transistor channel Log I D gate p+ p+ n-type substrate + V dd leakage current reversed-biased diode (drain-substrate) The leakage of a reverse-biased pmos transistor Subthreshold region Saturated region Decreasing V DS, V dd V GS, volts Subthreshold leakage with respect to gate-source voltage Design Course 29

31 30

32 the reverse-bias diode leakage at the transistor drains and the sub-threshold current through an turnedoff transistor channel Log I D gate p+ p+ n-type substrate + V dd leakage current reversed-biased diode (drain-substrate) The leakage of a reverse-biased pmos transistor Subthreshold region Saturated region Decreasing V DS, V dd V GS, volts Subthreshold leakage with respect to gate-source voltage Dimitrios Soudris, DUTH 31

33 Power consumption of transfer and storage over datapath operations both in hardware [Men95] and software [Tiw94, Gon96]. 33 relative energy/operation relative energy bit carry-select 16-bit Multiplier 8x128x16 SRAM (read) 8x128x16 SRAM (write) External I/O Access 16 bit Memory Access Storage Interconnect clocks Other RISC components Dimitrios Soudris, 32

34 Increasing power savings System level x Behavior level RT level 2-5 x Logic level Transistor level 20-50% Layout level Design Course 33

35 Algorithm Transformation to exploit concurrency Architecture Parallelism and Pipelining Circuit/Logic Transistor Sizing, Fast Logic Structures Technology Threshold Voltage Reduction, Feature Size scaling Design Course 34

36 Syste m U Partitioning, Powe r-down, powe r state s Algorithm C omple xity, C oncurre ncy, Re gularity, Locality, Data re pre se ntation Archite cture C oncurre ncy, Instruction se t se le ction, Signal corre lations, Data re pre se ntation, Data Encoding C ircuit/logic Transistor siz ing, Logic optimiz ation, Powe r down, Layout O ptimiz ation Te chnology Advance d packaging, SO I Design Course 35

37 System Specifications System Specifications System-Level Design System-Level Design System-Level Analysis/Estimation Power models f or System -level com ponents Architecture-Level Design Logic-Level Design Architecture-Level Design Architecture-Level Analysis/Estimation Power models f or macrocells, control logic Logic-Level Design Circuit-Level Design / Layout synthesis Logic-Level Analysis/Estimation Power models f or gates, cells (a) Circuit-Level Design / Layout synthesis Circuit-Level Analysis/Estimation (b) Design Course 36

38 multiplier clock generator 2.0 m technology T d = C L * V dd I NORMALIZED DELAY adder ring oscillator adder (SPICE) microcoded DSP chip T d(vdd=2) = (2) * (5-0.7) 2 T d(vdd=5) I ~ (V dd - V t ) 2 4 (5) * (2-0.7) V dd (volts) Relatively independent of logic function and style. Design Course 37

39 NORMALIZED POWER-DELAY PRODUCT quadratic dependence 51 stage ring oscillator 8-bit adder Vdd (volts) P x t d = E t = C L * V dd 2 E (Vdd=2) = E (Vdd=5) (C L ) * (2) 2 (C L ) * (5) 2 E (Vdd=2) 0.16 E (Vdd =5) Strong function of voltage (V 2 dependence). Relatively independent of logic function and style. Power Delay Product Improves with lowering V DD. Design Course 38

40 Delay I D 2V t V dd V t = 0 V t = 0.2 V GS Reduces the Speed Loss, But Increases Leakage Interesting Design Approach: DESIGN FOR P Leakage == P Dynamic Design Course 39

41 Lower Capacitance Small W/L s Higher Voltage Higher Capacitance Large W/L s Lower Voltage Larger sized devices are useful only when interconnect dominated. Minimum sized devices are usually optimal for low-power. Design Course 40

42 Global bus architecture Local bus architecture Shared Resources incur Switching Overhead Design Course 41

43 Power Consumption is Data Dependent Example: Static 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=1) = 1/4 P(0 1) = P(Out=0).P(Out=1) = 3/4 1/4 = 3/16 C EFF = 3/16 * C L Design Course 42

44 Design Course 43

45 A X B Z Reconvergence P(Z=1) = P(B=1). P(X=1 B=1) Becomes complex and intractable real fast Design Course 44

46 V DD M p Out In 1 In 2 In 3 PDN M e Power is Only Dissipated when Out=0! C EFF = P(Out=0).C L Design Course 45

47 Example: Dynamic 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=0) = 3/4 C EFF = 3/4 * C L Switching Activity Is Always Higher in Dynamic Circuits Design Course 46

48 Switching Activity for Precharged Dynamic Gates P 0 1 = P 0 Design Course 47

49