Advanced Digital Design
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1 Advanced Digital Design Introduction & Motivation by A. Steininger and M. Delvai Vienna University of Technology
2 Outline Challenges in Digital Design The Role of Time in the Design The Fundamental Design Problem A Simple Communication Model Basic Design Strategies - Overview The Timed Communication Model Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 2
3 The market demands faster chips ( performance ) smaller chips ( embedded ) cheaper products ( consumer prod. ) more functions ( features ) battery supply ( mobile ) robust operation ( reliable ) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 3
4 Technology s Answer Miniaturization makes chips faster smaller cheaper more complex & powerful (ultimately) more power-hungry more error-prone Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 4
5 The Chip Design Crisis hard physical limits impede miniaturization designer productivity gap hard physical limits impede speed-up heat problems short time-to-market power delivery problems increasing transient fault rates excessive test complexity increasing NRE costs Do we need a new ( revolutionary ) design approach? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 5
6 The MOS Transistor n-channel enhancement FET contacts gate oxide n+ T OX L W substrate channel Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 6
7 Scaling Theory Scaling technology by α scales area by 1/α 2 transistor current by 1/α transistor power by 1/α 2 power density (pwr/area) by 1 This is no more true for tech- nology nodes below 100nm! Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 7
8 Static Power Consumption gate tunnel currents (currents over gate oxide) grow exponentially for thinner oxide subthreshold currents (currents over open transistor) grow for lower threshold voltage leakage currents (currents over reverse biased junction) can be decreased by SIO, e.g. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 8
9 Dynamic Power Consumption switching currents (loading parasitic capacitances) P switch = f clk C V 2 DD crowbar currents (imperfect stack switching) Pcrowbar f clk Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 9
10 Power Consumption Trends processor power [W] dynamic static [Furuyama, DSD 06] Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 10
11 Limits of Miniaturization charge of an electron does not scale e = -1, C size of an atom does not scale Si-Atom = 0.05nm wave length for lithography does not scale λ UV >150nm statistics of band model does not scale: invalid for small populations (doping) exponential growth of tunnel currents linear growth of electrical field strength Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 11
12 Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 12
13 EM Wave Propagation Electrical signals and their associated electromagnetical (EM) waves travel at the speed of light. In vacuum this speed is 3 x 10 8 m/s, that is approx km/h or 30cm/ns. In media the speed of light depends on μ r and ε r and is always lower than in vacuum.. A typical value for a cable is 2/3 of the speed of light, that is 20cm/ns. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 13
14 Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 14
15 Capacitor Charging Process Step response of an RC lowpass exponential voltage curve u (t) c U s Time Constant τ determines timing scale 0,632Us τ 2τ t is the product of R and C. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 15
16 The RC-Charging Charging Curve u (t) c U in U C U s 0,632Us τ = RC τ 2τ Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 16 t
17 Delay caused by RC u (t) c Delay τ U s 0,632Us 65% (Threshold) τ 2τ t Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 17
18 Which R s and C s? Resistance (R) of the conducting FET (Drain( Drain/Source) the interconnect (Al, Cu) the vias the programming elements Capacitance (C) of conducting parts mutually structures of one/different FETs interconnect Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 18
19 Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 19
20 The Diffusion Process When opening/closing a FET switch charges must be removed from/moved moved to the channel. This occurs much slower than with the speed of light: The saturation value for the diffusion speed in silicon is 0.1mm/s, which is km/h, or 0.5% of the speed of light (in medium). Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 20
21 Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Fundamental law of physics Charging effects Charging of a capacitance with limited current takes time. inevitable Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. material-immanent immanent Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 21
22 Resume 1 Propagation & processing of information is inevitably associated with a delay This delay may be minimized, but will never become zero. Although this delay appears to be very small, it constitutes the major limitation for the speed of digital circuits, therefore it IS relevant. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 22
23 Power Delivery Problems need to deliver currents of many amps into chip extreme current density in bondings & power rails need to supply huge current spikes within ps parasitic inductances critical buffer capacitances required noise margins reduced Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 23
24 Time-to to-market needs to be ever shorter rapidly changing standards last minute availability of crucial components/specs specs exploit market opportunities being late causes tremendous loss of profit Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 24
25 Productivity Gap log trans/chip +59%/a (Moore) trans/staff/time +21%/a t [ITRS] We cannot design as complex chips as we could manufacture need much better tool support need to combine pre-designed modules Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 25
26 Test & Verification 70% of time spent on verification It will soon cost more to test a transistor than to manufacture it log cost/trans test costs -29%/a const t [ITRS] Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 26
27 Transient Faults occur times more often than permanent faults today originate from storage elements being upset can only be caused by disturbances with an energy larger than that stored in the affected cell are often caused by particle hits (single event upsets: SEUs) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 27
28 Fault Rate Predictions energy stored in a storage element scales with feature size power supply energy distribution of particles is non-linear significantly more particles towards lower energy fault potential largely increases with every technology node Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 28
29 Fault Mitigation stopping miniaturization is not an option technology (materials( materials, shielding, ) keeps fault rate per transistor constant = still overall increase per chip robust circuit design requires different design techniques system-level fault tolerance current solution expensive Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 29
30 Ideal Design Method An ideal design method minimizes power consumption miminizes circuit overhead naturally supports composability naturally aids testability yields robust circuits yields fast circuits. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 30
31 Solutions ahead? Many people envision a paradigm shift as the only solution As the pain grows so does the willingness to perform such a shift so does the incentive to come up with a novel solution Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 31
32 The Role of Time in Digital Design Assumptions behind common practice
33 Boolean Logic unambiguous time-free description combinational logic truth table, e.g. sequential logic state diagram, e.g.. (sequence( sequence) independent of implementation temporal relations are not relevant (but for sequence) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 33
34 Implementation There is a signal delay in all transistors through all interconnect this signal delay cannot be eliminated is indeterministic Why? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 34
35 Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Fundamental law of physics Charging effects Charging of a capacitance with limited current takes time. inevitable Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. material-immanent immanent Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 35
36 Delay Contributors Gate Delay propagation delay through a logic element largely independent from routing quite predictable Interconnect Delay propagation delay on a signal line very dependent on routing scarcely predicatble Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 36
37 Delay Trends delay [ns] 1.0 gate interconnect λ [μm] Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 37
38 Can we predict Delay? after synthesis: logic depth complexity of operation optimization & mapping after routing: interconnect geometrie (lengths, capacitances) vias, switches during operation: actual values process variations temperature supply voltage Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 38
39 Resume 2 Signal delay is not only extremely difficult to predict, it varies with the operating conditions. The delays along two individual signal paths will never be the exactly the same. The (maximum) difference among two or more signal paths of interest which is termed skew is even more difficult to predict. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 39
40 Skew and Consistency Data consistency When individual data items are interpreted together (to attain a more global, comprehensive view), these must belong to the same context: they must be temporally correlated Example: speeds of wheels combined to derive dynamic state of vehicle Skew distorts temporal correlation Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 40
41 Consistency an Example sending Delay receiving Skew receiving Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 41
42 Consistency & Glitches A 10 ΔT Y = A A 0 0 Everything OK for the steady state A dynamicanalysisrevealsglitches! Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 42
43 Boolean Logic unambiguous time-free description combinational logic truth table, e.g. sequential logic state diagram, e.g.. (sequence( sequence) independent of implementation temporal relations are not relevant (but for sequence) cannot be expressed! Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 43
44 The Consequences Boolean Logic describes the I/O-mapping without consideration of time A 0 B 0 C 0 F 0 This implies continuously valid inputs Skew inevitably causes inconsistency at the inputs and hence invalid dynamic states A Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 44
45 Resume 3 In practice temporal relations DO matter for a design. Boolean logic is not capable of expressing them. We need other means of introducing the missing information. This is exactly the purpose of a design style. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 45
46 The Fundamental Problem of Digital Design - a communication problem
47 What we actually need When can SNK use its input? When it is valid and consistent SRC f(x) SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 47
48 Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 48
49 Conclusion The purpose of a design style is to provide information for flow control. Boolean Logic alone cannot provide this information. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 49
50 Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 50
51 Timed Comm.. Model Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 51
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