Advanced Digital Design
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1 Advanced Digital Design The Synchronous Design Paradigm A. Steininger Vienna University of Technology
2 Outline The Need for a Design Style The ideal Method Requirements The Fundamental Problem Timed Communication Model Synchronous Design as a Solution Pros & Cons of Synchronous Design Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 2
3 recall Why a Design Stlye? Skew is inevitable and unpredictable It causes inconsistent transient states Their logic evaluation causes glitches Boolean Logic forms a digital abstraction, assuming continuous signal validity & consistency In addition, we need a design style to maintain these abstractions in the presence of skew Lecture "Advanced Digital Design" A. Steininger / TU Vienna 3
4 recall Without a Design Style combinational gates may, due to race conditions, receive contradictory inputs simultaneously, hence create glitch or runt pulses that may be converted into erroneous stable states or even cause metastability in storage loops. These glitches, runts and/or manifestations of metastability may propagate, and they may be subject to Byzantine interpretation, causing further erroneous states. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 4
5 The Chip Design Crisis hard physical limits impede miniaturization designer productivity gap hard physical limits impede speed-up heat problems short time-to-market power delivery problems increasing transient fault rates excessive test complexity increasing NRE costs Do we need a new ( revolutionary ) design approach? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 5
6 A Fair Comparison Severe technological problems force us to question the synchronous design practice. Alternatives must be critically evaluated with respect to improvements concerning area ( embedded, intelligent, cost ) power (mobile devices, heat, ) performance (as always) designability (efficient design of complex sys.) verifiability (test & validation cost!) robustness (critical apps, higher fault rates, ) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 6
7 Performance Performance has been improved by Transistor scaling (technology) Architectrural advances (pipelines, caches, prediction, ) Parallelization (vector operations, multicore, ) The design style has remained unchanged! Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 7
8 Verification Need to make sure that implementation matches specification: all desired functions available no undesired behavior 70% of time spent on verification Model-based approach: spec transformed into (high-level) model model properties formally verified model is implemented in HW & SW BUT: how check implementation vs. model?? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 8
9 Test Test complexity rises with more than O(n 2 ) with circuit complecity It will soon cost more to test a transistor than to manufacture it log test costs const t [ITRS] Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 9
10 Transient Faults occur times more often than permanent faults today originate from storage elements being upset (directly or indirectly) can only be caused by disturbances with an energy larger than that stored in the affected cell are often caused by particle hits (single event upsets: SEUs) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 10
11 Fault Rate Predictions energy stored in a storage element scales with feature size power supply energy distribution of particles is non-linear significantly more particles towards lower energy fault potential largely increases with every technology node Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 11
12 Fault Mitigation stopping miniaturization is not an option technology (materials, shielding, ) reduces fault rate per transistor but still overall increase per chip robust circuit design Several techniques applied, but Design style not changed system-level fault tolerance current solution, expensive (typ. 3x) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 12
13 A First Summary An ideal design method minimizes power consumption miminizes area overhead naturally supports intuitive design naturally aids testability yields robust circuits yields fast circuits. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 13
14 Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 14
15 What we actually need completion detection problem When can SNK use its input? When it is valid and consistent SRC f(x) SNK When can SRC apply the next input? When SNK has consumed the previous one input/output mode operation, requires indication principle Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 15
16 Timed Comm. Model contamination delay for details see: M. Delvai, A. Steininger. Solving the fundamental Problem of Digital Design A Systematic Review of Design Methods, 9th Euromicro Conference on System Design, Dubrovnik Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 16
17 The Capture Condition Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: t cons,x > t snkrdy,x µ snk > - snktrg Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 17
18 The Issue Condition Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: t invalid,x > t safe,x µ src > - invalid Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 18
19 Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 19
20 Control by Global Time Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 20
21 The Synchronous Concept FF1 f(x) FF2 T Clk Pure time domain solution: use periodic clock edges to derive triggers for SRC & SNK; determine period such that capture condition and issue condition are always fulfilled. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 21
22 Synchr. Timing Model How does the synchronous design fit into the timing model of global time? What is π? What is ϕ? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 22
23 The Implications Clock Period T Clk = Period π determined by static timing analysis Free choice of µ snk : capture condition Phase ϕ = π (!) this implies that µ src = -( snktrg + cons ) still we must guarantee µ src > - invalid (issue condition) Therefore it must hold that invalid > snktrg + cons (No freedom to choose!) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 23
24 Benefits of Sync. Logic Simplicity improves productivity time is considered discrete (!) design on high level of abstraction transients are irrelevant, all considered states are clearly defined timing analysis separate, after design clear distinction between data & clock Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 24
25 Benefits of Sync. Logic (2) High implementation efficiency: one single control signal for the complete system! periodic clock is easy to generate single-rail data coding minimum number of transitions on the data rails clock also provides a time base Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 25
26 Resume 1 Synchronous design does work billions of working designs Synchronous design is VERY efficient wrt. design (intuition) wrt. implementation (area) So everything is solved Is it? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 26
27 recall The Original Problem When can SNK use its input? When it is valid and consistent SRC f(x) SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 27
28 recall What have we done? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 28
29 That damned traffic light YES! It does matter Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 29
30 That damned Traffic light number of waiting cars Microwave oven temperature of the food Wiper visibility through the front shield Stairway light presence of a person in the stairway Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 30
31 What s wrong? As time is easy to measure, a projection is often made for the relative time between the occurrence of an event in the past and one expected in the future instead of directly observing the latter. This requires a model to be established, expressing how the quantity of interest relates to time. This becomes annoying when this artificial relation between actual event and time is so weak that either the model prediction gets too fuzzy, or the model too complicated. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 31
32 Pre-Determined Timing Designer User projected conditions system model?(unknown) worst case?(imperfections) safety margins actual conditions actual system Timing completely fixed after design No way to react to actual conditions & system Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 32
33 The Synchronous Approach FF1 f(x) FF2 T Clk After some TIME T clk FF2 can use f(x) s output and at the same time FF1 can apply a new input Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 33
34 The annoying consequences need to determine clock period circuit functionality is technology dependent substantial design efforts, large design loops need to make worst-case assumptions necessarily pessimistic (corner cases) still no robustness wrt. exceeding them need to maintain global synchrony clock distribution problems (skew!) power consumption problems Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 34
35 Timing Analysis not possible before the end of the design flow (large iteration loops!) gate delays interconnect delays P-variations VT-variations Specification Design-Entry Synth. & Technol.-Mapping Partitioning & Placement Routing Manufact. Operation Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 35
36 Worst-Case Assumptions normally too pessimistic real, chip could run faster no tolerance when exceeded graceful degradation desirable Η(α) α lim α Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 36
37 The Clock Skew Problem What happens if we move SRC time against SNK time? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 37
38 Sync. Design Properties Area: + single rail encoding, single clock line - clock network Power: + small, efficient circuit - clock net, permanent concurrent switching Performance: + pure feed-forward flow control - worst case design, safety margins Designability: + good abstraction level for logic - timing analysis complex, composability? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 38
39 Robustness metastability Issues clock = single point of failure non-redundant signal coding no graceful degradation timing margins help masking faults but they are shrinking! synchrony is a very strong assumption it takes a lot of efforts to maintain it assumption coverage is lower Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 39
![Experimental Results Fault Injection Results for SPEAR [Thesis Rahbaran] PhD Delvai: Design asynchronous processor SPEAR PhD Huber: Design Flow](/docs-images/76/73626788/images/40-2.jpg "& Validation asyn SPEAR PhD Rahbaran: Robustness Comparison syn/asyn Lecture \"Advanced Digital Design\" A. Steininger & M. Delvai / TU Vienna 40")
40 Experimental Results Fault Injection Results for SPEAR [Thesis Rahbaran] PhD Delvai: Design asynchronous processor SPEAR PhD Huber: Design Flow & Validation asyn SPEAR PhD Rahbaran: Robustness Comparison syn/asyn Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 40
41 Fault Masking Effects electrical masking too short fault pulse is filtered out by (parasitic) low-passes logical masking faults on masked gate inputs are irrelevant temporal masking signal values are considered only shortly before/during latching window; faults go unrecognized when outside Diploma thesis: Fault masking syn vs. asyn 0 & 0 Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 41
42 Testability Test Pattern Generator register chain register chain comb logic comb logic comb logic register chain Response Analysis Scan test turns sequential problem into combinational one => hard to beat! Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 42
43 Conclusion An analysis of the data transfer process allows mapping the trigger conditions for data source and sink to the time domain, yielding an issue condition and a capture condition. A convenient mapping to a purely time based solution is used by some design styles, in particular the synchronous design. This mapping is, however, not natural. As an alternative signal coding may be used to control the triggers of source and sink. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 43
44 Conclusion Synchronous design is extremely efficient wrt. design and testing. It builds on a relation between handshake events and time that becomes increasingly cumbersome. Weak points are inherent robustness and composability Power efficiency, area efficiency and performance efficiency are very good in principle, but limitations in clock distributions tend to foil these benefits. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 44
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