Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits
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1 Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits Dan Holcomb Wenchao Li Sanjit A. Seshia Department of EECS University of California, Berkeley Design Automation and Test in Europe, 2009 Holcomb, Li, Seshia Design as You See FIT 1
2 Soft errors in VLSI circuits Spurious radiation-induced flip of one or more stored bits Does not permanently damage devices Measured in units of FIT; 1 FIT is 1 failure in 10 9 hrs Strikes to logic or directly to memory Holcomb, Li, Seshia Design as You See FIT 2
3 Soft errors in VLSI circuits Spurious radiation-induced flip of one or more stored bits Does not permanently damage devices Measured in units of FIT; 1 FIT is 1 failure in 10 9 hrs Strikes to logic or directly to memory Logic FIT may increase 9 orders of magnitude from [Shivakumar 02] Logic FIT approaching memory FIT around 100nm [Shivakumar 02, Baumann 05] Circuit-level hardening techniques exist, but have costs Holcomb, Li, Seshia Design as You See FIT 2
4 Our contribution the verification guided error resilience methodology Use formal specifications to capture system-level correctness Holcomb, Li, Seshia Design as You See FIT 3
5 Our contribution the verification guided error resilience methodology Use formal specifications to capture system-level correctness Use verification to analyze system-level impact of circuit-level upsets Holcomb, Li, Seshia Design as You See FIT 3
6 Our contribution the verification guided error resilience methodology Use formal specifications to capture system-level correctness Use verification to analyze system-level impact of circuit-level upsets Guide efficient circuit hardening techniques Holcomb, Li, Seshia Design as You See FIT 3
7 Our contribution the verification guided error resilience methodology Use formal specifications to capture system-level correctness Use verification to analyze system-level impact of circuit-level upsets Guide efficient circuit hardening techniques Particularly suited for communication protocols and on-chip networks Holcomb, Li, Seshia Design as You See FIT 3
8 Outline Introduction Single Event Upset Circuit-level masking System-level masking Introduction Single Event Upset Circuit-level masking System-level masking BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Analysis Efficient Hardening Holcomb, Li, Seshia Design as You See FIT 4
9 Single Event Upset Circuit-level masking System-level masking Basic mechanisms of single event upset (SEU) in logic Strike near sensitive diffusion Sensitive diffusion is a function of gate input If sufficient charge, glitch results at gate output Glitch propagates downstream toward sequential element(s) Holcomb, Li, Seshia Design as You See FIT 5
10 Circuit-level masking not all glitches are equally likely to flip bits Single Event Upset Circuit-level masking System-level masking Logical Masking Is there a sensitized path from strike to latch(es)? Timing Masking Does the glitch arrive at latch(es) while open? Electrical Masking Is the strike magnitude sufficient to cause upset? SEU can lead to single (SBU) or multi-bit upset (MBU) Holcomb, Li, Seshia Design as You See FIT 6
11 Circuit-level masking Introduction Single Event Upset Circuit-level masking System-level masking Related work Holcomb, Li, Seshia Design as You See FIT 7
12 Circuit-level masking Introduction Single Event Upset Circuit-level masking System-level masking Related work Static analysis of circuit structure [Miskov-Zivanov 06, B. Zhang 06] Holcomb, Li, Seshia Design as You See FIT 7
13 Circuit-level masking Introduction Single Event Upset Circuit-level masking System-level masking Related work Static analysis of circuit structure [Miskov-Zivanov 06, B. Zhang 06] Electrical masking using input vectors [M. Zhang 06, Rao 07] Path-based methods Use only a subset of paths Lose accuracy in timing masking Holcomb, Li, Seshia Design as You See FIT 7
14 Circuit-level masking Introduction Single Event Upset Circuit-level masking System-level masking Related work Static analysis of circuit structure [Miskov-Zivanov 06, B. Zhang 06] Electrical masking using input vectors [M. Zhang 06, Rao 07] Path-based methods Use only a subset of paths Lose accuracy in timing masking Timing masking, with no electrical masking [Krishnaswamy 08] Holcomb, Li, Seshia Design as You See FIT 7
15 Circuit-level masking Introduction Single Event Upset Circuit-level masking System-level masking Related work Static analysis of circuit structure [Miskov-Zivanov 06, B. Zhang 06] Electrical masking using input vectors [M. Zhang 06, Rao 07] Path-based methods Use only a subset of paths Lose accuracy in timing masking Timing masking, with no electrical masking [Krishnaswamy 08] No analysis of MBU Holcomb, Li, Seshia Design as You See FIT 7
16 Circuit-level masking Introduction Single Event Upset Circuit-level masking System-level masking Related work Static analysis of circuit structure [Miskov-Zivanov 06, B. Zhang 06] Electrical masking using input vectors [M. Zhang 06, Rao 07] Path-based methods Use only a subset of paths Lose accuracy in timing masking Timing masking, with no electrical masking [Krishnaswamy 08] No analysis of MBU Our approach An efficient method for estimating electrical/timing masking Analysis of circuits up to 20k gates Able to handle multiple sensitized paths Analysis of both SBU and MBU Holcomb, Li, Seshia Design as You See FIT 7
17 Single Event Upset Circuit-level masking System-level masking System level masking not all bit flips are equally likely to cause system failure Related work Holcomb, Li, Seshia Design as You See FIT 8
18 Single Event Upset Circuit-level masking System-level masking System level masking not all bit flips are equally likely to cause system failure Related work Architectural Vulnerability Factor [Mukherjee 03] Find probability of a bit flip leading to incorrect future execution Requires detailed architecture model Holcomb, Li, Seshia Design as You See FIT 8
19 Single Event Upset Circuit-level masking System-level masking System level masking not all bit flips are equally likely to cause system failure Related work Architectural Vulnerability Factor [Mukherjee 03] Find probability of a bit flip leading to incorrect future execution Requires detailed architecture model Output equivalence Find probability of a bit flip leading to incorrect outputs Model state using Markov Chain theory [Miskov-Zivanov 08] Holcomb, Li, Seshia Design as You See FIT 8
20 Single Event Upset Circuit-level masking System-level masking System level masking not all bit flips are equally likely to cause system failure Related work Architectural Vulnerability Factor [Mukherjee 03] Find probability of a bit flip leading to incorrect future execution Requires detailed architecture model Output equivalence Find probability of a bit flip leading to incorrect outputs Model state using Markov Chain theory [Miskov-Zivanov 08] Verification Guided [Seshia 07] Find probability possibility of a bit flip leading to bad behavior Bad behavior formalized using specifications Model checking identifies non-critical latches High confidence but binary Can apply to individual functional blocks Holcomb, Li, Seshia Design as You See FIT 8
![Model state using Markov Chain theory [Miskov-Zivanov 08] Verification Guided [Seshia 07] Find probability possibility of a bit flip leading to bad behavior Bad behavior formalized using](/docs-images/81/82815647/images/21-1.jpg "specifications Model checking identifies non-critical latches High confidence but binary Can apply to individual functional blocks Our approach Verification guided, but produce a refined ranking")
21 Single Event Upset Circuit-level masking System-level masking System level masking not all bit flips are equally likely to cause system failure Related work Architectural Vulnerability Factor [Mukherjee 03] Find probability of a bit flip leading to incorrect future execution Requires detailed architecture model Output equivalence Find probability of a bit flip leading to incorrect outputs Model state using Markov Chain theory [Miskov-Zivanov 08] Verification Guided [Seshia 07] Find probability possibility of a bit flip leading to bad behavior Bad behavior formalized using specifications Model checking identifies non-critical latches High confidence but binary Can apply to individual functional blocks Our approach Verification guided, but produce a refined ranking Holcomb, Li, Seshia Design as You See FIT 8
22 Outline Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Introduction Single Event Upset Circuit-level masking System-level masking BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Analysis Efficient Hardening Holcomb, Li, Seshia Design as You See FIT 9
23 VGER toolkit Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 10
24 VGER toolkit Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 10
25 VGER toolkit Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 10
26 VGER toolkit Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 10
27 VGER toolkit Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 10
28 VGER toolkit Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 10
29 VGER toolkit Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 10
30 BFIT circuit level analysis tool BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Open source C++ simulation tool for combinational logic circuits Based on Nangate 45nm open cell library Inputs Comb. circuit and sampled states Outputs FIT of all events: FIT g E Struck gate g Set of upset sequential elements E some E are SBU, others are MBU Holcomb, Li, Seshia Design as You See FIT 11
31 What determines the FIT of an event? BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Every possible strike is represented by a collected charge and time (q, t) FIT g E R g (q, t) N g E (q, t) dt dq R g(q, t) R N g E (q, t) {0, 1} probability of observing strike q, t at gate g conditional probability of upset in set E of latches, given a strike q, t at gate g Encompasses logical, electrical, timing masking Holcomb, Li, Seshia Design as You See FIT 12
32 BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors BFIT approach to Masking N(q, t) of single path can be characterized using path delay and gate input Inputs determine drive strength Input determines shape of N(q, t) E-6 7.5E E-6 2.9E-6 Table: FIT vs gate input Holcomb, Li, Seshia Design as You See FIT 13
33 BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors BFIT approach to Masking N(q, t) of single path can be characterized using path delay and gate input Inputs determine drive strength Input determines shape of N(q, t) Path delay is time-shift to N(q, t) E-6 7.5E E-6 2.9E-6 Table: FIT vs gate input E-6 6.4E-6 6.4E-6 6.7E-6 Table: FIT vs path length Holcomb, Li, Seshia Design as You See FIT 13
34 Demonstration of BFIT algorithm BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Holcomb, Li, Seshia Design as You See FIT 14
35 Demonstration of BFIT algorithm BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors 1. Forward propagate input vector in levelized DAG Holcomb, Li, Seshia Design as You See FIT 14
36 Demonstration of BFIT algorithm BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors 1. Forward propagate input vector in levelized DAG 2. Dynamic programming back trace in reverse levelized order If an input can flip current gate, back propagate delays Holcomb, Li, Seshia Design as You See FIT 14
37 Demonstration of BFIT algorithm BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors 1. Forward propagate input vector in levelized DAG 2. Dynamic programming back trace in reverse levelized order If an input can flip current gate, back propagate delays 3. For each gate g, find all possible N g E (q, t) using: List of path delays and terminating latches Gate input state and load capacitance Cell precharacterization Holcomb, Li, Seshia Design as You See FIT 14
38 Demonstration of BFIT algorithm BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors 1. Forward propagate input vector in levelized DAG 2. Dynamic programming back trace in reverse levelized order If an input can flip current gate, back propagate delays 3. For each gate g, find all possible N g E (q, t) using: List of path delays and terminating latches Gate input state and load capacitance Cell precharacterization Holcomb, Li, Seshia Design as You See FIT 14
39 Demonstration of BFIT algorithm BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors 1. Forward propagate input vector in levelized DAG 2. Dynamic programming back trace in reverse levelized order If an input can flip current gate, back propagate delays 3. For each gate g, find all possible N g E (q, t) using: List of path delays and terminating latches Gate input state and load capacitance Cell precharacterization Holcomb, Li, Seshia Design as You See FIT 14
40 BFIT results Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Circuit INPUTS LATCHES GATES RUNTIME (s/1k vectors) FIT s e-3 s e-2 s e-2 s e-2 s e-2 s e-2 s e-2 Holcomb, Li, Seshia Design as You See FIT 15
41 BFIT results multiple bit upsets Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Do MBU occur? Holcomb, Li, Seshia Design as You See FIT 16
42 BFIT results multiple bit upsets Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Do MBU occur? BFIT HSPICE SBU 8.6e-7 7.4e-7 MBU 9.0e e-7 total FIT 1.7e-6 2.0e-6 Holcomb, Li, Seshia Design as You See FIT 16
43 BFIT results multiple bit upsets Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Do MBU occur? BFIT HSPICE SBU 8.6e-7 7.4e-7 MBU 9.0e e-7 total FIT 1.7e-6 2.0e-6 Is MBU a concern? Holcomb, Li, Seshia Design as You See FIT 16
44 BFIT results multiple bit upsets Introduction BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Do MBU occur? BFIT HSPICE SBU 8.6e-7 7.4e-7 MBU 9.0e e-7 total FIT 1.7e-6 2.0e-6 Is MBU a concern? Circuit %SBU %MBU s s s s s s s Holcomb, Li, Seshia Design as You See FIT 16
45 Verification Guided Error Resilience using sequential simulation with monitors BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Correctness captured in specifications Hardware monitors synthesized from specifications Estimate failure probabilities using random fault injections Accurately incorporate workload Produces refined ranking Inputs List of formal specifications List of circuit errors E output FP E - the probability that upset E will lead to a violated specification Holcomb, Li, Seshia Design as You See FIT 17
46 Outline Introduction Analysis Efficient Hardening Introduction Single Event Upset Circuit-level masking System-level masking BFIT: Circuit-level soft error analysis Sequential Simulation with Monitors Analysis Efficient Hardening Holcomb, Li, Seshia Design as You See FIT 18
47 Chip Multiprocessor (CMP) Router Analysis Efficient Hardening Simplified 2 port version of 5 port design[peh 01] 174 latches, 1300 gates Specification Every incoming flit must be routed correctly within 11 cycles Target Select gates or latches to harden to reduce combinational FIT to FIT TARGET Holcomb, Li, Seshia Design as You See FIT 19
48 BFIT analysis of CMP router Introduction Analysis Efficient Hardening Output from BFIT tool: Holcomb, Li, Seshia Design as You See FIT 20
49 BFIT analysis of CMP router Introduction Analysis Efficient Hardening Output from BFIT tool: Thousands of E observed, but over 94% are SBU Holcomb, Li, Seshia Design as You See FIT 20
50 System level masking in CMP Analysis Efficient Hardening 94% of SEU are SBU 94% of SEU are SBU Find failure probability (FP E ) for all SBU Holcomb, Li, Seshia Design as You See FIT 21
51 CMP - all masking factors Introduction Analysis Efficient Hardening Figure: System-level SBU FIT Holcomb, Li, Seshia Design as You See FIT 22
52 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Holcomb, Li, Seshia Design as You See FIT 23
53 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Assume a hardened gate contributes no FIT Holcomb, Li, Seshia Design as You See FIT 23
54 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Assume a hardened gate contributes no FIT To achieve FIT FIT TARGET : Harden 81/1300 gates Holcomb, Li, Seshia Design as You See FIT 23
55 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Assume a hardened gate contributes no FIT To achieve FIT FIT TARGET : Harden 81/1300 gates Pareto optimal coverage if all MBU causes system failure Holcomb, Li, Seshia Design as You See FIT 23
56 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Hardening latches Assume a hardened gate contributes no FIT To achieve FIT FIT TARGET : Harden 81/1300 gates Pareto optimal coverage if all MBU causes system failure Holcomb, Li, Seshia Design as You See FIT 23
57 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Assume a hardened gate contributes no FIT Hardening latches Assume a hardened latch captures no FIT To achieve FIT FIT TARGET : Harden 81/1300 gates Pareto optimal coverage if all MBU causes system failure Holcomb, Li, Seshia Design as You See FIT 23
58 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Assume a hardened gate contributes no FIT To achieve FIT FIT TARGET : Hardening latches Assume a hardened latch captures no FIT To achieve FIT FIT TARGET : Harden 81/1300 gates Harden 39/174 latches Pareto optimal coverage if all MBU causes system failure Holcomb, Li, Seshia Design as You See FIT 23
59 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Assume a hardened gate contributes no FIT To achieve FIT FIT TARGET : Hardening latches Assume a hardened latch captures no FIT To achieve FIT FIT TARGET : Harden 81/1300 gates Harden 39/174 latches Pareto optimal coverage if all MBU causes system failure Coverage is Pareto optimal with respect to SBU Holcomb, Li, Seshia Design as You See FIT 23
60 CMP Achieving FIT target by hardening gates or latches Analysis Efficient Hardening Hardening gates Assume a hardened gate contributes no FIT To achieve FIT FIT TARGET : Hardening latches Assume a hardened latch captures no FIT To achieve FIT FIT TARGET : Harden 81/1300 gates Harden 39/174 latches Pareto optimal coverage if all MBU causes system failure Coverage is Pareto optimal with respect to SBU... design as you see FIT Holcomb, Li, Seshia Design as You See FIT 23
61 Summary Summary Holcomb, Li, Seshia Design as You See FIT 24
62 Summary Summary A new method for efficiently analyzing system level impact of circuit level upsets Holcomb, Li, Seshia Design as You See FIT 24
63 Summary Summary A new method for efficiently analyzing system level impact of circuit level upsets Can guide cost-effective hardening of circuit level features Holcomb, Li, Seshia Design as You See FIT 24
64 Summary Summary A new method for efficiently analyzing system level impact of circuit level upsets Can guide cost-effective hardening of circuit level features Provide designer flexibility to harden either gates or latches Holcomb, Li, Seshia Design as You See FIT 24
65 Summary Summary A new method for efficiently analyzing system level impact of circuit level upsets Can guide cost-effective hardening of circuit level features Provide designer flexibility to harden either gates or latches MBU poses threat to reliability Holcomb, Li, Seshia Design as You See FIT 24
66 Summary Thank You BFIT is available at Holcomb, Li, Seshia Design as You See FIT 25
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