ECE 2300 Digital Logic & Computer Organization

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1 ECE 2300 Digital Logic & Computer Organization Spring 2018 Timing Analysis Lecture 11: 1

2 Announcements Lab report guidelines are uploaded on CMS As part of the assignment for Lab 3 report Lab 4(A) prelab due tomorrow Lecture 11: 2

3 Synchronous Circuits combinational The changes in the state of the memory elements are synchronized by a clock signal All flip-flops (FFs) are synchronized to capture the inputs simultaneously on the clock tick Must ensure the output of the combinational has settled before the next clock tick Lecture 11: 3

4 Review: Glitches in Synchronous Circuits X Y S S S Y S X F X S S X F Y S Y Lecture 11: 4

5 Stable FF Situation t clk stable stable t setup t hold t ffpd Flip-flop propagation delay (or clock-to-q delay): the time it takes for the FF output to be stable after the clock edge Lecture 11: 5

6 What if This Happens? IN CLK1 D CLK Q Q1 combinational D2 CLK2 D CLK Q IN CLK1 Q1 D2 CLK2 D2 input still transitioning May capture neither HIGH nor LOW Lecture 11: 6

7 Metastable State unstable t setup t hold Q stuck in the undefined region between 0 and 1 metastable Eventually moves to a stable state, but may take a while (metastable resolution time) Lecture 11: 7

8 But What About This Situation? X Y S S S Y S X F Wrong value captured X S S X F Y S Y Lecture 11: 8

9 Avoiding Timing Failure Possible causes of metastability and wrong value capture Clock pulse that is too narrow Input changes too soon before a clock edge Input changes too soon after a clock edge Avoid by meeting setup time, hold time, and minimum clock pulse width specifications Lecture 11: 9

10 Sequential Circuit Timing Analysis Timing analysis involves calculating the time delays between all FF pairs within the circuit To determine the maximum operating frequency and ensure that setup time requirements are met The clock cannot be too fast To ensure that hold time requirements are met The minimum propagation delay of the combinational (contamination delay) cannot be too small Independent of clock frequency Lecture 11: 10

11 Important Timing Parameters combinational t clk t ffpd t comb t setup t hold Lecture 11: 11

12 Setup Time Constraint t setup is the minimum amount of time before the triggering edge during which FF input must be stable t clk t ffpd t comb t setup t hold Lecture 11: 12

13 Determining Clock Cycle Time FF1 combinational FF2 t ffpd(max) + t comb(max) + t setup t clk Every circuit path between every pair of FFs must satisfy the above equation to run the circuit at a frequency of 1/t clk The longest timing path (worst case) determines the maximum clock frequency Worst case temperature and voltage Worst case manufacturing variations Lecture 11: 13

14 Example: Setup Time Calculations FF1 combinational FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb What s the best achievable cycle time? Lecture 11: 14

15 Example: Setup Time Calculations FF1 combinational FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb t clk >= t ffpd(max) + t comb(max) + t setup = = 19ns Lecture 11: 15

16 Hold Time Constraint FF1 combinational FF2 t hold is the minimum amount of time after the triggering edge during which FF input must remain stable Otherwise, the receiving flip-flop may be contaminated with an unexpected value Need to consider minimum propagation delays (contamination delays) for hold time calculations t ffpd(min) + t comb(min) t hold Lecture 11: 16

17 Example: Hold Time Constraint IN FF1 Q1 very short wire (assume negligible delay) D2 FF2 Q2 IN t ffpd t ffpd Q1 D2 Q2 Hold time windows (t hold ) D2 must be held stable for FF2 t ffpd(min) + t comb(min) = t ffpd(min) +0 t hold Lecture 11: 17

18 Example: Hold Time Calculations FF1 combinational FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb Hold time at FF2 met? Lecture 11: 18

19 Clock Skew Complicates Matters Further Clock may not reach all flip-flops simultaneously CLK1 FF1 combinational [long wire] CLK2 FF2 (assume nontrivial delay) tskew CLK1 (delayed) CLK2 t skew(max) : Maximum clock skew t skew(min) : Minimum clock skew Lecture 11: 19

20 Cycle Time With Clock Skew IN CLK1 FF1 Q1 Combinational D2 CLK2 FF2 [long wire] IN CLK1 Q1 D2 (delayed) (delayed) (delayed) CLK2 tskew tsetup Lecture 11: 20

21 Negative Clock Skew IN CLK1 FF1 Q1 Combinational D2 CLK2 FF2 [long wire] IN CLK1 Q1 D2 (delayed) (delayed) (delayed) t ffpd t comb CLK2 tskew tsetup Sending FF receives clock later than receiving FF t ffpd(max) + t comb(max) + t setup t clk t skew(max) Harmful skew for meeting setup time constraint Lecture 11: 21

22 IN CLK1 Positive Clock Skew FF1 Q1 [long wire] Combinational D2 CLK2 FF2 IN CLK1 Q1 D2 CLK2 (delayed) tskew tsetup Receiving FF receives clock later than sending FF t ffpd(max) + t comb(max) + t setup t clk + t skew(min) Beneficial skew for meeting setup time constraint Lecture 11: 22

23 Hold Time With Positive Clock Skew IN CLK1 FF1 Q1 Combinational D2 CLK2 FF2 [long wire] IN CLK1 Q1 D2 CLK2 (delayed) tskew thold (hold time window effectively widened) Receiving FF receives clock later than sending FF t ffpd(min) + t comb(min) t hold + t skew(max) Harmful skew for meeting hold time constraint Lecture 11: 23

24 Hold Time With Negative Clock Skew IN CLK1 D CLK Q Q1 Combinational D2 CLK2 D CLK Q [long wire] What if sending FF receives clock later than receiving FF? t ffpd(min) + t comb(min) t hold - t skew(min) Beneficial skew for meeting hold time constraint Lecture 11: 24

25 Example: Setup Analysis with Clock Skew FF1 combinational FF2 Clock may arrive at FF1 up to 1ns later than FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb What s the best achievable cycle time? t ffpd(max) + t comb(max) + t setup <= t clk - t skew(max) t clk >= = 20ns Lecture 11: 25

26 H&H , 5.5 Before Next Class Next Time Binary Arithmetic Lecture 11: 26

ENGIN 112 Intro to Electrical and Computer Engineering

ENGIN 112 Intro to Electrical and Computer Engineering Lecture 28 Timing Analysis Overview Circuits do not respond instantaneously to input changes Predictable delay in transferring inputs to outputs Propagation