Finite State Machines CS 64: Computer Organization and Design Logic Lecture #16

Size: px

Start display at page:

Download "Finite State Machines CS 64: Computer Organization and Design Logic Lecture #16"

Kelly Perry
5 years ago
Views:

1 Finite State Machines CS 64: Computer Organization and Design Logic Lecture #16 Ziad Matni Dept. of Computer Science, UCSB

2 Lecture Outline Review of Latches vs. FFs Finite State Machines Moore vs. Mealy types State Diagrams One Hot Method 3/13/18 Matni, CS64, Wi18 2

3 Latches vs. FFs D D Flip-Flop (D-FF) Q Latches capture data on an entire 1 or 0 level of the clock FFs capture data on the edge of the clock This example shows the positive (0à1) edge used > CLK Q Latch out FF out FFs give out less glitchy outputs 3/13/18 Matni, CS64, Wi18 3

4 If a combinational logic circuit is an implementation of a Boolean function, then a sequential logic circuit can be considered an implementation of a finite state machine. 3/13/18 Matni, CS64, Wi18 4

5 Finite State Machines (FSM) An abstract machine that can be in exactly one of a finite number of states at any given time It s a very simple model of a computational machine, unlike Pushdown Automatons and Turing Machines You ll discover these in other CS upper-div classes The FSM can change from one state to another in response to some external inputs The change from one state to another is called a transition. An FSM is defined by a list of its states, its initial state, and the conditions for each transition. 3/13/18 Matni, CS64, Wi18 5

Example of a Simple FSM: The Turnstile initial state State Transition Table Current State Input Next State Output Locked Coin Unlocked Unlocks the turnstile so that the customer can push through.

6 Example of a Simple FSM: The Turnstile initial state State Transition Table Current State Input Next State Output Locked Coin Unlocked Unlocks the turnstile so that the customer can push through. Locked Push Locked Nothing you re locked! J Unlocked Coin Unlocked Nothing you just wasted a coin! J Unlocked Push Locked When the customer has pushed through, locks the turnstile. 3/13/18 Matni, CS64, Wi18 6 Source: Wikipedia

7 Example of a Simple FSM: The Turnstile initial state State Transition Table Current State Input Next State Output Locked Coin Unlocked Unlocks the turnstile so that the customer can push through. Locked Push Locked Nothing you re locked! J Unlocked Coin Unlocked Nothing you just wasted a coin! J Unlocked Push Locked When the customer has pushed through, locks the turnstile. 3/13/18 Matni, CS64, Wi18 7 Source: Wikipedia

8 General Form of FSMs 3/13/18 Matni, CS64, Wi18 8

9 Example Output-to-input feedback Combinatorial logic A CLK Clock signal Q* State register Q Q* = Q O.A On the next rising edge of the clock, the output of the D-FF Q (Q*) will become the previous value of Q (Q O ) AND the value of input A 3/13/18 Matni, CS64, Wi18 9

10 FSM Types There are 2 types/models of FSMs: Moore machine Output is function of present state only Mealy machine Output is function of present state and present input 3/13/18 Matni, CS64, Wi18 10

11 Moore Machine 3/13/18 Matni, CS64, Wi18 11

12 Example of a Moore Machine (with 1 state) A Q Z CLK B Z = (Q* + B) = (Q O.A + B) On the next rising edge of the clock, the output of the entire circuit (Z) will become (the previous value of Q (Q O ) AND the value of input A) NOR B 3/13/18 Matni, CS64, Wi18 12

13 Mealy Machine 3/13/18 Matni, CS64, Wi18 13

14 Example of a Mealy Machine (with 1 state) A CLK B Q Z Z = (Q* + A + B) = (Q O XOR A) + (A + B) On the next rising edge of the clock, the output of the entire circuit (Z) will become etc 3/13/18 Matni, CS64, Wi18 14

15 Diagraming State Machines A simple FSM example 2 states: Door opened Door closed This is called a state diagram 3/13/18 Matni, CS64, Wi18 15

16 Example of a Moore Machine 1 WASHER_DRYER Let s build a sequential logic FSM that acts as a controller to a washer/dryer machine SO: Before we begin, the machine is in an initial state that is waiting for you to insert a coin. We ll call that state the Initial State (inventive, no?) The machine will start a washer timer as soon as a coin is inserted. The timer is controlled by a signal (i.e. input var) called TIMER_LT_30, which is always initialized to be 1. 3/13/18 Matni, CS64, Wi18 16

17 Example of a Moore Machine 1 WASHER_DRYER Upon inserting a coin in the machine, we will begin the wash cycle. We ll call that state Wash. This state will output a signal to fill the washer with water (FILL_WATER). As long as the timer is below 30 mins (TIMER_LT_30 = 1), the cycle continues. When the timer surpasses 30 mins (i.e. TIMER_LT_30 = 0), this state will end 3/13/18 Matni, CS64, Wi18 17

18 Example of a Moore Machine 1 WASHER_DRYER When the timer hits 30 mins, we will begin the rinse cycle. We ll call that Rinse. This will output a signal to drain the water and refill with new water (DRAIN_REFILL = 1). As long as the soap sensor is on (SOAP = 1), the cycle continues. When the soap sensor turns off (i.e. SOAP= 0), this state will end 3/13/18 Matni, CS64, Wi18 18

19 Example of a Moore Machine 1 WASHER_DRYER When the soap sensor goes off, we will begin the dry cycle. We ll call that Dry. This state will output a signal to drain the water and begin drying (DRAIN = 1). As long as the wet clothes sensor is on (WET = 1), the cycle continues. When the wet clothes sensor is off (WET = 0), we will stop! This means going back to the Initial State 3/13/18 Matni, CS64, Wi18 19

20 State Diagram 1 TIMER_LT_30 = 1 SOAP = 1 COIN = 0 Wash TIMER_LT_30 = 0 Rinse Initial State TIMER_LT_30 = 1 FILL_WATER = 1 DRAIN_REFILL = 1 WET = 0 Dry WET = 1 DRAIN = 1 3/13/18 Matni, CS64, Wi18 20

21 Example of a Moore Machine 2 DETECT_1101 Let s build a sequential logic FSM that always detects a specific serial sequence of bits: 1101 SO: We ll start at an Initial state (S0) We ll first look for a 1. We ll call that State 1 (S1) Don t go to S1 if all we find is a 0! We ll then keep looking for another 1. We ll call that State 11 (S2) Then a 0. We ll call that State 110 (S3) Then another 1. We ll call that State 1101 (S4) this will output a FOUND signal We will always be detecting 1101 (it doesn t end) 3/13/18 Matni, CS64, Wi18 21

22 State Diagram 2 Input = 1 Input = 0 Input = S1 S2 Initial State S0 Input = 0 Input = S4 Input = S3 FOUND = 1 3/13/18 Matni, CS64, Wi18 22

23 Going from State Diagram to Circuit There s more than 1 way to do this, but the most popular is the One Hot Method Give each state it s own D-FF output # of FFs needed = # of states Inputs to the FFs are combinatorial logic that can simplified into a sum-of-products type of Boolean expression Current CAD software can do this automatically Implementation is usually done on a simulator (software), or prototype hardware Integrated Circuit (FPGA) 3/13/18 Matni, CS64, Wi18 23

24 Encoding our States Per the last example: We had 5 separate states: NAME Binary Code One Hot Code OUTPUT Initial State S S S S S FOUND Advantage of this One Hot approach? When we implement the machine with circuits, we can use a D-FF for every state (so, in this example, we d use 5 of them) 3/13/18 Matni, CS64, Wi18 24

25 Using the One Hot Code to Determine the Circuit Design Every state has 1 D-FF We can see that (follow the arrows!!): S1* = S0.I S2* = S1.I + S2.I + S4.I S3* = S2.I S4* = S3.I S0* = S0.I + S1.I + S3.I + S4.I Input = 0 Input = Initial State S0 S S4 FOUND = 1 Input = 0 Input = 1 S2 110 S3 Input = 1 Input = 0 also, when S4 happens, FOUND = 1, i.e. FOUND = S4 3/13/18 Matni, CS64, Wi18 25

26 Implementing the Circuit 3/13/18 Matni, CS64, Wi18 26

27 Your To Dos Lab #8 is due end of day Friday 3/13/18 Matni, CS64, Wi18 27

28 3/13/18 Matni, CS64, Wi18 28

Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #14

Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #14 Ziad Matni Dept. of Computer Science, UCSB Administrative Remaining on the calendar This supersedes