Understanding Engineers #2

Transcription

1 Understanding Engineers #! The graduate with a Science degree asks, "Why does it work?"! The graduate with an Engineering degree asks, "How does it work?"! The graduate with an Accounting degree asks, "How much will it cost?"! The graduate with an Arts degree asks, "Do you want fries with that?" CS 5 - Spring 27 Lec #8 Mid #2 Review - Understanding Engineers #2! MS CS -- Soft-ware! MS EE -- Hard-ware! MBA -- Un-a-ware! MFA -- No-ware CS 5 - Spring 27 Lec #8 Mid #2 Review - 2

2 Midterm II! THIS Thursday, 22 March (that is TWO days from today!), 2: -- 3:3+, CS 5 Lab! Lectures,, 2, (no lecture 3!), 4, 5, 6; Labs #4 and #5 (Debugging/Logic Analyzers) + Checkpoints # and # (SDRAM + Video Encoder)! Don t forget: Spring 5/Fall 5 exams are on-line!! 5 x point questions, mostly design-oriented! Closed book, open crib sheet; PENCIL, not pen!! Two review sessions: Tu 8 PM and W 8 PM in the lab! NOTE: Discussion sections and lab lecture cancelled this week CS 5 - Spring 27 Lec #8 Mid #2 Review - 3 Sequential Logic Implementation! Models for representing sequential circuits " Mealy, Moore, and synchronous Mealy machines " Verilog specifications for state machines! Finite state machine design procedure " Deriving state diagram from word specifications " Deriving state transition table " Determining next state and output functions " Implementing combinational logic CS 5 - Spring 27 Lec #8 Mid #2 Review - 4

3 SDRAM Memory Controller! Static RAM Technology " 6T Memory Cell " Memory Access Timing! Dynamic RAM Technology " T Memory Cell " Memory Access Timing! Theory in lecture, but practical detailed memory system organization and timing in Lab Checkpoint # CS 5 - Spring 27 Lec #8 Mid #2 Review - 5 Two-way Video Conferencing Project! Project Concept and Background! SDRAM Controller (Checkpoint #)! Video Encoder/Display System (Checkpoint #) CS 5 - Spring 27 Lec #8 Mid #2 Review - 6

4 Videoconferencing System Concept Video Decoder Multiport SDRAM Memory System Video Encoder Camera SDRAM (Checkpoint #) Display Video Decoder Videostream Multiport Arbitration Video Encoder (Checkpoint #) Checkpoint #2 Checkpoint #4 Wireless Transceiver (Checkpoint #3) CS 5 - Spring 27 Lec #8 Mid #2 Review - 7 Computer Organization! Computer design as an application of digital logic design procedures! Computer = processing unit + memory system! Processing unit = control + datapath! Control = finite state machine " Inputs = machine instruction, datapath conditions " Outputs = register transfer control signals, ALU operation codes " Instruction interpretation = instruction fetch, decode, execute! Datapath = functional units + registers " Functional units = ALU, multipliers, dividers, etc. " Registers = program counter, shifters, storage registers CS 5 - Spring 27 Lec #8 Mid #2 Review - 8

5 Register Transfer A B C! A Sel D E C Sel Sel Sel! ; Ld! C! B Sel! ; Ld! Bus Ld C Clk Clk Sel A on Bus B on Bus Ld CS 5 - Spring 27 Lec #8 Mid #2 Review - 9 Ld C from Bus? Register Transfer! Point-to-point connection " Dedicated wires " Muxes on inputs of each register! Common input from multiplexer " Load enables for each register " Control signals for multiplexer! Common bus with output enables " Output enables and load enables for each register MUX rs rs MUX rt MUX rd MUX R4 rt rd R4 MUX rs rt rd R4 CS 5 - Spring 27 Lec #8 Mid #2 Review - BUS

6 State Machine Implementation! Alternative controller FSM implementation approaches based on: " Classical Moore and Mealy machines " Time state: Divide and Counter " Jump counters " Microprogramming (ROM) based approaches # branch sequencers # horizontal microcode # vertical microcode CS 5 - Spring 27 Lec #8 Mid #2 Review - Time State (Divide & Conquer) Time State FSM Most instructions follow same basic sequence Differ only in detailed execution sequence Time State FSM can be parameterized by opcode and AC states Instruction State: stored in IR<5:4> Condition State: stored in AC<5> = = IR = = LD ST ADD BRN AC < AC<5>= AC?" T T T2 T3 T4 T5 T6 T7 AC<5>= CS 5 - Spring 27 Lec #8 Mid #2 Review - 2 BRN AC! / (LD + ST + ADD) BRN + (ST Wait)/ (LD + ADD) Wait

7 Jump Counters Pure Jump Counter Inputs Count, Load, Clear Logic Jump State Logic NOTE: No inputs to jump state logic Clear Load Count CLOCK Synchronous Counter State Register Logic blocks implemented via discrete logic, PLAs, ROMs CS 5 - Spring 27 Lec #8 Mid #2 Review - 3 Jump Counters Hybrid Jump Counter Inputs Count, Load, Clear Logic Load Count Clear CLOCK Jump State Logic Synchronous Counter State Register Load inputs are function of state and FSM inputs CS 5 - Spring 27 Lec #8 Mid #2 Review - 4

8 Jump Counters CLR, CNT, LD implemented via Mux Logic CLR = CLRm + Reset CLR = CLRm + Reset /CLRm /Reset Reset Wait /CLR Jump State IR5 IR<5> IR4 IR<4> /Reset /Wait 3 2 CNT /LD /CLR P T CLK D C B A LOAD CLR 63 RCO QD QC QB QA G2 G D C B A \S3 \S2 \S \S \S9 \S8 \S7 \S6 \S5 \S4 \S3 \S2 \S \S Active Lo outputs: hi input inverted at the output Note that CNT is active hi on counter so invert MUX inputs! S3 S2 S S G E5 5 E4 + E3 + E2 E E E9 E8 E7 E6 E5 E4 E3 Wait E2 /Wait E E S3 S2 S S G G E5 5 E5 5 E4 E4 E3 E3 E2 E2 E E E E /Wait E9 E9 EOUT E8 E8 EOUT CNT /CLRm EOUT E7 E6 E5 E4 E3 E2 E E + S3 S2 S S E7 E6 E5 E4 E3 E2 E E /LD CS 5 - Spring 27 Lec #8 Mid #2 Review - 5 Branch Sequencers 4 Way Branch Sequencer I n p u t s Mux Mux # $ a a a2 a3 a4 a5 x x x x 64 Word ROM Z Y X W C o n t r o l S i g n a l s N $ # $ # $ # $ # W X Y Z state Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states CS 5 - Spring 27 Lec #8 Mid #2 Review - 6

9 Branch Sequencers! and " MUX Control Alternative Horizontal Implementation! "! "! "! " A A A2 A3 n- n- n- n- Datapath Control Signals I N P U T S M U M X U X! " bit n : MUX 4: MUX bit bit n bit state register Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In example FSM, input MUX can be 2:! Adding length to ROM word saves on bits vs. doubling words Vertical format: (4 + 4) x 64 = 52 ROM bits Horizontal format: (4 + 4 x 4 + 2) x 6 = 52 ROM bits CS 5 - Spring 27 Lec #8 Mid #2 Review - 7 Vertical Microprogramming Branch Jump Compare indicated signal to or Branch Jump Format Type Condition Select Condition Compare 2 6 Next Address = Wait = AC<5> = IR<5> = IR<4> Register Transfer Source, Destination, Operation ROM Bits Register Transfer Format : NO OP : PC! ABUS : IR! ABUS : MBR! MBUS : MAR! M : AC! RBUS : ALU Res! RBUS Source Destination Operation : NO OP : RBUS! AC : MBUS! IR : ABUS! MAR : M! MBR : RBUS! MBR : ABUS! PC : MBR! M CS 5 - Spring 27 Lec #8 Mid #2 Review - 8 : NO OP : ALU ADD : ALU PASS B :! PC : PC +! PC : Read : Write

10 Vertical Programming Controller Block Diagram Address ROM T SRC DST OP 3:8 DEC Enb 3:8 DEC Enb Reset ALU ADD ALU PASS B PC +! PC 5 Read 6 Write RBUS! AC ABUS! IR ABUS! MAR M! MBR RBUS! MBR ABUS! PC MBR! M! PC Read/Write Request Wait AC<5> IR<5> IR<4> Cond Logic LD CLR µpc CNT PC! ABUS IR! ABUS 2 3:8 3 MBR! ABUS DEC 4 MAR! M 5 AC! RBUS 6 ALU Res! RBUS Enb 7 Reset Clk CS 5 - Spring 27 Lec #8 Mid #2 Review - 9 Design/Reverse Engineering! Design Procedure: Specification --> Abstract Design --> Concrete Implementation " E.g., What the state machine is supposed to do to state diagram to jump counter implementation! Reverse Engineering: Concrete Implementation --> Abstract Design --> Specification " E.g., Jump counter implementation to state diagram to what the state machine is supposed to do CS 5 - Spring 27 Lec #8 Mid #2 Review - 2