Pipelined Architecture (2A) Young Won Lim 4/7/18

Transcription

1 Pipelined Architecture (2A)

2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using LibreOffice.

3 Based on ARM System-on-Chip Architecture, 2 nd ed, Steve Furber Pipelined Architecture 3

4 B bus A bus ALU bus 3-stage Pipeline A[31:0] MAR +1 Register Bank Instruction Decoder / mult Shifter ALU MDO MDI D[31:0] Pipelined Architecture 4

5 B bus A bus ALU bus Register-Register Operations A[31:0] MAR +1 Rd Rn Register Bank PC Rm Instruction Decoder / mult Shifter ALU MDO MDI I. Pipe D[31:0] Pipelined Architecture 5

6 B bus A bus ALU bus Register-Immediate Operations A[31:0] MAR +1 Rd Rn Register Bank PC Rm Instruction Decoder / mult Shifter ALU MDO MDI I. Pipe D[31:0] Pipelined Architecture 6

7 B bus A bus ALU bus STR - 1 st Cycle A[31:0] MAR +1 Rd Rn Register Bank PC Rm Instruction Decoder / mult Shifter ALU MDO MDI I. Pipe D[31:0] Pipelined Architecture 7

8 B bus A bus ALU bus STR - 2 nd Cycle A[31:0] MAR +1 Rd PC Rn Register Bank Rm Instruction Decoder / mult Shifter ALU MDO MDI I. Pipe D[31:0] Pipelined Architecture 8

9 B bus A bus ALU bus B - 1 st Cycle A[31:0] MAR +1 Rd PC Register Bank Rm Instruction Decoder / mult Shifter ALU MDO MDI I. Pipe D[31:0] Pipelined Architecture 9

10 B bus A bus ALU bus B - 2 nd Cycle A[31:0] MAR +1 Rd PC Rn Register Bank Rm Instruction Decoder / mult Shifter ALU MDO MDI I. Pipe D[31:0] Pipelined Architecture 10

11 ARM Instruction Set The load-store architecture 3-address data processing instructions (2 source registers + 1 destination register) Conditionally executes every instruction Multiple data transfer instruction Single cycle execution of shift and ALU operations Open instruction set for coprocessors A very dense 16-bit compressed instruction set (Thumb) Pipelined Architecture 11

12 3-stage fetch the instruction is fetched from memory it is placed in the instruction pipeline decode the instruction is decoded next cycle control signal is prepared the decode logic but not the datapath is dedicated execute the datapath is dedicated reading the register bank shifting an operand performing ALU operations writing back the result into the register bank Pipelined Architecture 12

13 3 stage pipeline single cycle fetch decode execute fetch decode execute fetch decode execute Pipelined Architecture 13

14 3-stage pipeline multi-cycle Fetch ADD decode execute Fetch STR decode Calc address Data transfer Fetch ADD decode execute Fetch ADD decode execute Fetch ADD decode execute the decode logic is involved in all the decode cycle the address calculation the datapath is involved in all the execute cycle the address calculation the data transfer Pipelined Architecture 14

15 3-stage pipeline multi-cycle decode logic datapath decode Calc address execute Calc address Data transfer Pipelined Architecture 15

16 3-stage pipeline multi-cycle decode logic datapath datapath fetch fetch decode logic datapath i-th instruction fetch decode logic (i+1)-th instruction fetch (i+2)-th instruciton Pipelined Architecture 16

17 ARM Exception Handling N Z C V R R R R R R R R R R R R R R R R R R R R R R R R R R R R Pipelined Architecture 17

18 References [1] ftp://ftp.geoinfo.tuwien.ac.at/navratil/haskelltutorial.pdf [2]