EC4205 Microprocessor and Microcontroller

Size: px

Start display at page:

Download "EC4205 Microprocessor and Microcontroller"

Homer Ellis
5 years ago
Views:

1 EC4205 Microprocessor and Microcontroller Webcast link: All announcement made through webpage: check back often Students are welcome outside the class (right after class) Dr. A. Islam Dept. of ECE BIT, Mesra, Ranchi Prepared and presented by Dr. A. Islam 1

2 EC4205 Lecture notes based on material From me, Prof. (Dr.) R. Sukesh Kumar and following text books: 1. Digital Computer Electronics, 2/e, by A. P. Malvino. 2. Microprocessor Architecture, Programming and Applications with 8085, by R. S. Gaonkar. 3. Microprocessor and Interfacing, Programming of Hardware, by D. Hall. 4. Microprocessor and Peripherals, by S. P. Chowdhury and S. Chowdhury. 5. INTEL 8086/8088 Microprocessor, Architecture, Programming, Design and Interfacing, 3/e, by B. S. Chhabra. 6. Microprocessor, Microcomputer and their Applications, 2/e, by A, K. Mukhopadhyay. 7. The Intel Microprocessors 8086/888, 80186/80188, 80286, 80386, 80486, Pentium and Pentium Pro processor architecture, programming and interfacing, 4/e, by B. B. Brey. 8. Microprocessors with applications in process control, by SI Ahson. 9. Microprocessors theory and applications: Intel and Motorola, by M. Rafiquzzaman. Use the material without violating copyright act involved with original books. Prepared and presented by Dr. A. Islam 2

3 Module-I: Outline 1. Revision of logic circuits with emphasis on control lines 2. SAP concepts with stress on timing diagrams 3. Microinstructions 4. Microprogramming 5. Variable machine cycle 6. Architecture of 8085 Processor 7. Functions of all signals 8. Bus concepts 9. Multiplexed and De-multiplexed Bus 10.Minimum system Prepared and presented by Dr. A. Islam 3

4 Fig (Malvino) LDA Routine (a) T4 state; (b) T5 state (c) T6 state Prepared and presented by Dr. A. Islam 4

5 T states T4 T5 LDA routine (Execution cycle) Active control signals E I bar L M bar CE bar L A bar Active parts of SAP-1 MAR IR CON MAR RAM IR CON T6 None None NOP A Operation takes place As low EI bar enables tristated o/p buffer of IR, its content (address field out of the two nibbles) is outputted onto W bus. Low L M bar makes MAR enabled to be loaded. when +ve CLK edge hits in the middle of T4 state MAR gets loaded with the address available on the W bus. In T5 state CE bar is active (low). CE bar enables tristated o/p of RAM making addressed RAM content available onto W bus. As L A bar is active (low), it makes A enabled to be loaded with W bus content, i.e. addressed RAM data is transferred to accumulator on +ve CLK edge. Prepared and presented by Dr. A. Islam 5

6 ADD routine (Execution cycle) T states T4 T5 T6 Active control signals E I bar L M bar CE bar L B bar L A bar E U Active parts SAP-1 MAR IR CON MAR RAM IR CON B IR CON A B of Operation takes place During T4 state the instruction field goes to controller-sequencer. As low EI bar enables tristated o/p buffer of IR, its content (address field out of the two fields) is outputted onto W bus. Low L M bar makes MAR enabled to be loaded. when +ve CLK edge hits in the middle of T4 state MAR gets loaded with the address available on the W bus. In T5 state CE bar is active (low). CE bar enables tristated o/p of RAM making addressed RAM content available onto W bus. As L B bar is active, it makes B enabled to be loaded with W bus content, i.e. addressed RAM data is transferred to accumulator on +ve CLK edge. The high E U enables tristated o/p buffer of adder/sub making result available onto W and as L A bar is active (low), it makes A enabled to be loaded with W bus content (i.e. result gets loaded into accumulator and as usual loading takes place midway through the state when the positive clock edge hits the CLK i/p of A register). SUB routine is similar to ADD routine. Active control signals & parts are same except that during T6 state S U goes high making subtraction possible in stead of addition. Prepared and presented by Dr. A. Islam 6

7 Fig (Malvino) Fetch and LDA timing diagram Prepared and presented by Dr. A. Islam 7

The new contents return to the accumulator input, but the new content don t get there until two propagation delays after the +ve CLK edge (one for the accumulator and one

8 The setup and propagation delay prevent racing of accumulator during the final execution (T6 state). When the +ve CLK edge hits in Fig. 10.6(c) (Malvino), the accumulator contents change, forcing the adder/subtracter contents to change. The new contents return to the accumulator input, but the new content don t get there until two propagation delays after the +ve CLK edge (one for the accumulator and one for the adder/subtracter). By then it is too late to change the accumulator. This prevents the accumulator racing (loading more than once on the same CLK edge). Fig. 10.6(Malvino) ADD and SUB routines: (a) T4 state; (b) T5 state; (c) T6 state. Prepared and presented by Dr. A. Islam 8

9 Address state of Fetch cycle : T1: active control signals are E P and L M bar Increment state of Fetch cycle : T2: active control signals are C P Memory state of Fetch cycle : T3: active control signals are C E bar and L E bar Execution cycle of ADD/SUB routine: T4: active control signals are L M bar and E I bar Execution cycle of ADD/SUB routine: T5: active control signals are C E bar and L B bar Execution cycle of ADD/SUB routine: T6: active control signals are L A bar and E U (In addition to these, the control signal S U will be high in case of SUB routine during T6 state). Fig. 10.7(Malvino) Fetch and ADD timing diagram Prepared and presented by Dr. A. Islam 9

10 Prepared and presented by Dr. A. Islam 10

11 During T4 state the instruction field goes to the controller-sequencer for decoding. Then controllersequencer sends out the control word needed to load the accumulator contents into the output register. Execution cycle of OUT routine: T4: active control signals are L O bar and E A. E A makes tristated o/p buffer of A register enabled thereby placing its content onto the W bus. L O bar enables output register to be loaded with the content of W bus when the +ve CLK edge hits the o/p register. Timing diagram includes the fetch cycle also which is same for all instructions. T5 and T6 states of OUT instructions are NOPs. HLT: does not require a control word because no registers are involved in the execution of an HLT instruction. When it is executed, the instruction field containing 1111 goes to controller-sequencer which stops the computer by turning off the clock circuitry. Fig. 10.8(Malvino) T4 of OUT instruction Prepared and presented by Dr. A. Islam 11

EC4205 Microprocessor and Microcontroller

EC4205 Microprocessor and Microcontroller Webcast link: https://sites.google.com/a/bitmesra.ac.in/aminulislam/home All announcement made through webpage: check back often Students are welcome outside the