ICS Low Skew Fan Out Buffers. Integrated Circuit Systems, Inc. General Description. Pin Configuration. Block Diagram. 28-Pin SSOP & TSSOP

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1 Integrated Circuit Systems, Inc. ICS Low Skew Fan Out Buffers General Description The ICS generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Outputs will handle up to 33MHz clocks. An output enable is provided for testability. The device is a buffer with low output to output skew. This is a Fanout buffer device, not using an internal PLL. This buffer can also be a feedback to an external PLL stage for phase synchronization to a master clock. There are a total of ten outputs, sufficient for feedback to a PLL source and to drive four small outline DIMM modules (S.O. DIMM) at clocks each. Or a total of ten outputs as a Fanout buffer from a common clock source. The individual clock outputs are addressable through I C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed. Features Ten High speed, low noise non-inverting buffers for (to 33MHz), clock buffer applications. Output slew rate faster than.5v/ns into 0pF Supports up to four small outline DIMMS (S.O. DIMM). Synchronous clocks skew matched to 50ps window on PUTs (0:9). I C Serial Configuration interface to allow individual PUTs to be stopped low. Multiple VDD, VSS pins for noise reduction Tri-state pin for testing 3.0V 3.7V supply range 8-pin (09 mil) SSOP and (6.mm) TSSOP package Block Diagram Pin Configuration 8-Pin SSOP & TSSOP PentiumPro is a trademark of Intel Corporation I C is a trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

2 Pin Descriptions PIN NUMBER PIN NAME, 3 PUT (0:) 6, 7 PUT (:3), 3 PUT (4:5) 6, 7 PUT (6:7) PUT8 8 PUT9 9 BUF_IN 0 OE 4 SDATA 5 SCLK, 5, 0, 9, 4, 8 VDD (0:5) 4, 8,, 6, 7,, 5 GND (0:5) 3 VDDI 6 GNDI TYPE IN DESCRIPTION outputs, uses VDD0, GND0 outputs, uses VDD, GND outputs uses VDD, GND output uses VDD3, GND3 output uses VDD4, GND4 output uses VDD5, GND5 Input for buffers I N ri-states all outputs when held LOW. Has internal pull-up. I/ O I/ O PWR PWR PWR PWR T Data pin for I circuitry C 3 pin for I circuitry C 3 3.3V Power supply for PUT buffers Ground for PUT buffers 3.3V Power supply for I C circuitry and internal logic Ground for I C circuitry and internal logic Notes:. At power up all ten PUTs are enabled and active.. OE has a 00K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 00K Ohms as well for complete platform flexibility. Power Groups VDD (0:5), GND (0:5) = Power supply for PUT buffer VDDI, GNDI = Power supply for I C circuitry

3 Technical Pin Function Descriptions VDD This is the power supply to the internal core logic of the device as well as the clock output buffers for PUT (0:9). This pin operates at 3.3V volts. s from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the s, please consult the DC parameter table in this data sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. PUT (0:9) These Output s are use to drive Dynamic RAM s and are low skew copies of the CPU s. The voltage swing of the PUTs output is controlled by the supply voltage that is applied to VDD of the device, operates at 3.3 volts. I C The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I C protocol. It will allow read-back of the registers. See configuration map for register functions. The I C specification in Philips I C Peripherals Data Handbook (996) should be followed. BUF_IN Input for Fanout buffers (PUT 0:9). OE OE tristates all outputs when held low. VDD This is the power supply to I C circuitry. 3

4 General I C serial interface information The information in this section assumes familiarity with I C programming. How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. How to Read: Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Notes: Controller (Host) Start Address D (H) Dummy Command Code Dummy Byte Count Byte 0 Byte Byte Byte 3 Byte 4 Byte 5 Byte 6 Stop How to Write: ICS (Slave/Receiver) Controller (Host) Start Address D3 (H). The ICS clock generator is a slave/receiver, I C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.. The data transfer rate supported by this clock generator is 00K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. Stop How to Read: ICS (Slave/Receiver) Byte Count Byte 0 Byte Byte Byte 3 Byte 4 Byte 5 Byte 6 4

5 Serial Configuration Command maps Byte 0: PUT Register (Default=0) B IT PIN# PWD 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 7 PUT3 6 PUT 3 PUT 0 PUT0 DESCRIPTION Notes: = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default Byte : PUT Register B IT PIN# PWD DESCRIPTION 7 7 PUT7 (Act/Inact) 6 6 PUT6 (Act/Inact) 5 3 PUT5 (Act/Inact) 4 PUT4 (Act/Inact) 3 - Reserved - Reserved - Reserved 0 - Reserved Notes: = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default ICS Power Management The values below are estimates of target specifications. Condition No Mode (BUF_IN - VDD or GND) I C Circuitry Active Active 66MHz (BUF_IN = 66.66MHz) Active 00MHz (BUF_IN = 00.00MHz) Active 33MHz (BUF_IN = 33.33MHz) Max 3.3V supply consumption Max discrete cap loads VDD = 3.465V All static inputs = VDD or GND 3mA 30mA 360mA 460mA Byte : PUT Register B IT PIN# PWD DESCRIPTION 7 8 PUT9 (Act/Inact) 6 PUT8 (Act/Inact) 5 - Reserved 4 - Reserved 3 - Reserved - Reserved - Reserved 0 - Reserved Notes: = Enabled; 0 = Disabled, outputs held low Functionality O E# PUT (0:9) 0 Hi-Z X BUF_IN 5

6 Absolute Maximum Ratings Supply Voltage V Logic Inputs GND 0.5 V to V DD +0.5 V Ambient Operating Temperature C to +70 C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH V DD +0.3 V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD 5 ua Input Low Current I IL V IN = 0 V; Inputs with no pull-up resistors -5 ua I IL V IN = 0 V; Inputs with 00K pull-up resistors ua I DD C L = 0 pf; F 66M 80 0 ma Operating I DD C L = 0 pf; F 00M 0 80 ma I DD3 C L = 0 pf; F 33M ma Supply Current I DD4 C L = 30 pf; RS=33Ω; F 66M ma I DD5 C L = 30 pf; RS=33Ω; F 00M ma I DD6 C L = 30 pf; RS=33Ω; F 33M ma Input frequency F i V DD = 3.3 V; All Outputs Loaded 0 33 MHz Input Capacitance C IN Logic Inputs 5 pf Guarenteed by design, not 00% tested in production. 6

7 Electrical Characteristics - Outputs T A = 0-70C; V DD = 3.3 V +/-5%; C L = 0-30 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP V O = V DD *(0.5) 0 4 Ω Output Impedance R DSN V O = V DD *(0.5) 0 4 Ω Output High Voltage V OH I OH = -30 ma.3 3 V Output Low Voltage V OL I OL = 3 ma V Output High Current I OH V OH =.0 V ma Output Low Current I OL V OL = 0.8 V ma Rise Time T r V OL = 0.4 V, V OH =.4 V ns Fall Time T f V OH =.4 V, V OL = 0.4 V ns Duty Cycle D t V T =.5 V % Skew T sk V T =.5 V 0 50 ps T PHL V T =.5 V ns T PLH V T =.5 V ns Propagation, T PHL 50% Buffer In to 90% Out ns T PLH 50% Buffer In to 0% Out ns T EN V T =.5 V 8 ns T DIS V T =.5 V 8 ns Note: Paramater is guaranteed by design and characterization for all operating frequencies, (0MHz - 33MHz). Not 00% tested in production Note: Duty cycle of input clock is 47.5% to 5.5%. Input edge rate is for propagation delay V/ns 7

8 General Layout Precautions: ) Use a ground plane on the top layer of the PCB in all areas not used by traces. ) Make all power traces and vias as wide as possible to lower inductance. Notes: All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. Capacitor Values: All unmarked capacitors are 0.0µF ceramic 8

9 09 mil SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A A b c D SEE VARIATIONS SEE VARIATIONS E E e 0.65 BASIC BASIC L N SEE VARIATIONS SEE VARIATIONS α VARIATIONS D mm. D (inch) N MIN MAX MIN MAX mil SSOP Reference Doc.: JEDEC Publication 95, MO Ordering Information 979yF-03LF-T Example: XXXX y F - PPPLF - T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Pattern Number ( or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

10 6.0 mm. Body, 0.65 mm. Pitch TSSOP INDEX AREA N D E E c α L (40 mil) (5.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A A b c D E SEE VARIATIONS 8.0 BASIC SEE VARIATIONS 0.39 BASIC E e 0.65 BASIC BASIC L N SEE VARIATIONS SEE VARIATIONS α aaa A A A -C- VARIATIONS D mm. D (inch) N MIN MAX MIN MAX e b SEATING PLANE Reference Doc.: JEDEC Publication 95, MO-53 aaa C Ordering Information 979yG-03LF-T Example: XXXX y G - PPPLF - T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Pattern Number ( or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type 0

11 Revision History Rev. Issue Date Description Page # J 8/9/005 Added LF Ordering Information. 9, 0 K /5/008 Removed ICS prefix from ordering information 9, 0