Frequency Generator & Integrated Buffers for Celeron & PII/III

Transcription

1 Integrated Circuit Systems, Inc. ICS950-8 Frequency Generator & Integrated Buffers for Celeron & PII/III Recommended Application: 80/80E and 85 type chipset. Output Features: CPU (.5V) (up to 33 achievable through I C) 3 SDRAM (3.3V) (up to 33 achievable through I C) PCI (3.3 IOAPIC Hublink clocks ( (Non spread spectrum) REF 4.38 Features: Supports spread spectrum modulation, 0 to -0.5% down spread. I C support for power management Efficient power management scheme through PD# Uses external 4.38 crystal Alternate frequency selections available through I C control. IOAPIC VDDL *FS/REF0 VDDREF X X VDD3V66 3V66_0 3V66_ 3V66_ VDDPCI PCICLK0 PCICLK FS0 VDDA PD# SCLK SDATA VDD48 48_0 48_ FS Pin Configuration ICS VDDL CPUCLK0 CPUCLK SDRAM0 SDRAM VDDSDR SDRAM SDRAM3 SDRAM4 VDDSDR SDRAM5 SDRAM6 VDDSDR SDRAM7 SDRAM8 SDRAM9 VDDSDR SDRAM0 SDRAM VDDSDR SDRAM Functionality 56-Pin 300mil SSOP * This input has a 50KW pull-down to. Block Diagram X X FS(:0) PD# SDATA SCLK XTAL OSC Control Logic Config Reg PLL Spread Spectrum / / /3 / REF0 CPU66/00/33 [:0] 3V66 (:0) 3 SDRAM (:0) 3 PCICLK (:0) IOAPIC PLL 48 (:0) FS FS0 FS 0 0 X Tristate 0 X Test Power Groups Analog VDDREF = X, X VDDA = PLL VDD48 = PLL Function Active CPU = 66 SDRAM = 00 Active CPU = 00 SDRAM = 00 Active CPU = 33 SDRAM = 33 Active CPU = 33 SDRAM = 00 Digital VDD3V66, VDDPCI VDDSDR, VDDL Rev B 0/6/00 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

2 General Description The ICS950-8 is part of a two chip clock solution for 80/80E and 85 type chipset. Combined with the ICS9-7, the ICS950-8 provides all necessary clock signals for such a system. Spread spectrum may be enabled through I C programming. Spread spectrum typically reduces EMI by 8dB to 0 db. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS950-8 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Pin Configuration PIN NUMBER PIN NAME IOAPIC, 56 VDDL 4 5, 9, 4, 0, 5, 3, 35, 40, 44, 49 FS REF0 VDD 6 X 7 X 3, 8, 3, 7, 9, 4, 30, 34, 39, 43, 48, 5, 55 TYPE DESCRIPTION O UT.5V clock output running at PWR IN.5V power supply for CPU & IOAPIC Function Select pin. Determines CPU frequency, all output functionality O UT 3.3V, 4.38 reference clock output. PWR IN OUT PWR,, 0 3V66 (:0) OUT 8, 8 FS (, 0) 6, 5 PCICLK[:0] PD# SCLK IN OUT IN IN 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X Crystal output, nominally Has internal load cap (33pF) Ground pins for 3.3V supply 3.3V Fixed 66 clock outputs for HUB Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page V PCI clock outputs Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock pin of I C circuitry 5V tolerant 3 SDATA I/ O Data pin for I C circuitry 5V tolerant 6, 7 48_ 0 O UT 3.3V Fixed 48 clock outputs. 9, 3, 33, 36, 37, 38, 4, 4, 45, 46, 47, 50, 5 SDRAM (:0) 54, 53 CPUCLK (:0) OUT OUT 3.3V output running 00. All SDRAM outputs can be turned off through I C.5V Host bus clock output. 66, 00 or 33 depending on FS (:0) pins.

3 Power Down Waveform Note. After PD# is sampled active (Low) for consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion.. Power-up latency <3ms. 3. Waveform shown for 00 Maximum Allowed Current 85 Condition Powerdown Mode (PWRDWN# = 0 Full Active 66 FS[:0] = 00 Full Active 00 FS[:0] = 0 Full Active 33 FS[:0] = Max.5V supply consumption Max discrete cap loads, Vddq =.65V All static inputs = Vddq3 or Max.5V supply consumption Max discrete cap loads, Vddq = 3.465V All static inputs = Vddq3 or Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66 PCICLK REF, 48 Osc VCOs 0 LOW LOW LOW LOW LOW LOW OFF OFF ON ON ON ON ON ON ON ON 3

4 Truth Table FS FS0 FS CPU SDRAM 3V66 PCI 48 REF IOAPIC 0 0 X Tristate Tristate Tristate Tristate Tristate Tristate Tristate 0 X TCLK/ TCLK/ TCLK/ 3 TCLK/ 6 TCLK/ TCLK TCLK/ Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD) Desctiption B it7 ICS Reserved bit (Note ) 0 B it6 ICS Reserved bit (Note ) 0 B it5 ICS Reserved bit (Note ) 0 B it4 ICS Reserved bit (Note ) 0 B it3 ICS Reserved bit (Note ) 0 B it Undefined bit (Note 3) B it Undefined bit (Note 3) 0 0 FS0 FS CPUCLK SDRAM 3V66 PCICLK IOAPIC PWD X X 0 Note Note : For system operation, the BSEL lines of the CPU will program FS0, FS for the appropriate CPU speed, always with SDRAM = 00. After BIOS verifies the SDRAM is PC33 speed, then bit 0 can be written from the default 0 to to change the SDRAM output frequency from 00 to 33. This will only change if the CPU is at the 33 FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch free during this transition, and only SDRAM will change. Note : "ICS RESERVED BITS" must be writtern as "0". Note3: Undefined bits can be written either as " or 0" 4

5 Byte 0: Control Register ( = enable, 0 = disable) B it Pin# Name PWD Description 7 - Reserved ID 6 - Reserved ID 5 - Reserved ID 4 - Reserved ID 3 - SpreadSpectrum (=On/0=Off) Reserved ID Note: Reserved ID bits must be written as "0" Byte : Control Register ( = enable, 0 = disable) B it Pin# Name PWD Description 7 38 SDRAM7 6 4 SDRAM6 5 4 SDRAM SDRAM SDRAM3 47 SDRAM 50 SDRAM 0 5 SDRAM0 Byte : Control Register ( = enable, 0 = disable) B it Pin# Name PWD Description 7 3V66- (AGP) 6 9 SDRAM 5 3 SDRAM 4 33 SDRAM SDRAM9 37 SDRAM8 6 PCICLK 0 - Reserved Notes:. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.. PWD = Power on Default 3. Undefined bit can be wirtten with either a "" or "0". 5

6 Byte 4: Reserved Register ( = enable, 0 = disable) B it Pin# Name PWD Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved - Reserved - Reserved 0 - Reserved Notes:. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.. PWD = Power on Default Group Timing Relationship Table CPU to Group CPU to SDRAM to SDRAM 3V66 3V66 CPU 66 SDRAM 00 Offset Tolerance CPU 00 SDRAM 00 Offset Tolerance CPU 33 SDRAM 00 Offset Tolerance CPU 33 SDRAM 33 Offset Tolerance -.5ns 5.0ns 3.75ns 7.5ns 5.0ns -3.75ns 3V66 to PCI.5-3.5ns.5-3.5ns.5-3.5ns.5-3.5ns PCI to PCI USB & DOT.0ns Asynch N/ A Asynch N/ A Asynch N/ A Asynch N/ A 6

7 Absolute Maximum Ratings Core Supply Voltage V I/O Supply Voltage V Logic Inputs V to V DD +0.5 V Ambient Operating Temperature C to +70 C Maximum Case Operating Temperature C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0-70C; Supply Voltage V DD = 3.3 V +/-5%, V DDL =.5 V +/-5% (unless otherwise stated) Input High Voltage V IH V DD +0.3 V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD -5 5 µa Input Low Current I IL V IN = 0 V; Inputs with no pull-up resistors -5 I IL V IN = 0 V; Inputs with pull-up resistors -00 µa C L = 0 66/ C L = 0 00/ C L = 0 33/ I DD3.3OP C L = 0 33/ C L = Max 66/ C L = Max 00/ C L = Max 33/ Operating Supply C L = Max 33/ Current C L = 0 66/ C L = 0 00/00 8 C L = 0 33/ I DD.5OP C L = 0 33/ C L = Max 66/ C L = Max 00/ C L = Max 33/ C L = Max 33/ Powerdown Current I DD3.3PD C L = Max loads I DD.5PD Input address VDD or < 0 µa Input Frequency F i V DD = 3.3 V Transition time T trans To st crossing of target frequency 3 ms Settling time T s From st crossing to % target frequency 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target frequency 3 ms Delay t PZH,t PZL Output enable delay (all outputs) 0 ns t PHZ,t PLZ Output disable delay (all outputs) 0 ns Guaranteed by design, not 00% tested in production. 7

8 Electrical Characteristics - CPU T A = 0-70C; V DDL =.5 V +/-5%; C L = 0-0 pf (unless otherwise specified) Output Impedance R DSPB V O = V DD *(0.5) Ω Output Impedance R DSNB V O = V DD *(0.5) Ω Output High Voltage V OHB I OH = - V Output Low Voltage V OLB I OL = 0.4 V Output High Current Output Low Current I OHB I OLB V MIN =.0 V V MAX =.375 V -9-7 V MIN =. V 7 54 V MAX = 0.3 V 30 Rise Time t rb V OL = 0.4 V, V OH =.0 V ns Fall Time t fb V OH =.0 V, V OL = 0.4 V ns Duty Cycle d tb V T =.5 V % Skew window t skb V T =.5 V ps Jitter, Cycle-to-cycle t jcyc-cycb V T =.5 V ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - 3V66 T A = 0-70C; V DD = 3.3 V +/-5%; C L = 0-0 pf (unless otherwise specified) Output Impedance R DSPB V O = V DD *(0.5) 4 55 Ω Output Impedance R DSNB V O = V DD *(0.5) Ω Output High Voltage V OH I OH = -.4 V Output Low Voltage V OL I OL = 0.55 V Output High Current Output Low Current I OH I OL V MIN =.0 V V MAX = 3.35 V V MIN =.95 V V MAX = 0.4 V 9 38 Rise Time t r V OL = 0.4 V, V OH =.4 V ns Fall Time t f V OH =.4 V, V OL = 0.4 V ns Duty Cycle d t V T =.5 V % Skew window t sk V T =.5 V ps Jitter, Cycle-to-cycle t jcyc-cyc V T =.5 V ps Guaranteed by design, not 00% tested in production. 8

9 Electrical Characteristics - IOAPIC T A = 0-70C; V DDL =.5 V +/-5%; C L = 0-0 pf (unless otherwise specified) Output Impedance R DSP4B V O = V DD *(0.5) Ω Output Impedance R DSN4B V O = V DD *(0.5) Ω Output High Voltage V OH4B I OH = - V Output Low Voltage V OL4B I OL = 0.4 V Output High Current Output Low Current I OH4B I OL4B V MIN =.0 V V MAX =.375 V -9-7 V MIN =. V 7 54 V MAX = 0.3 V 30 Rise Time t r4b V OL = 0.4 V, V OH =.0 V ns Fall Time t f4b V OH =.0 V, V OL = 0.4 V ns Duty Cycle d t4b V T =.5 V % Jitter, Cycle-to-cycle t jcyc-cyc4b V T =.5 V ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - SDRAM T A = 0-70C; V DD = 3.3 V +/-5%; C L = 0-30 pf (unless otherwise specified) Output Impedance R DSP3B V O = V DD *(0.5) 0 4 Ω Output Impedance R DSN3B V O = V DD *(0.5) Ω Output High Voltage V OH3 I OH = -.4 V Output Low Voltage V OL3 I OL = 0.4 V Output High Current Output Low Current I OH3 I OL3 V MIN =.0 V V MAX = 3.35 V V MIN =.0 V V MAX = 0.4 V 9 53 Rise Time t r3 V OL = 0.4 V, V OH =.4 V ns Fall Time t f3 V OH =.4 V, V OL = 0.4 V ns Duty Cycle d t3 V T =.5 V % Skew window t sk3 V T =.5 V 0 50 ps Jitter, Cycle-to-cycle t jcyc-cyc3 V T =.5 V ps Guaranteed by design, not 00% tested in production. 9

10 Electrical Characteristics - PCI T A = 0-70C; V DD = 3.3 V +/-5%; C L = 0-30 pf (unless otherwise specified) Output Impedance R DSPB V O = V DD *(0.5) 5 55 Ω Output Impedance R DSNB V O = V DD *(0.5) 5 55 Ω Output High Voltage V OH I OH = -.4 V Output Low Voltage V OL I OL = 0.55 V Output High Current Output Low Current I OH I OL V MIN =.0 V V MAX = 3.35 V V MIN =.95 V V MAX = 0.4 V 9 38 Rise Time t r V OL = 0.4 V, V OH =.4 V ns Fall Time t f V OH =.4 V, V OL = 0.4 V ns Duty Cycle d t V T =.5 V % Skew window t sk V T =.5 V ps Jitter, Cycle-to-cycle t jcyc-cyc V T =.5 V ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - REF, 48_0 (Pin 6) T A = 0-70C; V DD = 3.3 V +/-5%; C L = 0-0 pf (unless otherwise specified) Output Impedance R DSP5B V O = V DD *(0.5) Ω Output Impedance R DSN5B V O = V DD *(0.5) Ω Output High Voltage V OH5 I OH = -.4 V Output Low Voltage V OL5 I OL = 0.55 V Output High Current Output Low Current I OH5 I OL5 V MIN =.0 V V MAX = 3.35 V - -3 V MIN =.95 V 9 54 V MAX = 0.4 V 6 7 Rise Time t r5 V OL = 0.4 V, V OH =.4 V ns Fall Time t f5 V OH =.4 V, V OL = 0.4 V ns Duty Cycle d t5 V T =.5 V % Jitter, Cycle-to-cycle t jcyc-cyc5 V T =.5 V, Fixed clocks ps Jitter, Cycle-to-cycle t jcyc-cyc5 V T =.5 V, Ref clocks ps Guaranteed by design, not 00% tested in production. 0

11 Electrical Characteristics - 48_ (Pin 7) T A = 0-70C; V DD = 3.3 V +/-5%; C L = 0-5 pf (unless otherwise specified) Output Impedance R DSP3B V O = V DD *(0.5) Ω Output Impedance R DSN3B V O = V DD *(0.5) Ω Output High Voltage V OH3 I OH = -.4 V Output Low Voltage V OL3 I OL = 0.55 V Output High Current Output Low Current I OH3 I OL3 V MIN =.0 V V MAX = 3.35 V V MIN =.0 V V MAX = 0.4 V 8 53 Rise Time t r3 V OL = 0.4 V, V OH =.4 V ns Fall Time t f3 V OH =.4 V, V OL = 0.4 V ns Duty Cycle d t3 V T =.5 V % Jitter, Cycle-to-cycle t jcyc-cyc3b V T =.5 V ps Guaranteed by design, not 00% tested in production.

12 Group Skews (CPU 66, SDRAM 00) T A = 0-70º C; V DD = 3.3 V +/-5%, V DDL =.5 V +/-5% CPU & IOAPIC load (lumped) = 0 pf; PCI, SDRAM, 3V66 load (lumped) = 30 pf Refer to Group Offset Waveforms diagram for definition of transition edges. CPU to SDRAM Skew T sk CPU-SDRAM ns V, V Skew Window T w CPU-SDRAM ps CPU to 3V66 Skew T sk CPU-3V ns V, V Skew Window T w CPU-3V ps SDRAM to 3V66 Skew T sk SDRAM-3V ps SDRAM, V Skew Window T w SDRAM-3V ps 3V66 to PCI Skew T sk 3V66-PCI ns 3V66, V Skew Window T w 3V66-PCI ps IOAPIC to PCI Skew T sk IOAPIC-PCI ns V, V Skew Window T w IOAPIC-PCI 0 0 ns Guaranteed by design, not 00% tested in production. Group Skews (CPU 00, SDRAM 00) T A = 0-70º C; V DD = 3.3 V +/-5%, V DDL =.5 V +/-5% CPU & IOAPIC load (lumped) = 0 pf; PCI, SDRAM, 3V66 load (lumped) = 30 pf Refer to Group Offset Waveforms diagram for definition of transition edges. CPU to SDRAM Skew T sk CPU-SDRAM ns V, V Skew Window T w CPU-SDRAM ps CPU to 3V66 Skew T sk CPU-3V ns V, V Skew Window T w CPU-3V ps SDRAM to 3V66 Skew T sk SDRAM-3V ps SDRAM, V Skew Window T w SDRAM-3V ps 3V66 to PCI Skew T sk 3V66-PCI ns 3V66, V Skew Window T w 3V66-PCI ps IOAPIC to PCI Skew T sk IOAPIC-PCI ns V, V Skew Window T w IOAPIC-PCI 0 0 ns Guaranteed by design, not 00% tested in production.

13 Group Skews (CPU 33, SDRAM 33) T A = 0-70º C; V DD = 3.3 V +/-5%, V DDL =.5 V +/-5% CPU & IOAPIC load (lumped) = 0 pf; PCI, SDRAM, 3V66 load (lumped) = 30 pf Refer to Group Offset Waveforms diagram for definition of transition edges. CPU to SDRAM Skew T sk3 CPU-SDRAM ns V, V Skew Window T w3 CPU-SDRAM ps CPU to 3V66 Skew T sk3 CPU-3V ps V, V Skew Window T w3 CPU-3V ps SDRAM to 3V66 Skew T sk3 SDRAM-3V ps SDRAM, V Skew Window T w3 SDRAM-3V ps 3V66 to PCI Skew T sk3 3V66-PCI ns 3V66, V Skew Window T w3 3V66-PCI ps IOAPIC to PCI Skew T sk3 IOAPIC-PCI ns V, V Skew Window T w3 IOAPIC-PCI 0 0 ns Guaranteed by design, not 00% tested in production. Group Skews (CPU33, SDRAM 00) T A = 0-70º C; V DD = 3.3 V +/-5%, V DDL =.5 V +/-5% CPU & IOAPIC load (lumped) = 0 pf; PCI, SDRAM, 3V66 load (lumped) = 30 pf Refer to Group Offset Waveforms diagram for definition of transition edges. CPU to SDRAM Skew T sk3 CPU-SDRAM V, V ps Skew Window T w3 CPU-SDRAM ps CPU to 3V66 Skew T sk3 CPU-3V66 V, V ps Skew Window T w3 CPU-3V ps SDRAM to 3V66 Skew T sk3 SDRAM-3V66 SDRAM, V ps Skew Window T w3 SDRAM-3V ps 3V66 to PCI Skew T sk3 3V66-PCI 3V66, V ns Skew Window T w3 3V66-PCI ps IOAPIC to PCI Skew T sk3 IOAPIC-PCI V, V ns Skew Window T w3 IOAPIC-PCI 0 0 ns Guaranteed by design, not 00% tested in production. 3

14 0ns 0ns 0ns 30ns 40ns Cycle Repeats CPU 66 CPU 00 CPU 33 SDRAM 00 SDRAM 33 3V66 PCI 33 APIC 33 REF 4.38 USB 48 Group Offset Waveforms 4

15 General I C serial interface information The information in this section assumes familiarity with I C programming. For more information, contact ICS for an I C programming application note. How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Notes: Controller (Host) Start Address D (H) Dummy Command Code Dummy Byte Count Byte 0 Byte Byte Byte 3 Byte 4 Byte 5 Stop How to Write: ICS (Slave/Receiver) Controller (Host) Start Address D3 (H) ICS (Slave/Receiver) Byte Count. The ICS clock generator is a slave/receiver, I C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.. The data transfer rate supported by this clock generator is 00K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. Stop How to Read: Byte 0 Byte Byte Byte 3 Byte 4 Byte 5 5

16 General Layout Precautions: ) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. VDD Ferrite Bead C µf/0v Tantalum C µf/0v Tantalum Ferrite Bead VDD ) Make all power traces and ground traces as wide as the via pad for lower inductance V Power Route Notes: All clock outputs should have provisions for a 5pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. C C C3 Clock Load Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed Component Values: C : Crystal load values determined by user C : µf/0v/d case/tantalum AVX TAJD6M00R C3 : 5pF capacitor FB = Fair-Rite products X All unmarked capacitors are 0.0µF ceramic Ground V Power Route Connections to VDD:

17 SYMBOL In Millimeters COMMON DIMENSIONS In Inches COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e BASIC 0.05 BASIC h L N SEE VARIATIONS SEE VARIATIONS α VARIATIONS N D mm. D (inch) MIN MAX MIN MAX Ordering Information ICS950yF-8-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number ( or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 7 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.