DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9"

Transcription

1 Integrated Circuit Systems, Inc. ICS93738 DDR and SDRAM Buffer Recommended Application: DDR & SDRAM fanout buffer, for VIA P4X/KT66/333 chipsets. Product Description/Features: Low skew, fanout buffer to differential clock distribution I C for functional and output control Feedback pin for input to output synchronization Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + DDR DIMMs Frequency supports up to 00MHz (DDR400) Supports Power Down Mode for power mananagement CMOS level control signal input Switching Characteristics: OUTPUT - OUTPUT skew: <00ps SDRAM OUTPUT - OUTPUT skew: <50ps DDR Output Rise and Fall Time for DDR outputs: 600ps - 950ps DUTY CYCLE: 47% - 53% DDR DUTY CYCLE: 45%- 55% SDRAM FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM DDRT_SDRAM DDRC_SDRAM3 DDRT_SDRAM4 DDRC_SDRAM5 BUF_ DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM0 DDRC5_SDRAM SDATA Pin Configuration ICS SEL_DDR* VDD.5 DDRT DDRC DDRT0 DDRC0 VDD.5 DDRT9 DDRC9 VDD.5 PD#* DDRT8 DDRC8 VDD.5 DDRT7 DDRC7 DDRT6 DDRC6 SCLK 48-Pin SSOP *Internal Pull-up Resistor of 0K to VDD Block Diagram Functionality BUF_ FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM DDRT_SDRAM DDRC_SDRAM3 MODE P 48 DDR Mode SEL_DDR= VDD 3.3_.5.5V P 4, 5, 6, 7, 0,, 5, 6, 9, 0,, These outputs will be DDR outputs SCLK SDATA SEL_DDR* PD# Control Logic DDRT_SDRAM4 DDRC_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDR/SD Mode SEL_DDR=0 3.3V These outputs will be standard SDRAM outputs DDRT5_SDRAM0 DDRC5_SDRAM DDRT(:6) DDRC (:6)

2 Pin Descriptions P NUMBER P NAME TYPE DESCRIPTION FB_OUT, 8,, 7, 3, VDD3.3_. 5 3, 9, 4, 8, 6, 3, 35, 40, 46 45, 43, 39, 34, 30, 8, 44, 4, 38, 33, 9, 7,, 9, 5, 0, 6, 4 OUT PWR PWR Feedback output, dedicated for external feedback.5v or 3.3V voltage supply to pins 4, 5, 6, 7, 0,, 5, 6, 9, 0,, Ground D DRT ( :6) O UT "True" Clock of differential pair outputs. DDRC (:6) DDRT (5:0) SDRAM (0, 8, 6, 4,, 0) DDRC (5:0), 0, 6,, 7, 5 SDRAM (, 9, 7, 5, 3,,) 3 BUF_ O UT "Complementory" clocks of differential pair outputs. OUT OUT "True" Clock of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input " Complementory" clocks of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input Single ended buffer input 4 SDAT A 5 SCLK 3, 37, 4, 47 VDD PD# 48 SEL_DDR I/ O PWR Data pin for I C circuitry 5V tolerant Clock input of I C input, 5V tolerant input.5v voltage supply Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled. The latency of the power down will not be greater than 3ms. Select input for DDR mode or DDR/SD mode 0=DDR/SD mode =DDR mode

3 Byte 6: Output Control (= enable, 0 = disable) B IT P# PWD DESCRIPTION 7 48 SEL_DDR (Read back only) 6 - (Reserved) 5 - (Reserved) 4 - (Reserved) 3 45, 44 DDRT, DDRC 43, 4 DDRT0, DDRC0 39, 38 DDRT9, DDRC9 0 34, 33 DDRT8, DDRC8 Byte 7: Output Control (= enable, 0 = disable) B IT P# PWD DESCRIPTION 7 30, 9 DDRT7, DDRC7 6 8, 7 DDRT6, DDRC6 5, DDRT5, SDRAM0 DDRC5_SDRAM 4 9, 0 DDRT4_SDRAM8 DDRC4_SDRAM9 3 5, 6 DDRT3_SDRAM6 DDRC3_SDRAM7 0, DDRT_SDRAM4 DDRC_SDRAM5 6, 7 DDRT_SDRAM DDRC_SDRAM3 0 4, 5 DDRT0_SDRAM DDRC0_SDRAM0 3

4 Absolute Maximum Ratings Supply Voltage (VDD & VDD.5) V to 3.6V Logic Inputs V to V DD +0.5 V Ambient Operating Temperature C to +85 C Case Temperature C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input / Supply / Common Output Parameters - SDRAM SEL_DDR=0, SDRAM Outputs, V DD3.3_.5 = 3.3V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Input High Current I IH V = V DD or 0 µa Input Low Current I IL V = V DD or -00 µa I DD3.3_.5 C L = 0 pf at 33 MHz ma Operating Supply Current I DD.5 C L = 0 pf at 33 MHz ma I DDPD C L = 0 pf 0 0 µa Output High Current I OH V DD = 3.3V, V OUT = V -8 ma Output Low Current I OL V DD = 3.3V, V OUT =.V 6 ma High-level Output Voltage V OH V DD = 3.3V, IOH = -ma V Low-level Output Voltage V OL V DD = 3.3V, IOL = ma 0.4 V Input Capacitance C V = V DD or pf. Guaranteed by design, not 00% tested in production. Recommended Operating Conditions - SDRAM SEL_DDR=0, SDRAM Outputs, V DD3.3_.5 = 3.3V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Power Supply Voltage V DD3.3_ V DD V Input High Voltage V IH SEL_DDR, PD# inputs V Input Low Voltage V IL SEL_DDR, PD# inputs 0.8 V Input Voltage Level V V 4

5 Electrical Characteristics - Input / Supply / Common Output Parameters - DDR SEL_DDR=, DDR/DDR_SDRAM Outputs, V DD3.3_.5 =.5V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Input High Current I IH V = V DD or 0 µa Input Low Current I IL V = V DD or -00 µa I DD3.3_.5 C L = 0 pf at 33 MHz 5 00 ma Operating Supply Current I DD.5 C L = 0 pf at 33 MHz ma I DDPD C L = 0 pf 0 0 µa Output High Current I OH V DD =.5V, V OUT = V -8 ma Output High Current I OL V DD =.5V, V OUT =.V 6 ma High-level Output Voltage V OH V DD =.5V, IOH = -ma.7 V Low-level Output Voltage V OL V DD =.5V, IOL = ma 0.46 V Output differential-pair V crossing voltage C DD / V DD / + 0. Input Capacitance C V = V DD or pf. Guaranteed by design, not 00% tested in production. V Recommended Operating Conditions - DDR SEL_DDR=, DDR/DDR_SDRAM Outputs, V DD3.3_.5 =.5V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Power Supply Voltage V DD3.3_ V DD V Input High Voltage V IH SEL_DDR, PD# inputs V Input Low Voltage V IL SEL_DDR, PD# inputs 0.8 V Input Voltage Level V V 5

6 Switching Characteristics T A = 0-85 o C PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Operating Frequency MHz Input clock duty cycle d tin % Output to output Skew (DDR outputs) Output to output Skew (SDRAM outputs) T skewddr T skewsd V T = 50%, Not including FB_OUT to outputs V T =.5V ps ps Duty Cycle,3 V T = 50%, 66 MHz to 00 MHz, w/loads DC DDR (DDR outputs) V T = 50%, 0 MHz to 67 MHz, w/loads % Duty Cycle,3 (SDRAM outputs) DC SD V T =.5V, w/loads % Rise Time, Fall Time (DDR Single-ended 0-80 % t rd, t fd outputs) 33 MHz, Load = 0Ω / pf Rise Time, Fall Time Single-ended V OL = 0.4V, V OH =.4V t rs, t fs (SDRAM outputs) 33 MHz, Load = pf ps ns SDRAM Buffer LH Propagation Delay, t PLH Input edge greater than V/ns. Guaranteed by design, not 00% tested in production.. Refers to transistion on non-inverting output. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t / t, where the cycle time (t) decreases as the frequency increases. Switching Waveforms Duty Cycle Timing.5 ns SDRAM Buffer HL Propagation Delay, t PHL Input edge greater than V/ns.9.5 ns t t.5v.5v.5v SDRAM Buffer LH and HL Propagation Delay PUT.5V.5V OUTPUT.5V.5V t 6 t 7 6

7 . The ICS clock generator is a slave/receiver, I C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.. The data transfer rate supported by this clock generator is 00K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. General I C serial interface information The information in this section assumes familiarity with I C programming. For more information, contact ICS for an I C programming application note. How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Notes: Controller (Host) Start Address D4(H) Dummy Command Code Dummy Byte Count Byte 0 Byte Byte Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Stop How to Write: ICS (Slave/Receiver) How to Read: Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Controller (Host) Start Address D5 (H) Stop How to Read: ICS (Slave/Receiver) Byte Count Byte 0 Byte Byte Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 7

8 N c 300 mil SSOP DEX AREA D E A E h x 45 α L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS M MAX M MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e BASIC 0.05 BASIC h L N SEE VARIATIONS SEE VARIATIONS α e b A -C- - SEATG PLANE VARIATIONS D mm. D (inch) N M MAX M MAX (.004) C Reference Doc.: JEDEC Publication 95, MO mil SSOP Ordering Information ICS93738yFLFT Example: ICS XXXX y F LF - T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 8

9 Revision History Rev. Issue Date Description Page # B //006 Added LF to Ordering Information 8 9

ICS Frequency Generator & Integrated Buffers for PENTIUM/Pro TM. Integrated Circuit Systems, Inc. General Description.

ICS Frequency Generator & Integrated Buffers for PENTIUM/Pro TM. Integrated Circuit Systems, Inc. General Description. Integrated Circuit Systems, Inc. ICS9248-39 Frequency Generator & Integrated Buffers for PENTIUM/Pro TM General Description The ICS9248-39 generates all clocks required for high speed RISC or CISC microprocessor

More information

ICS9P935 ICS9P935. DDR I/DDR II Phase Lock Loop Zero Delay Buffer 28-SSOP/TSSOP DATASHEET. Description. Pin Configuration

ICS9P935 ICS9P935. DDR I/DDR II Phase Lock Loop Zero Delay Buffer 28-SSOP/TSSOP DATASHEET. Description. Pin Configuration DATASHEET ICS9P935 Description DDR I/DDR II Zero Delay Clock Buffer Output Features Low skew, low jitter PLL clock driver Max frequency supported = 400MHz (DDRII 800) I 2 C for functional and output control

More information

ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Power Groups. Ground Groups. 28 pin SOIC and SSOP

ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Power Groups. Ground Groups. 28 pin SOIC and SSOP Integrated Circuit Systems, Inc. ICS948-60 Pentium/Pro TM System Clock Chip General Description The ICS948-60 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style

More information

ICS Low Skew PCI / PCI-X Buffer. General Description. Block Diagram. Pin Configuration. Pin Descriptions OE CLK0

ICS Low Skew PCI / PCI-X Buffer. General Description. Block Diagram. Pin Configuration. Pin Descriptions OE CLK0 Low Skew PCI / PCI-X Buffer General Description The ICS9112-27 is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X applications

More information

ICS Frequency Generator & Integrated Buffers for PENTIUM/Pro TM. Integrated Circuit Systems, Inc. General Description.

ICS Frequency Generator & Integrated Buffers for PENTIUM/Pro TM. Integrated Circuit Systems, Inc. General Description. Integrated Circuit Systems, Inc. ICS9248-39 Frequency Generator & Integrated Buffers for PENTIUM/Pro TM General Description The ICS9248-39 generates all clocks required for high speed RISC or CISC microprocessor

More information

ICS2304NZ-1 LOW SKEW PCI/PCI-X BUFFER. Description. Features. Block Diagram DATASHEET

ICS2304NZ-1 LOW SKEW PCI/PCI-X BUFFER. Description. Features. Block Diagram DATASHEET DATASHEET ICS2304NZ-1 Description The ICS2304NZ-1 is a high-performance, low skew, low jitter PCI/PCI-X clock driver. It is designed to distribute high-speed signals in PCI/PCI-X applications operating

More information

LOW SKEW 1 TO 4 CLOCK BUFFER. Features

LOW SKEW 1 TO 4 CLOCK BUFFER. Features DATASHEET ICS651 Description The ICS651 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is a low skew, small clock buffer. IDT makes many non-pll and

More information

ICS542 CLOCK DIVIDER. Features. Description. Block Diagram DATASHEET. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

ICS542 CLOCK DIVIDER. Features. Description. Block Diagram DATASHEET. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 DATASHEET ICS542 Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide

More information

PCK MHz I 2 C differential 1:10 clock driver INTEGRATED CIRCUITS

PCK MHz I 2 C differential 1:10 clock driver INTEGRATED CIRCUITS INTEGRATED CIRCUITS 70 190 MHz I 2 C differential 1:10 clock driver Product data Supersedes data of 2001 May 09 File under Integrated Circuits, ICL03 2001 Jun 12 FEATURES Optimized for clock distribution

More information

ICS9112A-16. Low Skew Output Buffer. General Description. Pin Configuration. Block Diagram. 8 pin SOIC, TSSOP

ICS9112A-16. Low Skew Output Buffer. General Description. Pin Configuration. Block Diagram. 8 pin SOIC, TSSOP Low Skew Output Buffer General Description The ICS92A-6 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF

More information

ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS. Description. Features. Block Diagram PRELIMINARY DATASHEET

ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS. Description. Features. Block Diagram PRELIMINARY DATASHEET PRELIMINARY DATASHEET ICS1493-17 Description The ICS1493-17 is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device

More information

ICS HDTV AUDIO/VIDEO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET

ICS HDTV AUDIO/VIDEO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET DATASHEET ICS662-03 Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior

More information

MK1413 MPEG AUDIO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET

MK1413 MPEG AUDIO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET DATASHEET MK1413 Description The MK1413 is the ideal way to generate clocks for MPEG audio devices in computers. The device uses IDT s proprietary mixture of analog and digital Phase-Locked Loop (PLL)

More information

Features VDD 1 CLK1. Output Divide PLL 2 OE0 GND VDD. IN Transition Detector CLK1 INB. Output Divide PLL 2 OE0 GND

Features VDD 1 CLK1. Output Divide PLL 2 OE0 GND VDD. IN Transition Detector CLK1 INB. Output Divide PLL 2 OE0 GND DATASHEET ICS58-0/0 Description The ICS58-0/0 are glitch free, Phase Locked Loop (PLL) based clock multiplexers (mux) with zero delay from input to output. They each have four low skew outputs which can

More information

ICS97U2A845A Advance Information

ICS97U2A845A Advance Information Integrated Circuit Systems, Inc. ICS97U2A845A 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR DIMM logic solution

More information

ICS GLITCH-FREE CLOCK MULITPLEXER. Features. Description. Block Diagram DATASHEET

ICS GLITCH-FREE CLOCK MULITPLEXER. Features. Description. Block Diagram DATASHEET DATASHEET ICS580-01 Description The ICS580-01 is a clock multiplexer (mux) designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by an input

More information

ICS9FG107. Programmable FTG for Differential P4 TM CPU, PCI-Express & SATA Clocks DATASHEET. Description

ICS9FG107. Programmable FTG for Differential P4 TM CPU, PCI-Express & SATA Clocks DATASHEET. Description DATASHEET Programmable FTG for Differential P4 TM CPU, PCI-Express & SATA Clocks ICS9FG107 Description ICS9FG107 is a Frequency Timing Generator that provides 7 differential output pairs that are compliant

More information

ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET DATASHEET ICS180-51 Description The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology

More information

PI6C :8 Clock Driver for Intel PCI Express Chipsets. Description. Features. Pin Configuration. Block Diagram

PI6C :8 Clock Driver for Intel PCI Express Chipsets. Description. Features. Pin Configuration. Block Diagram Features Eight Pairs of Differential Clocks Low skew < 50ps Low Cycle-to-cycle jitter < 50ps Output Enable for all outputs Outputs Tristate control via SMBus Power Management Control Programmable PLL Bandwidth

More information

2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features

2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential

More information

Description YT0 YC0 YT1 YC1 YT2 YC2 YT3 YC3 YT4 YC4 YT5 YC5 YT6 YC6 YT7 YC7 YT8 YC8 YT9 YC9 FBOUTT FBOUTC

Description YT0 YC0 YT1 YC1 YT2 YC2 YT3 YC3 YT4 YC4 YT5 YC5 YT6 YC6 YT7 YC7 YT8 YC8 YT9 YC9 FBOUTT FBOUTC Differential Clock Buffer/Driver Features Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications 1:10 differential outputs External Feedback pins (, FBINC) are used to

More information

ICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

ICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET DATASHEET ICS660 Description The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses

More information

LOCO PLL CLOCK MULTIPLIER. Features

LOCO PLL CLOCK MULTIPLIER. Features DATASHEET ICS501A Description The ICS501A LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands

More information

ICS512 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

ICS512 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET DATASHEET ICS512 Description The ICS512 is the most cost effective way to generate a high-quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. The name

More information

1.8V Low-Power Wide-Range Frequency Clock Driver CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT2 CLK_INT CLK_INC CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 AGND

1.8V Low-Power Wide-Range Frequency Clock Driver CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT2 CLK_INT CLK_INC CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 AGND Integrated Circuit Systems, Inc. ICS98ULPA877A.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR2 DIMM logic solution

More information

ICS502 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

ICS502 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET DATASHEET ICS502 Description The ICS502 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The

More information

2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux

2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux 2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features F MAX = 500MHz 10 pairs of differential LVPECL outputs Low additive jitter,

More information

ICS7151A-50 SPREAD SPECTRUM CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

ICS7151A-50 SPREAD SPECTRUM CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET DATASHEET ICS7151A-50 Description The ICS7151A-50 is a clock generator for EMI (Electromagnetic Interference) reduction. Spectral peaks are attenuated by modulating the system clock frequency. Down or

More information

ICS LOW PHASE NOISE CLOCK MULTIPLIER. Features. Description. Block Diagram DATASHEET

ICS LOW PHASE NOISE CLOCK MULTIPLIER. Features. Description. Block Diagram DATASHEET DATASHEET ICS601-01 Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase

More information

MK AMD GEODE GX2 CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

MK AMD GEODE GX2 CLOCK SOURCE. Description. Features. Block Diagram DATASHEET DATASHEET MK1491-09 Description The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked

More information

PCI-EXPRESS CLOCK SOURCE. Features

PCI-EXPRESS CLOCK SOURCE. Features DATASHEET ICS557-01 Description The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.

More information

MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET DATASHEET MK2705 Description The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal.

More information

Features. Phase Detector, Charge Pump, and Loop Filter. External feedback can come from CLK or CLK/2 (see table on page 2)

Features. Phase Detector, Charge Pump, and Loop Filter. External feedback can come from CLK or CLK/2 (see table on page 2) DATASHEET ICS570 Description The ICS570 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended

More information

ICS663 PLL BUILDING BLOCK. Description. Features. Block Diagram DATASHEET

ICS663 PLL BUILDING BLOCK. Description. Features. Block Diagram DATASHEET DATASHEET ICS663 Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled

More information

DESCRIPTION CLK1 CLK2 GND CLK1 CLK2 VDD CLK3 CLK4 VDD

DESCRIPTION CLK1 CLK2 GND CLK1 CLK2 VDD CLK3 CLK4 VDD PL123-05N PL123-09N FEATURES Output fanout buffer for DC to 134MHz Output Options: o 1:5 output fanout with PL123-05 o 1:9 output fanout with PL123-09 Low power consumption for portable applications Low

More information

3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE IDT23S05 FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs

More information

ICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

ICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET DATASHEET ICS511 Description The ICS511 LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands

More information

Description. Applications

Description. Applications High Performance HCSL Fanout Buffer Features ÎÎ2 HCSL outputs ÎÎUp to 250MHz output frequency ÎÎUltra low additive phase jitter: < 0.1 ps (typ) ÎÎTwo selectable inputs ÎÎLow delay from input to output

More information

Features. Applications

Features. Applications 267MHz 1:2 3.3V HCSL/LVDS Fanout Buffer PrecisionEdge General Description The is a high-speed, fully differential 1:2 clock fanout buffer with a 2:1 input MUX optimized to provide two identical output

More information

Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC CLK2 VDD CLK0 SOT23-6L

Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC CLK2 VDD CLK0 SOT23-6L FEATURES 3 LVCMOS Outputs 12mA Output Drive Strength Input/Output Frequency: o Reference Clock: 1MHz to 150MHz Supports LVCMOS or Sine Wave Input Clock Very Low Jitter and Phase Noise Low Current Consumption

More information

440BX AGPset Spread Spectrum Frequency Synthesizer

440BX AGPset Spread Spectrum Frequency Synthesizer 440BX APset Spread Spectrum Frequency Synthesizer Features Maximized electromagnetic interference (EMI) suppression using Cypress s Spread Spectrum technology Single-chip system frequency synthesizer for

More information

PI74LPT V, 16-Bit Buffer/Line Driver. Features. Description. Block Diagram

PI74LPT V, 16-Bit Buffer/Line Driver. Features. Description. Block Diagram Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to 5V bus Advanced Low Power CMOS Operation

More information

ICS663 PLL BUILDING BLOCK

ICS663 PLL BUILDING BLOCK Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO)

More information

PI6C V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Diagram

PI6C V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Diagram Features Pin-to-pin compatible to ICS8533-01 Maximum operation frequency: 800MHz 4 pair of differential LVPECL outputs Selectable differential CLK and PCLK inputs CLK, n CLK pair accepts LVDS, LVPECL,

More information

PCKV MHz differential 1:10 clock driver

PCKV MHz differential 1:10 clock driver INTEGRATED CIRCUITS Supersedes data of 2001 Dec 03 2002 Sep 13 FEATURES ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. Latch-up testing is

More information

Single, 3 V, CMOS, LVDS Differential Line Receiver ADN4662

Single, 3 V, CMOS, LVDS Differential Line Receiver ADN4662 Data Sheet FEATURES ±15 kv ESD protection on input pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 2.5 ns maximum propagation delay 3.3 V power supply High impedance outputs

More information

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency

More information

74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs

74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs September 1991 Revised November 1999 74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs General Description The ABT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs

More information

ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET

ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET DATASHEET ICS722 Description The ICS722 is a low cost, low-jitter, high-performance 3.3 volt designed to replace expensive discrete s modules. The on-chip Voltage Controlled Crystal Oscillator accepts

More information

CLK_EN CLK_SEL. Q3 THIN QFN-EP** (4mm x 4mm) Maxim Integrated Products 1

CLK_EN CLK_SEL. Q3 THIN QFN-EP** (4mm x 4mm) Maxim Integrated Products 1 19-2575; Rev 0; 10/02 One-to-Four LVCMOS-to-LVPECL General Description The low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS inputs to four differential LVPECL outputs.

More information

3.3 VOLT COMMUNICATIONS CLOCK PLL MK Description. Features. Block Diagram DATASHEET

3.3 VOLT COMMUNICATIONS CLOCK PLL MK Description. Features. Block Diagram DATASHEET DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-45 Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO

More information

3.3V Zero Delay Buffer

3.3V Zero Delay Buffer 3.3V Zero Delay Buffer Features Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations see Available Configurations table Multiple low-skew outputs 10-MHz

More information

3.3V LVPECL 1:4. Features. Description. Block Diagram AK8181D

3.3V LVPECL 1:4. Features. Description. Block Diagram AK8181D Preliminary 3.3V LVPECL 1:4 Clock Fanout Buffer AK8181D Features Four differential 3.3V LVPECL outputs Selectable differential PCLK0p/n or LVPECL clock inputs PCLK0p/n pair can accept the following differential

More information

MK3722 VCXO PLUS AUDIO CLOCK FOR STB. Description. Features. Block Diagram DATASHEET

MK3722 VCXO PLUS AUDIO CLOCK FOR STB. Description. Features. Block Diagram DATASHEET DATASHEET MK3722 Description The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage

More information

UNISONIC TECHNOLOGIES CO., LTD CD4069

UNISONIC TECHNOLOGIES CO., LTD CD4069 UNISONIC TECHNOLOGIES CO., LTD CD4069 INVERTER CIRCUITS DESCRIPTION The UTC CD4069 consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating

More information

PI6C49X0204A. Low Skew 1 TO 4 Clock Buffer. Features. Description. Block Diagram. Pin Assignment

PI6C49X0204A. Low Skew 1 TO 4 Clock Buffer. Features. Description. Block Diagram. Pin Assignment Features ÎÎLow skew outputs (250 ps) ÎÎPackaged in 8-pin SOIC ÎÎLow power CMOS technology ÎÎOperating Voltages of 1.5 V to 3.3 V ÎÎOutput Enable pin tri-states outputs ÎÎ3.6 V tolerant input clock ÎÎIndustrial

More information

PI3USB10LP-A. USB 2.0 High-Speed (480 Mbps) Signal Switch Targeted for Battery Powered Applications. Description. Features.

PI3USB10LP-A. USB 2.0 High-Speed (480 Mbps) Signal Switch Targeted for Battery Powered Applications. Description. Features. Features USB 2.0 compliant (high speed and full speed) R ON is 5.5Ω typical @ V CC = 3.0V Low bit-to-bit skew Low Crosstalk: 40dB @ 500 Mbps Off Isolation: 35dB @ 500 Mbps Near-Zero propagation delay:

More information

PCKV MHz differential 1:10 clock driver

PCKV MHz differential 1:10 clock driver INTEGRATED CIRCUITS Supersedes data of 2001 Mar 16 File under Intergrated Circuits ICL03 2001 Jun 12 FEATURES ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM

More information

DS Tap High Speed Silicon Delay Line

DS Tap High Speed Silicon Delay Line www.dalsemi.com FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances

More information

PI6C V Low Skew 1-to-4 LVTTL/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Configuration

PI6C V Low Skew 1-to-4 LVTTL/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Configuration Features Maximum operation frequency: 500 MHz 4 pair of differential LVPECL outputs Selectable CLK 0 and inputs CLK 0, accept LVCMOS, LVTTL input level Output Skew: 80ps (maximum) Part-to-part skew: 50ps

More information

ICS83056I-01. General Description. Features. Block Diagram. Pin Assignment 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01

ICS83056I-01. General Description. Features. Block Diagram. Pin Assignment 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01 ICS83056I-01 General Description The ICS83056I-01 is a 6-bit, :1, Single-ended ICS LVCMOS Multiplexer and a member of the HiPerClockS HiPerClockS family of High Performance Clock Solutions from IDT. The

More information

P1P Portable Gaming Audio/Video Multimedia. MARKING DIAGRAM. Features

P1P Portable Gaming Audio/Video Multimedia.  MARKING DIAGRAM. Features .8V, 4-PLL Low Power Clock Generator with Spread Spectrum Functional Description The PP4067 is a high precision frequency synthesizer designed to operate with a 27 MHz fundamental mode crystal. Device

More information

YT0 YT1 YC1 YT2 YC2 YT3 YC3 FBOUTT FBOUTC

YT0 YT1 YC1 YT2 YC2 YT3 YC3 FBOUTT FBOUTC Differential Clock Buffer/Driver Features Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications 1:5 differential outputs External feedback pins (, ) are used to

More information

74LVT LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs

74LVT LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs 74LVT16374 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description The LVT16374 and LVTH16374 contain sixteen non-inverting D-type flip-flops with 3-STATE outputs and is

More information

CD4069, CD4069-SMD Inverter Circuits

CD4069, CD4069-SMD Inverter Circuits CD4069, CD4069-SMD Inverter Circuits General Description The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range,

More information

PI6C High Performance LVPECL Fanout Buffer. Features. Description. Applications. Pin Configuration (20-Pin TSSOP) Block Diagram

PI6C High Performance LVPECL Fanout Buffer. Features. Description. Applications. Pin Configuration (20-Pin TSSOP) Block Diagram Features ÎÎ4 LVPECL outputs ÎÎUp to 1.5GHz output frequency ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range) ÎÎTwo selectable inputs ÎÎLow delay

More information

16-Channel Constant Current LED Driver

16-Channel Constant Current LED Driver 16-Channel Constant Current LED Driver FEATURES 16 Constant current-sink channels Serial interface up to 25MHz clock frequency 3V to 5.5V logic supply LED current range from 2mA to 100mA LED current set

More information

PI6C V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux /Q4 /Q5 /Q6 /Q3

PI6C V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux /Q4 /Q5 /Q6 /Q3 LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features ÎÎF MAX < 1.5GHz ÎÎ10 pairs of differential LVPECL outputs ÎÎLow additive jitter, < 0.03ps (typ) ÎÎSelectable differential input pairs

More information

CD4069UBC Inverter Circuits

CD4069UBC Inverter Circuits CD4069UBC Inverter Circuits General Description The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power

More information

1:4 Clock Fanout Buffer

1:4 Clock Fanout Buffer 1:4 Clock Fanout Buffer Features Low-voltage operation V DD = 3.3V 1:4 Fanout Single-input configurable for LVDS, LVPECL, or LVTTL Four differential pairs of LVDS outputs Drives - or 100-ohm load (selectable)

More information

74ABT Bit Transceiver with 3-STATE Outputs

74ABT Bit Transceiver with 3-STATE Outputs 74ABT16245 16-Bit Traceiver with 3-STATE Outputs General Description The ABT16245 contai sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applicatio. The

More information

3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574. Features. Description. Block Diagram DATASHEET

3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574. Features. Description. Block Diagram DATASHEET DATASHEET 3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574 Description The MK1574 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 khz clock input as a reference, and generates many

More information

AV9108. CPU Frequency Generator. Integrated Circuit Systems, Inc. General Description. Features. Block Diagram

AV9108. CPU Frequency Generator. Integrated Circuit Systems, Inc. General Description. Features. Block Diagram Integrated Circuit Systems, Inc. AV98 CPU Frequency Generator General Description The AV98 offers a tiny footprint solution for generating two simultaneous clocks. One clock, the REFCLK, is a fixed output

More information

CLK1 GND. Phase Detector F VCO = F REF * (2 * M/R) VCO. P-Counter (14-bit) F OUT = F VCO / (2 * P) Programming Logic

CLK1 GND. Phase Detector F VCO = F REF * (2 * M/R) VCO. P-Counter (14-bit) F OUT = F VCO / (2 * P) Programming Logic PL611s-19 PL611s-19 FEATURES Designed for Very Low-Power applications Input Frequency, AC Coupled: o Reference Input: 1MHz to 125MHz o Accepts >0.1V input signal voltage Output Frequency up to 125MHz LVCMOS

More information

3-Channel Fun LED Driver

3-Channel Fun LED Driver 3-Channel Fun LED Driver Description is a 3-channel fun LED driver which features two-dimensional auto breathing mode. It has One Shot Programming mode and PWM Control mode for RGB lighting effects. The

More information

74LCX374 OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

74LCX374 OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: f MAX = 150 MHz (MIN.) at V CC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS

More information

Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator 87016 DATASHEET GENERAL DESCRIPTION The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has 4 banks of 4 outputs and each bank can be independently

More information

System Clock Chip for ATI RS400 P4 TM -based Systems

System Clock Chip for ATI RS400 P4 TM -based Systems System Clock Chip for ATI RS400 P4 TM -based Systems Recommended Application: ATI RS400 systems using Intel P4 TM processors Output Features: 6 - Pairs of SRC/PCI-Express clocks 2 - Pairs of ATIG (SRC/PCI

More information

Description. Applications. ÎÎNetworking systems ÎÎEmbedded systems ÎÎOther systems

Description. Applications. ÎÎNetworking systems ÎÎEmbedded systems ÎÎOther systems Features ÎÎ3.3V ±10% supply voltage ÎÎ25MHz XTAL or reference clock input ÎÎFive PCIe 2.0 Compliant 100MHz selectable HCSL outputs with -0.5% spread default is spread off ÎÎTwo 25MHz LVCMOS output ÎÎIndustrial

More information

MM74HC86 Quad 2-Input Exclusive OR Gate

MM74HC86 Quad 2-Input Exclusive OR Gate MM74HC86 Quad 2-Input Exclusive OR Gate Features Typical Propagation Delay: 9ns Wide Operating oltage Range: 2 6 Low Input Current: 1mA Maximum Low Quiescent Current: 20mA Max. (74 Series) Output Drive

More information

Frequency Generator and Integrated Buffer for PENTIUM

Frequency Generator and Integrated Buffer for PENTIUM Integrated Circuit Systems, Inc. ICS9159C-14 Frequency Generator and Integrated Buffer for PENTIUM General Description The ICS9159C-14 generates all clocks required for high speed RISC or CISC microprocessor

More information

Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408) Flexible Ultra-Low Jitter Clock Synthesizer Clockworks FLEX General Description The SM802xxx series is a member of the ClockWorks family of devices from Micrel and provide an extremely low-noise timing

More information

P4C1256L LOW POWER 32K X 8 STATIC CMOS RAM FEATURES DESCRIPTION V CC. Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100µA/100µA

P4C1256L LOW POWER 32K X 8 STATIC CMOS RAM FEATURES DESCRIPTION V CC. Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100µA/100µA FEATURES Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100µA/100µA Access Times 55/70/85 Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O

More information

3.3V Zero Delay Buffer

3.3V Zero Delay Buffer 3.3V Zero Delay Buffer Features Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations, see Available CY2308 Configurations on page 3 Multiple low skew

More information

The PL is an advanced Spread Spectrum clock generator (SSCG), and a member of PicoPLL Programmable Clock family.

The PL is an advanced Spread Spectrum clock generator (SSCG), and a member of PicoPLL Programmable Clock family. FEATURES Advanced programmable PLL with Spread Spectrum Reference Clock input o 1MHz to 200MHz Output Frequency o

More information

IDT Programmable Timing Control Hub TM for Next Gen P4 TM Processor ICS932S208 ICS932S208 DATASHEET. 56-pin SSOP & TSSOP

IDT Programmable Timing Control Hub TM for Next Gen P4 TM Processor ICS932S208 ICS932S208 DATASHEET. 56-pin SSOP & TSSOP Programmable Timing Control Hub TM for Next Gen P4 TM Processor Recommended Application: CK409B clock, Intel Yellow Cover part, Server Applications Output Features: 4-0.7V current-mode differential CPU

More information

PI6C :4 24MHz Clock Buffer. Description. Features. Applications. Block Diagram. Pin Configuration (16-Pin TSSOP) 16-pin (173 mil) TSSOP

PI6C :4 24MHz Clock Buffer. Description. Features. Applications. Block Diagram. Pin Configuration (16-Pin TSSOP) 16-pin (173 mil) TSSOP Features ÎÎSupport XTAL or Clock input at 24MHz ÎÎFour buffered outputs support V DDO operation ÎÎVery low phase jitter(rms) : < 1.5ps (max) ÎÎVery low additive jitter:

More information

Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) SINGLE 2-INPUT NAND GATE 5V TOLERANT INPUTS HIGH SPEED: t PD = 4.7ns (MAX.) at V CC =3V LOW POWER DISSIPATION: I CC =1µA (MAX.)atT A =25 C POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT

More information

HT82V Bit CCD/CIS Analog Signal Processor. Features. Applications. General Description. Block Diagram

HT82V Bit CCD/CIS Analog Signal Processor. Features. Applications. General Description. Block Diagram 6-Bit CCD/CIS Analog Signal Processor Features Operating voltage: 33V Low power consumption at 56mW Power-down mode: Under A (clock timing keep low) 6-bit 6 MSPS A/D converter Guaranteed no missing codes

More information

ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Functionality. 48-Pin SSOP

ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Functionality. 48-Pin SSOP ICS94802 Pentium/Pro TM System Clock Chip General Description Features Pin Configuration Block Diagram 48Pin SSOP Functionality Pentium is a trademark on Intel Corporation. 94802 Rev C /26/99 SEL CPUCLK,

More information

Note: ^ Deno tes 60K Ω Pull-up resisto r. Phase Detector F VCO = F REF * (M/R) F OUT = F VCO / P

Note: ^ Deno tes 60K Ω Pull-up resisto r. Phase Detector F VCO = F REF * (M/R) F OUT = F VCO / P FEATURES Advanced programmable PLL with Spread Spectrum Crystal or Reference Clock input o Fundamental crystal: 10MHz to 40MHz o Reference input: 1MHz to 200MHz Accepts 0.1V reference signal input voltage

More information

DEI1044, DEI1045 QUAD ARINC 429 LINE RECEIVER

DEI1044, DEI1045 QUAD ARINC 429 LINE RECEIVER Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1044, DEI1045 QUAD ARINC 429 LINE RECEIER Features: Converts

More information

Nuvoton SMBus GPIO Controller W83L603G W83L604G

Nuvoton SMBus GPIO Controller W83L603G W83L604G Nuvoton SMBus GPIO Controller W83L603G W83L604G Revision: 1.1 Date: July, 2008 W83L603G/W83L604G Datasheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 N.A. Aug./06 1.0 1.0 Initial

More information

CD4724BC 8-Bit Addressable Latch

CD4724BC 8-Bit Addressable Latch 8-Bit Addressable Latch General Description The CD4724BC is an 8-bit addressable latch with three address inputs (A0 A2), an active low enable input (E), active high clear input (C L ), a data input (D)

More information

StarChips. Technology. SCT2026 V02_01; Jan/08. In/Parallel Product Description. Features. Pin Configurations

StarChips. Technology. SCT2026 V02_01; Jan/08. In/Parallel Product Description. Features. Pin Configurations StarChips Technology V02_01; Jan/08 16-bit Serial-In/Pa In/Parallel rallel-out Constant-Current Current LED Driver Product Description The serial-interfaced LED driver sinks 16 LED clusters with constant

More information

PL High Speed Translator Buffer to LVDS FEATURES PIN CONFIGURATION

PL High Speed Translator Buffer to LVDS FEATURES PIN CONFIGURATION FEATURES Differential output Single AC coupled input (min. 100mV swing). Input range from 0 to 1.0GHz. 2.5V to 3.3V operation. Available in 8-Pin SOP or 3x3mm QFN GREEN/RoHS compliant packaging. PIN CONFIGURATION

More information

NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear

NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear General Description The NC7SZ175 is a single positive edge-triggered D-type CMOS Flip-Flop with Asynchronous Clear from Fairchild s Ultra High Speed

More information

IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH

IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH 3. CMOS 16-BIT TRANSPARENT LATCH 3. CMOS 16-BIT TRANSPARENT LATCH IDT74FCT163373A/C FEATURES: 0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps ESD > 200 per MIL-STD-883, Method 3015; > 20

More information

74ABT646 Octal Transceivers and Registers with 3-STATE Outputs

74ABT646 Octal Transceivers and Registers with 3-STATE Outputs April 1992 Revised November 1999 74ABT646 Octal Traceivers and Registers with 3-STATE Outputs General Description The ABT646 coists of bus traceiver circuits with 3- STATE, D-type flip-flops, and control

More information

One-PLL General Purpose Clock Generator

One-PLL General Purpose Clock Generator One-PLL General Purpose Clock Generator Features Integrated phase-locked loop Low skew, low jitter, high accuracy outputs Frequency Select Pin 3.3V Operation with 2.5 V Output Option 16-TSSOP Benefits

More information