DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9

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1 Integrated Circuit Systems, Inc. ICS93738 DDR and SDRAM Buffer Recommended Application: DDR & SDRAM fanout buffer, for VIA P4X/KT66/333 chipsets. Product Description/Features: Low skew, fanout buffer to differential clock distribution I C for functional and output control Feedback pin for input to output synchronization Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + DDR DIMMs Frequency supports up to 00MHz (DDR400) Supports Power Down Mode for power mananagement CMOS level control signal input Switching Characteristics: OUTPUT - OUTPUT skew: <00ps SDRAM OUTPUT - OUTPUT skew: <50ps DDR Output Rise and Fall Time for DDR outputs: 600ps - 950ps DUTY CYCLE: 47% - 53% DDR DUTY CYCLE: 45%- 55% SDRAM FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM DDRT_SDRAM DDRC_SDRAM3 DDRT_SDRAM4 DDRC_SDRAM5 BUF_ DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM0 DDRC5_SDRAM SDATA Pin Configuration ICS SEL_DDR* VDD.5 DDRT DDRC DDRT0 DDRC0 VDD.5 DDRT9 DDRC9 VDD.5 PD#* DDRT8 DDRC8 VDD.5 DDRT7 DDRC7 DDRT6 DDRC6 SCLK 48-Pin SSOP *Internal Pull-up Resistor of 0K to VDD Block Diagram Functionality BUF_ FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM DDRT_SDRAM DDRC_SDRAM3 MODE P 48 DDR Mode SEL_DDR= VDD 3.3_.5.5V P 4, 5, 6, 7, 0,, 5, 6, 9, 0,, These outputs will be DDR outputs SCLK SDATA SEL_DDR* PD# Control Logic DDRT_SDRAM4 DDRC_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDR/SD Mode SEL_DDR=0 3.3V These outputs will be standard SDRAM outputs DDRT5_SDRAM0 DDRC5_SDRAM DDRT(:6) DDRC (:6)

2 Pin Descriptions P NUMBER P NAME TYPE DESCRIPTION FB_OUT, 8,, 7, 3, VDD3.3_. 5 3, 9, 4, 8, 6, 3, 35, 40, 46 45, 43, 39, 34, 30, 8, 44, 4, 38, 33, 9, 7,, 9, 5, 0, 6, 4 OUT PWR PWR Feedback output, dedicated for external feedback.5v or 3.3V voltage supply to pins 4, 5, 6, 7, 0,, 5, 6, 9, 0,, Ground D DRT ( :6) O UT "True" Clock of differential pair outputs. DDRC (:6) DDRT (5:0) SDRAM (0, 8, 6, 4,, 0) DDRC (5:0), 0, 6,, 7, 5 SDRAM (, 9, 7, 5, 3,,) 3 BUF_ O UT "Complementory" clocks of differential pair outputs. OUT OUT "True" Clock of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input " Complementory" clocks of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input Single ended buffer input 4 SDAT A 5 SCLK 3, 37, 4, 47 VDD PD# 48 SEL_DDR I/ O PWR Data pin for I C circuitry 5V tolerant Clock input of I C input, 5V tolerant input.5v voltage supply Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled. The latency of the power down will not be greater than 3ms. Select input for DDR mode or DDR/SD mode 0=DDR/SD mode =DDR mode

3 Byte 6: Output Control (= enable, 0 = disable) B IT P# PWD DESCRIPTION 7 48 SEL_DDR (Read back only) 6 - (Reserved) 5 - (Reserved) 4 - (Reserved) 3 45, 44 DDRT, DDRC 43, 4 DDRT0, DDRC0 39, 38 DDRT9, DDRC9 0 34, 33 DDRT8, DDRC8 Byte 7: Output Control (= enable, 0 = disable) B IT P# PWD DESCRIPTION 7 30, 9 DDRT7, DDRC7 6 8, 7 DDRT6, DDRC6 5, DDRT5, SDRAM0 DDRC5_SDRAM 4 9, 0 DDRT4_SDRAM8 DDRC4_SDRAM9 3 5, 6 DDRT3_SDRAM6 DDRC3_SDRAM7 0, DDRT_SDRAM4 DDRC_SDRAM5 6, 7 DDRT_SDRAM DDRC_SDRAM3 0 4, 5 DDRT0_SDRAM DDRC0_SDRAM0 3

4 Absolute Maximum Ratings Supply Voltage (VDD & VDD.5) V to 3.6V Logic Inputs V to V DD +0.5 V Ambient Operating Temperature C to +85 C Case Temperature C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input / Supply / Common Output Parameters - SDRAM SEL_DDR=0, SDRAM Outputs, V DD3.3_.5 = 3.3V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Input High Current I IH V = V DD or 0 µa Input Low Current I IL V = V DD or -00 µa I DD3.3_.5 C L = 0 pf at 33 MHz ma Operating Supply Current I DD.5 C L = 0 pf at 33 MHz ma I DDPD C L = 0 pf 0 0 µa Output High Current I OH V DD = 3.3V, V OUT = V -8 ma Output Low Current I OL V DD = 3.3V, V OUT =.V 6 ma High-level Output Voltage V OH V DD = 3.3V, IOH = -ma V Low-level Output Voltage V OL V DD = 3.3V, IOL = ma 0.4 V Input Capacitance C V = V DD or pf. Guaranteed by design, not 00% tested in production. Recommended Operating Conditions - SDRAM SEL_DDR=0, SDRAM Outputs, V DD3.3_.5 = 3.3V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Power Supply Voltage V DD3.3_ V DD V Input High Voltage V IH SEL_DDR, PD# inputs V Input Low Voltage V IL SEL_DDR, PD# inputs 0.8 V Input Voltage Level V V 4

5 Electrical Characteristics - Input / Supply / Common Output Parameters - DDR SEL_DDR=, DDR/DDR_SDRAM Outputs, V DD3.3_.5 =.5V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Input High Current I IH V = V DD or 0 µa Input Low Current I IL V = V DD or -00 µa I DD3.3_.5 C L = 0 pf at 33 MHz 5 00 ma Operating Supply Current I DD.5 C L = 0 pf at 33 MHz ma I DDPD C L = 0 pf 0 0 µa Output High Current I OH V DD =.5V, V OUT = V -8 ma Output High Current I OL V DD =.5V, V OUT =.V 6 ma High-level Output Voltage V OH V DD =.5V, IOH = -ma.7 V Low-level Output Voltage V OL V DD =.5V, IOL = ma 0.46 V Output differential-pair V crossing voltage C DD / V DD / + 0. Input Capacitance C V = V DD or pf. Guaranteed by design, not 00% tested in production. V Recommended Operating Conditions - DDR SEL_DDR=, DDR/DDR_SDRAM Outputs, V DD3.3_.5 =.5V, T A = 0-85 o C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Power Supply Voltage V DD3.3_ V DD V Input High Voltage V IH SEL_DDR, PD# inputs V Input Low Voltage V IL SEL_DDR, PD# inputs 0.8 V Input Voltage Level V V 5

6 Switching Characteristics T A = 0-85 o C PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Operating Frequency MHz Input clock duty cycle d tin % Output to output Skew (DDR outputs) Output to output Skew (SDRAM outputs) T skewddr T skewsd V T = 50%, Not including FB_OUT to outputs V T =.5V ps ps Duty Cycle,3 V T = 50%, 66 MHz to 00 MHz, w/loads DC DDR (DDR outputs) V T = 50%, 0 MHz to 67 MHz, w/loads % Duty Cycle,3 (SDRAM outputs) DC SD V T =.5V, w/loads % Rise Time, Fall Time (DDR Single-ended 0-80 % t rd, t fd outputs) 33 MHz, Load = 0Ω / pf Rise Time, Fall Time Single-ended V OL = 0.4V, V OH =.4V t rs, t fs (SDRAM outputs) 33 MHz, Load = pf ps ns SDRAM Buffer LH Propagation Delay, t PLH Input edge greater than V/ns. Guaranteed by design, not 00% tested in production.. Refers to transistion on non-inverting output. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t / t, where the cycle time (t) decreases as the frequency increases. Switching Waveforms Duty Cycle Timing.5 ns SDRAM Buffer HL Propagation Delay, t PHL Input edge greater than V/ns.9.5 ns t t.5v.5v.5v SDRAM Buffer LH and HL Propagation Delay PUT.5V.5V OUTPUT.5V.5V t 6 t 7 6

7 . The ICS clock generator is a slave/receiver, I C component. It can read back the data stored in the l