ICS Frequency Generator & Integrated Buffers. Integrated Circuit Systems, Inc. Pin Configuration. 48-Pin SSOP. Block Diagram.

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1 Integrated Circuit Systems, Inc. ICS Frequency Generator & Integrated Buffers Recommended Application: SIS 530/620 style chipset Output Features: V/3.3V up to 33.3 MHz V (including free-running) V up to 33.3MHz V, 4.38MHz - 24/4.3 MHz selectable output for SIO - Fixed clock at 48MHz (3.3V) - 2.5V / 3.3V Features: Up to 33MHz frequency support Support power management: CPU, PCI, SDRAM stop and Power down Mode from I 2 C programming. Spread spectrum for EMI control ( ± 0.25% center spread & 0 to -0.5% down spread). Uses external 4.38MHz crystal FS pins for frequency select Key Specifications: CPU CPU<75ps SDRAM SDRAM < 350ps CPU SDRAM < 500ps CPU(early) PCI : -4ns (typ. 2ns) PCI PCI <500ps VDDR/X *MODE/REF0 GNDREF X X2 VDDPCI *FS/PCICLK_F *FS2.PCICLK0 GNDPCI PCICLK PCICLK2 PCICLK3 PCICLK4 VDDPCI SDRAM2 GNDSDR *CPU_STOP# /SDRAM *PCI_STOP# /SDRAM0 VDDSD/C *SDRAM_STOP# /SDRAM9 *PD# /SDRAM8 GNDFIX SDATA SCLK Pin Configuration ICS Pin SSOP * Internal Pull-up Resistor of 20K to 3.3V on indicated inputs VDDLAPIC IOAPIC REF/SD_SEL#* GNDLAPIC REF2/CPU2.5_3.3#* CPUCLK VDDLCPU CPUCLK2 CPUCLK3 GNDCPU SDRAM0 SDRAM VDDSDR SDRAM2 SDRAM3 GNDSDR SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GNDSDR 48MHz/FS0* SIO/SEL24_4#MHz* Block Diagram Functionality PLL2 48MHz SD_SEL FS2 FS FS0 CPU MHZ SDRAM MHZ PCI MHZ SEL24_4# X X2 MODE FS(2:0) CPU3.3#_2.5 SD_SEL# SDRAM_STOP# CPU_STOP# PCI_STOP# PD# SDATA SCLK 3 XTAL OSC PLL Spread Spectrum POR LATCH Control Logic Config. Reg. 5 /2 PCI CLOCK DIVDER CPU_STOP PCI_STOP STOP STOP SIO REF(2:0) 3 IOAPIC CPUCLK (3:) 3 SDRAM (2:0) 3 PCICLK (4:0) 5 PCICLK_F Note: REF, IOAPIC = 4.38MHz Rev B /6/00 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

2 ICS Pin Descriptions Pin number Pin name Type Description VDDR/X Power Isolated 3.3 V power for crystal & reference 2,2 REF0 Output 3.3V, 4.38 MHz reference clock output. Mode Input Function select pin, =desk top mode, 0=mobile mode. Latched input. 3,9,6,22, 27,33,39 GND Power 3.3 V Ground 4 X Input 4.38 MHz crystal input 5 X2 Output 4.38 MHz crystal output 6,4 VDDPCI Power 3.3 V power for the PCI clock outputs 7,2 8,2 FS PCICLK 0 Input Output Logic input frequency select bit. Input latched at power-on. 3.3 V PCI clock outputs, generating timing requirements for Pentium II PCICLK_F FS2 Output Input 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP# Logic input frequency select bit. Input latched at power-on. 3, 2,, 0 PCICLK (4:) Output 3.3 V PCI clock outputs, generating timing requirements for Pentium II 5,28,29,3,32, SDRAM 2, 34,35,37,38 SDRAM (7:0) Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input. SDRAM Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input. 7 CPU_STOP# Input Asynchronous active low input pin used to stop the CPUCLK in low state, all other clocks will continue to run. The CPUCLK will have a "Turnon" latency of at least 3 CPU clocks. SDRAM 0 Output SDRAM clock outputs. Frequency is selected by SD-SEL latched input. 8 Synchronous active low input used to stop the PCICLK in a low state. It will not PCI-STOP# Input effect PCICLK_F or any other outputs. 9 VDDSD/C Power 3.3 V power for SDRAM outputs and core SDRAM 9 Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input. 20 Asynchronous active low input used to stop the SDRAM in a low state. SDRAM_STOP# Input It will not effect any other outputs. SDRAM 8 Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input. 2 Asynchronous active low input pin used to power down the device into a low PD# Input power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SDATA Input Data input for I 2 C serial input. 24 SCLK Input Clock input of I 2 C input SEL24_4# Input This input pin controls the frequency of the SIO. If logic 0 at power on SIO=4.38 MHz. If logic at power-on SIO=24MHz. SIO Output Super I/O output. 24 or 4.38 MHz. Selectable at power-up by SEL24_4MHz 25,2 FS0 Input Logic input frequency select bit. Input latched at power-on. 26,2 3.3 V 48 MHz clock output, fixed frequency clock typically used with 48 MHz Output USB devices 30,36 VDDSDR Power 3.3 V power for SDRAM outputs 40,4,43 CPUCLK (3:) 0utput 2.5 V CPU and Host clock outputs 42 VDDLCPU Power 2.5 V power for CPU REF2 Output 3.3V, 4.38 MHz reference clock output. 44,2 This pin selects the operating voltage for the CPU. If logic 0 at power on CPU3.3#_2.5 Input CPU=3.3 V and if logic at power on CPU=2.5 V operating voltage. 45 GNDL Power 2.5 V Ground for the IOAPIC or CPU 46,2 REF Output 3.3V, 4.38 MHz reference clock output. SD_SEL# Input This input pin controls the frequency of the SDRAM. 47 IOAPIC Output 2.5V fixed 4.38 MHz IOAPIC clock outputs 48 VDDLAPIC Power 2.5 V power for IOAPIC : Internal Pull-up Resistor of 20K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 0Kohm resistor to program logic Hi to VDD or GND for logic low. 2

3 ICS General Description The ICS is the single chip clock solution for Desktop/Notebook designs using the SIS style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 2 C programming. Spread spectrum typically reduces system EMI by 8dB to 0dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I 2 C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(sd_sel=) or other clock frequencies (SD_SEL=0) Mode Pin - Power Management Input Control MODE, Pin 2 (Latched Input) 0 Power Management Functionality PD# CPU_STOP# PCI_STOP# SDRAM_STOP PCICLK (0:4) 0 X X X Pin 7 Pin 8 Pin 20 Pin 2 CPU_STOP# (INPUT) SDRAM (OUTPUT) PCI_STOP# (INPUT) SDRAM 0 (OUTPUT) SDRAM (0:2) SDRAM_STOP# (INPUT) SDRAM9 (OUTPUT) PCICLK_F CPUCLK PD# (INPUT) SDRAM8 (OUTPUT) Crystal OSC Running Running Running Running Running Running 0 Running Running Running Running Running 0 Running Running Running Running Running 0 0 Running Running Running Running 0 Running Running Running Running Running 0 0 Running Running Running Running 0 0 Running Running Running Running Running Running Running VCO CPU 3.3#_2.5V Buffer selector for CPUCLK drivers. CPU3.3#_2.5 Buffer Selected Input level for operation at: (Latched Data) 2.5V VDD 0 3.3V VDD 3

4 ICS Serial Configuration Command map Byte 0: Functionality and frequency select register (Default = 0) 7 (2, 6:4) 3 0 Description 0 - ±0.25% Center Spread Spectrum - 0 to -0.5% Down Spread Spectrum (2, 6:4) CPUCLK SDRAM PCICLK Frequency is selected by hardware select, latched inputs - Frequency is selected by 2, 6:4 0 - Normal - Spread spectrum enabled 0 - Running - Tristate all outputs PWD 0,00 Note 0 0 Note : Default at power-up will be for latched logic inputs to define frequency. I 2 C readback of the power up default indicates the revision ID code in bit 2, 6:4 as shown. 4

5 ICS Byte : CPU, Active/Inactive Register ( = enable, 0 = disable) B it Pin # PWD Description 7 - (Reserved) 6 - (Reserved) 5 - (Reserved) 4 - (Reserved) 3 40 CPUCLK3 2 4 CPUCLK2 43 CPUCLK 0 - X FS0#. Inactive means outputs are held LOW and are disabled from switching. Byte 2: PCI Active/Inactive Register ( = enable, 0 = disable) B it Pin # PWD Description 7 - X FS# 6 7 PCICLK_ F 5 - (Reserved) 4 3 PCICLK4 3 2 PCICLK3 2 PCICLK2 0 PCICLK 0 8 PCICLK0. Inactive means outputs are held LOW and are disabled from switching. Byte 3: SDRAM Active/Inactive Register ( = enable, 0 = disable) B it Pin # PWD Description 7 28 SDRAM SDRAM6 5 3 SDRAM SDRAM SDRAM SDRAM2 37 SDRAM 0 38 SDRAM0. Inactive means outputs are held LOW and are disabled from switching. Byte 4: SDRAM Active/Inactive Register ( = enable, 0 = disable) B it Pin # PWD Description 7 - (Reserved) /4MHz MHz 4 5 SDRAM2 3 7 SDRAM 2 8 SDRAM0 20 SDRAM9 0 2 SDRAM8. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Peripheral Active/Inactive Register ( = enable, 0 = disable) B it Pin # PWD Description 7 - (Reserved) 6 - X FS2# 5 - (Reserved) 4 47 IOAPIC 3 - X SD_SEL# 2 44 REF2 46 REF 0 2 REF0. Inactive means outputs are held LOW and are disabled from switching. 5

6 ICS Absolute Maximum Ratings Supply Voltage V Logic Inputs GND 0.5 V to V DD +0.5 V Ambient Operating Temperature C to +70 C Storage Temperature C to +50 C Case Temperature C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0-70C; Supply Voltage V DD = V DDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2 V DD +0.3 V Input Voltage V IL V SS V Input High Current I IH V IN = V DD 5 µa Input Current I IL V IN = 0V; Inputs with no pull-up resistors -5 µa Input Current I IL2 V IN = 0V; Inputs with pull-up resistors -200 µa Operating Supply I DD3.3OP66 C L = 0 pf; 66 MHz ma Current I DD3.3OP00 C L = 0 pf; 00 MHz ma Powerdown Current I DD3.3PD C L = 0 pf; Input address to VDD or GND µa Input Frequency F i V DD = 3.3 V MHz Input Capacitance C IN Logic Inputs 5 pf C INX X & X2 pins pf Transition time T trans To st crossing of target frequency 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target frequency 3 ms T CPU00SDRAM00 V T =.5V ps Skew T CPU-PCI V T =.5V ns Guaranteed by design, not 00% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0-70C; Supply Voltage VDD = 3.3 V +/- 5%, VDDL = 2.5V +/- 5% (unless otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply IDD2.5OP66 C L = 0 pf; 66 MHz ma Current IDD2.5OP00 C L = 0 pf; 00 MHz ma Skew TCPU00SDRAM00 VT =.5V; VTL =.25V ps TCPU-PCI VT =.5V; VTL =.25V ns Guaranteed by design, not 00% tested in production. 6

7 ICS Electrical Characteristics - CPUCLK T A = 0-70º C; V DD = V DDL = 3.3 V +/-5%; C L = 0-20 pf (unless otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH2B I OH = -2 ma V Output Voltage V OL2B I OL = 2 ma V Output High Current I OH2B V OH = 2 V -6-9 ma Output Current I OL2B V OL = 0.8 V 9 22 ma Rise Time t r2b V OL = 0.4 V, V OH = 2.4 V.45 2 ns Fall Time t f2b V OH = 2.4 V, V OL = 0.4 V ns Duty Cycle d t2b V T =.5 V % Skew t sk2b V T =.5 V ps Jitter, Cycle-to-cycle t jcyc-cyc2b V T =.5 CPU & SDRAM = 00 MHz ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - CPUCLK T A = 0-70º C; V DD = 3.3 V +/-5%, V DDL = 2.5V +/- 5 %; C L = 0-20 pf (unless otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH2B I OH = -2 ma V Output Voltage V OL2B I OL = 2 ma V Output High Current I OH2B V OH =.7 V -5-9 ma Output Current I OL2B V OL = 0.7 V 9 23 ma Rise Time t r2b V OL = 0.4 V, V OH = 2.0 V.4.6 ns Fall Time t f2b V OH = 2.0 V, V OL = 0.4 V.2.6 ns Duty Cycle d t2b V T =.25 V % Skew t sk2b V T =.25 V ps V Jitter, Cycle-to-cycle t T =.25 CPU & jcyc-cyc2b SDRAM = 00 MHz ps Guaranteed by design, not 00% tested in production. 7

8 ICS Electrical Characteristics - PCICLK T A = 0-70º C; V DD = 3.3 V +/- 5%, V DDL = 2.5 V +/- 5 %; C L = 30 pf (unless otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH I OH = - ma V Output Voltage V OL I OL = 9.4 ma V Output High Current I OH V OH = 2.0 V ma Output Current I OL V OL = 0.8 V 6 24 ma Rise Time t r V OL = 0.4 V, V OH = 2.4 V.8 2 ns Fall Time t f V OH = 2.4V, V OL = 0.4 V.7 2 ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V ps Jitter, Cycle-to-cycle t jcyc-cyc V T =.5 V ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - SDRAM T A = 0-70º C; V DD = 3.3 V +/- 5%, V DDL = 2.5 V +/- 5 %; C L = 30 pf (unless otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH I OH = - ma V Output Voltage V OL I OL = 9.4 ma V Output High Current I OH V OH = 2.0 V ma Output Current I OL V OL = 0.8 V 6 24 ma Rise Time t r V OL = 0.4 V, V OH = 2.4 V.6 2 ns Fall Time t f V OH = 2.4V, V OL = 0.4 V.6 2 ns d t V T =.5 V; divide by 2 selects < 24 MHz % Duty Cycle d t2 V T =.5 V; divide by 3 selects % d t3 V T =.5 V; selects >= 24 MHz % t sk V T =.5 V; SDRAM 8, 9, & ps Skew t sk2 V T =.5 V; all except SDRAM 8, 9, & ps t sk3 V T =.5 V; all SDRAMs ps Jitter, Cycle-to-cycle t jcyc-cyc V T =.5 V ps Guaranteed by design, not 00% tested in production. 8

9 ICS Electrical Characteristics - REF/48MHz/SIO T A = 0-70º C; V DD = 3.3 V +/- 5%, V DDL = 2.5 V +/- 5 %; C L = 20 pf (unless otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High V Voltage OH5 I OH = -2 ma V Output Voltage V OL5 I OL = 0 ma V Output High Current I OH5 V OH = 2.0 V ma Output Current I OL5 V OL = 0.8 V 6 24 ma Rise Time t r5 V OL = 0.4 V, V OH = 2.4 V 2. 4 ns Fall Time t f5 V OH = 2.4V, V OL = 0.4 V 2. 4 ns Duty Cycle d t5 V T =.5 V % Jitter, Cycle-to- Cycle, REF t jcyc-cyc, REF V T =.5 V ps Jitter, Cycle-to- Cycle, fixed clock t jcyc-cyc, fixed V T =.5 V ps Guaranteed by design, not 00% tested in production. 9

10 ICS General I 2 C serial interface information The information in this section assumes familiarity with I 2 C programming. For more information, contact ICS for an I 2 C programming application note. How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Controller (Host) Start Address D2 (H) Dummy Command Code Dummy Byte Count Byte 0 Byte Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Stop How to Write: ICS (Slave/Receiver) Controller (Host) Start Address D3 (H). The ICS clock generator is a slave/receiver, I 2 C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 00K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. Stop How to Read: ICS (Slave/Receiver) Byte Count Byte 0 Byte Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 0

11 ICS CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 00 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS All other clocks continue to run undisturbed. (including SDRAM outputs).

12 ICS SDRAM_STOP# Timing Diagram SDRAM_STOP# is an sychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. SDRAM_STOP# is synchronized by the ICS All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.. All timing is referenced to the internal CPU clock. 2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the SDRAM clocks inside the ICS All other clocks continue to run undisturbed. 2

13 ICS PCI_STOP# Timing Diagram PCI_STOP# is an synchronous input to the ICS It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse) is at least 0 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 3

14 ICS Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic 0) voltage potential. A 0 Kilohm (0K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 4

15 ICS General Layout Precautions: ) Use a ground plane on the top layer of the PCB in all areas not used by traces. VDD Ferrite Bead C2 22µF/20V Tantalum C2 22µF/20V Tantalum Ferrite Bead VDD 2) Make all power traces and ground traces as wide as the via pad for lower inductance C ) All clock outputs should have a series terminating resistor, and a 20pF capacitor to ground between the resistor and clock pin. Not shown in all places to improve readibility of diagram. C C 3.3V Power Route C4 C3 2.5V Power Route Clock Load 2) Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed Ground Connections to VDD: V Power Route = Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load 5

16 ICS SYMBOL In Millimeters COMMON DIMENSIONS In Inches COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e BASIC BASIC h L N SEE VARIATIONS SEE VARIATIONS α VARIATIONS D mm. D (inch) N MIN MAX MIN MAX JEDEC MO-8 DOC# //00 REV B Ordering Information ICS9248yF-28 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 6 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.