ICS9112A-16. Low Skew Output Buffer. General Description. Pin Configuration. Block Diagram. 8 pin SOIC, TSSOP
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1 Low Skew Output Buffer General Description The ICS92A-6 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to MHz. ICS92A-6 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 50 ps, the part acts as a zero delay buffer. Features Zero input - output delay Frequency range 25 - MHz (.V) High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 Jitter between outputs Skew controlled outputs Skew less than 250 between outputs Available in 8 pin 50 mil SOIC or 7 mil TSSOP package..v ±0% operation The ICS92A-6 comes in an eight pin 50 mil SOIC or 7 mil TSSOP package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. Block Diagram Pin Configuration 8 pin SOIC, TSSOP
2 Pin Descriptions PI UMBER PI AME TYPE REF 2 I reference frequency. 2 CLK2 OUT CLK OUT 4 GD 5 LK 6 VDD 7 LK4 8 LKOUT PWR C OUT C OUT C OUT Buffered clock output Buffered clock output Ground Buffered clock output P WR Power Supply (.V) Buffered clock output otes:. Guaranteed by design and characterization. ot subject to 00% test. 2. Weak pull-down. Weak pull-down on all outputs DESCRIPTIO Buffered clock output. Internal feedback on this pin 2
3 Absolute Maximum Ratings Supply Voltage V Logic s GD 0.5 V to VDD +0.5 V Ambient Operating Temperature C to +70 C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at.v V DD =.0.6 V, T A = 0 70 C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CODITIOS MI TYP MAX UITS Low Voltage High Voltage V IL 0. 8 V V IH 2. 0 V Low Current High Current I IL I IH Output Low Voltage V OL Output High Voltage V OH Power Down Supply Current Supply Current IDD IDD VI = 0V µ A VI = VDD µ A I OL I OH = 25mA V = 25mA V REF = 0 MHz µ A Unloaded oututs at MHz SEL inputs at VDD or GD ma otes:. Guaranteed by design and characterization. ot subject to 00% test. 2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to.4v.. Duty cycle measured at.4v. 4. Skew measured at.4v on rising edges. Loading must be equal on outputs.
4 Switching Characteristics PARAMETER SYMBOL Output period t period t Duty Cycle Dt Duty Cycle Dt2 Rise Time tr Fall Time tf Rise Time tr Fall Time tf Delay, REF Rising Edge to CLKOUT, 2 R ising Edge Dr Output to Output Tskew Skew Device to Device Tdsk-Tdsk Skew Cycle to Cycle Tcyc-Tcyc Jitter PLL Lock Time tlock Jitter; Absolute Tjabs Jitter Jitter; - Sigma Tjs With CL=0pF With CL=0pF CODITIO MI (25) (25) TYP MAX 7.5 () 7.5 () UITS ns (MHz) ns (MHz) at.4v; CL=0pF % at VDD/2 Fout <66.6MHz CL=0pF CL=0pF CL=5pF CL=5pF between 0.8V and 2.0V: between 2.0V and 0.8V; between 0.8V and 2.0V: between 2.0V and 0.8V; %.2. 5 ns.2. 5 ns ns ns at.4v 0 ± 50 All outputs equally loaded, CL=20pF at VDD/2 on the CLKOUT pins of devices outputs at MHz, loaded Stable power supply, valid clock presented on REF 0,000 0,000 CL=0pF cycles cycles ms otes:. Guaranteed by design and characterization. ot subject to 00% test. 2. REF input has a threshold voltage of.4v. All parameters expected with loaded outputs 4
5 Output to Output Skew The skew between CLKOUT and the CLK(-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(-4) outputs are less loaded than CLKOUT, CLK(-4) outputs will lead it; and if the CLK(-4) is more loaded than CLKOUT, CLK(-4) will lag the CLKOUT. Since the CLKOUT and the CLK(-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. REF input and all outputs loaded Equally REF input and CLK(-4) outputs loaded equally, with CLKOUT loaded More. REF input and CLK(_4) outputs loaded equally, with CLKOUT loaded Less. Timing diagrams with different loading configurations 5
6 50 mil (arrow Body) SOIC IDEX AREA 2 D E H h x 45 A C L In Millimeters In Inches SYMBOL COMMO DIMESIOS COMMO DIMESIOS MI MAX MI MAX A A B C D E e.27 BASIC BASIC H h L a e B A SEATIG PLAE VARIATIOS D mm. D (inch) MI MAX MI MAX (.004) Reference Doc.: JEDEC Publication 95, MS mil (arrow Body) SOIC Ordering Information 92AM-6LFT Example: XXXX A M PPP LFT Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern umber (2 or digit number for parts with ROM code patterns) Package Type M = SOIC Revision Designator Device Type 6
7 IDEX AREA 2 D E E c L In Millimeters In Inches SYMBOL COMMO DIMESIOS COMMO DIMESIOS MI MAX MI MAX A A A b c D E 6.40 BASIC BASIC E e 0.65 BASIC BASIC L aaa A2 e -Cb A A SEATIG PLAE C aaa VARIATIOS D mm. D (inch) MI MAX MI MAX Reference Doc.: JEDEC Publication 95, MO mm. Body, 0.65 mm. pitch TSSOP (7 mil) ( Inch) Ordering Information 92AG-6LF-T Example: XXXX A G PPP LFT Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern umber (2 or digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator Device Type 7
8 Revision History Rev. Issue Date Description Page # H 9//2004 Updated Lead Free information 6-7 I /2/2004 Added L option 6-7 J 4/26/2007 Removed L option superceded by LF. 6-7 K 8//2007 Updated Switching Characteristics Rise/Fall time. 4 L 2/9/2008 Removed ICS prefix from ordering information
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Features High-speed, low-noise, non-inverting 1:4 buffer Maximum Frequency up to 200 MHz Low output skew < 100ps Low propagation delay < 3.5ns Optimized duty cycle 3.3 tolerent input 1.2 or 1.5 supply
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DATASHEET ICS501 Description The ICS501 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
NETWORKING CLOCK SYNTHESIZER. Features
DATASHEET ICS650-11 Description The ICS650-11 is a low cost, low jitter, high performance clock synthesizer customized for BroadCom. Using analog Phase-Locked Loop (PLL) techniques, the device accepts
Frequency Generator & Integrated Buffers for Celeron & PII/III TM *SEL24_48#/REF0 VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI
Integrated Circuit Systems, Inc. ICS9248-38 Frequency Generator & Integrated Buffers for Celeron & PII/III TM Recommended Application: 80/80E and Solano type chipset. Output Features: 2- CPUs @ 2.5V 9
MK AMD GEODE GX2 CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK1491-09 Description The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked
3.3 VOLT COMMUNICATIONS CLOCK PLL MK Description. Features. Block Diagram DATASHEET
DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-45 Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO
ICS DIMM Buffer. Integrated Circuit Systems, Inc. General Description. Block Diagram. Pin Configuration
Integrated Circuit Systems, Inc. ICS9179-12 3 DIMM Buffer General Description The ICS9179-12 is a buffer intended for reduced pin count 2 - chip Intel BX chipset designs An I 2 C interface is included,
MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK2705 Description The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal.
PI6C557-03B. PCIe 3.0 Clock Generator with 2 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TSSOP) Block Diagram
Features ÎÎPCIe 3.0 compliant à à PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V
MK2703 PLL AUDIO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET MK2703 Description The MK2703 is a low-cost, low-jitter, high-performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using IDT
ICS Frequency Generator & Integrated Buffers for PENTIUM/Pro TM. Integrated Circuit Systems, Inc. General Description.
Integrated Circuit Systems, Inc. ICS9248-39 Frequency Generator & Integrated Buffers for PENTIUM/Pro TM General Description The ICS9248-39 generates all clocks required for high speed RISC or CISC microprocessor
ICS AMD - K8 System Clock Chip. Integrated Circuit Systems, Inc. Pin Configuration ICS Recommended Application: AMD K8 Systems
Integrated Circuit Systems, Inc. ICS950401 AMD - K8 System Clock Chip Recommended Application: AMD K8 Systems Output Features: 2 - Differential pair push-pull CPU clocks @ 3.3V 7 - PCI (Including 1 free
PI6C B. 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Diagram
Features Maximum output frequency: 500MHz 4 pair of differential LPECL outputs Selectable and crystal inputs accepts LCMOS, LTTL input level Ultra low additive phase jitter: < 0.05 ps (typ) (differential
PT7C4511. PLL Clock Multiplier. Features. Description. Pin Configuration. Pin Description
Features Zero ppm multiplication error Input crystal frequency of 5-30 MHz Input clock frequency of - 50 MHz Output clock frequencies up to 200 MHz Peak to Peak Jitter less than 200ps over 200ns interval
PI6CX201A. 25MHz Jitter Attenuator. Features
Features PLL with quartz stabilized XO Optimized for MHz input/output frequency Other frequencies available Low phase jitter less than 30fs typical Free run mode ±100ppm Single ended input and outputs
3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574. Features. Description. Block Diagram DATASHEET
DATASHEET 3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574 Description The MK1574 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 khz clock input as a reference, and generates many
Addr FS2:0. Addr FS2:0
DATASHEET Description The MK1575-01 is a clock recovery Phase-Locked Loop (PLL) designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to accept a low-frequency
ICS9P935 ICS9P935. DDR I/DDR II Phase Lock Loop Zero Delay Buffer 28-SSOP/TSSOP DATASHEET. Description. Pin Configuration
DATASHEET ICS9P935 Description DDR I/DDR II Zero Delay Clock Buffer Output Features Low skew, low jitter PLL clock driver Max frequency supported = 400MHz (DDRII 800) I 2 C for functional and output control
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC DESCRIPTION
FEATURES 1:6 LVCMOS output fanout buffer for DC to 150MHz 8mA Output Drive Strength Low power consumption for portable applications Low input-output delay Output-Output skew less than 250ps Low Additive
MK3722 VCXO PLUS AUDIO CLOCK FOR STB. Description. Features. Block Diagram DATASHEET
DATASHEET MK3722 Description The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage