Frequency Generator with 200MHz Differential CPU Clocks MHz_USB MHz_DOT 3V66_5 3V66_3 3V66_(4,2) REF CPUCLKT (2:0) 3 CPUCLKC (2:0)

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1 Integrated Circuit Systems, Inc. ICS95080 Frequency Generator with 200MHz Differential CPU Clocks Recommended Application: CK-408 clock for BANIAS processor/ ODEM and MONTARA-G chipsets. Output Features: 3 0.7V Differential CPU Clock Pairs 7 PCI 33.3MHz 3 PCI_F 33.3MHz USB 48MHz DOT 48MHz REF 4.38MHz 5 3V MHz VCH/3V66 48MHz or 66.6MHz Features: Supports spread spectrum modulation, down spread 0 to -0.5%. (CPU, 3V66, PCI) Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. Key Specifications: CPU Output Jitter <50ps 3V66 Output Jitter <250ps CPU Output Skew <00ps Block Diagram X X2 PD# CPU_STOP# PCI_STOP# MULTSEL0 FS (2:0) SDATA SCLK PLL2 XTAL OSC PLL Spread Spectrum Control Logic Config. Reg. CPU DIVDER PCI DIVDER 3V66 DIVDER Stop Stop 3 48MHz_USB 48MHz_DOT 3V66_5 3V66_3 3V66_(4,2) REF CPUCLKT (2:0) 3 CPUCLKC (2:0) 7 3 PCICLK (6:0) PCICLK_F (2:0) 3V66_0 3V66_/VCH_CLK I REF Pin Configuration VDDREF 56 REF X 2 55 FS X FS0 GND 4 53 CPU_STOP#* PCICLK_F CPUCLKT0 PCICLK_F 6 5 CPUCLKC0 PCICLK_F VDDCPU VDDPCI 8 49 CPUCLKT GND 9 48 CPUCLKC PCICLK GND PCICLK 46 VDDCPU PCICLK CPUCLKT2 PCICLK CPUCLKC2 VDDPCI 4 43 MULTSEL0* GND 5 42 IREF PCICLK4 6 4 GND PCICLK FS2 PCICLK MHz_USB VDD3V MHz_DOT GND VDD48 3V66_ GND 3V66_ V66_/VCH_CLK 3V66_ PCI_STOP#* 3V66_ V66_0 *PD# VDD3V66 VDDA 26 3 GND GND SCLK Vtt_PWRGD# SDATA 56-Pin 300mil SSOP 6.0 mm. Body, 0.50 mm. pitch TSSOP * These inputs have 50K internal pull-up resistor to VDD. Functionality FS2 FS FS0 CPU (MHz) 3V66(5:0) (MHz) PCI_F PCI (MHz) X X X X Mid 0 0 Tristate Tristate Tristate Mid 0 TCLK/ 2 TCLK/ 4 TCLK/ 8 Mid 0 Mid ICS F 0/2/04

2 ICS95080 Pin Configuration PIN NUMBER PIN NAME VDDREF 2 X 3 X2 4 GND 5 PCICLK_F0 6 PCICLK_F 7 PCICLK_F2 8 VDDPCI 9 GND 0 PCICLK0 PCICLK 2 PCICLK2 3 PCICLK3 TYPE PWR Ref, XTAL power supply, nominal 3.3V I N Crystal input,nominally 4.38MHz. Crystal output, nominally 4.38MHz. Ground pin for 3V outputs. DESCRIPTION Free running PCI clock not affected by PCI_STOP#. Free running PCI clock not affected by PCI_STOP#. Free running PCI clock not affected by PCI_STOP#. PWR Power supply for PCICLK_F and PCICLK, nominal 3.3V Ground pin for 3V outputs. PCI clock outputs. PCI clock outputs. PCI clock outputs. PCI clock outputs. 4 VDDPCI PWR Power supply for PCICLK_F and PCICLK, nominal 3.3V 5 GND Ground pin for 3V outputs. 6 PCICLK4 PCI clock outputs. 7 PCICLK5 PCI clock outputs. 8 PCICLK6 PCI clock outputs. 9 VDD3V66 Power pin for the 3V66 clocks. 20 GND Ground pin for 3V outputs. 2 3V66_ 2 66MHz outputs at 3.3V. 22 3V66_ 3 66MHz outputs at 3.3V. 23 3V66_ 4 66MHz outputs at 3.3V. 24 3V66_ 5 66MHz input/output at 3.3V. 25 PD# 26 VDDA 27 GND IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V power for the PLL core. Ground pin for 3V outputs. 0472F 0/2/04 2

3 ICS95080 Pin Configuration (Continued) PIN NUMBER PIN NAME TYPE DESCRIPTION 28 Vtt_PWRGD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when FS[2:0] and MULTISEL0 inputs are valid and are ready to be sampled. (active low) 29 SDATA I/ O Data pin for I2C circuitry 5V tolerant 30 SCLK IN Clock pin of I2C circuitry 5V tolerant 3 GND Ground pin for 3V outputs. 32 VDD3V66 Power pin for the 3V66 clocks. 33 3V66_ 0 66MHz outputs at 3.3V. 34 PCI_STOP# IN Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low 35 3V66_/VCH_CLK Selectable 48MHz non-ssc or 66MHz SSC clock output 36 GND Ground pin for 3V outputs. 37 VDD48 Power for 48MHz output buffers and fixed PLL core MHz_DOT 48MHz output clock 39 48MHz_USB 48MHz output clock 40 FS2 I N Frequency select pin. 4 GND Ground pin for 3V outputs. 42 IREF 43 MULTSEL0 44 CPUCLKC2 45 CPUCLKT2 46 VDDCPU 47 GND 48 CPUCLKC 49 CPUCLKT 50 VDDCPU 5 CPUCLKC0 52 CPUCLKT0 53 CPU_STOP# 54 FS0 55 FS 56 REF IN PWR This pin festablishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selection the current multiplier for CPU outputs "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks,3.3v nominal Ground pin for 3V outputs. PWR "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks,3.3v nominal "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. I N This asynchronous input halts to active low level when driven low. I N Frequency select pin. I N Frequency select pin MHz reference clock. 0472F 0/2/04 3

4 ICS95080 Power Groups (Analog) VDDA = PLL VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR Truth Table (Digital) VDDPCI VDD3V66 VDDCPU FS2 FS FS0 CPU (MHz) 3V66 (5:0) (MHz) PCI_F PCI (MHz) REF0 (MHz) USB/DOT (MHz) X X X X Mid 0 0 Tristate Tristate Tristate Mid 0 TCLK/ 2 TCLK/ 4 TCLK/ 8 Mid 0 Mid Tristate Tristate TCLK TCLK/ 2 Maximum Allowed Current Condition Powerdown Mode (PWRDWN# = 0) Full Active Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 25mA 360mA Host Swing Select Functions MULTISEL0 Board Target Trace/Term Z Reference R, Iref = V D D /(3*Rr) Output Current Z ohms Rr = 475 %, Iref = 2.32mA Ioh = 6* I REF 50 NOTE: MULTSEL0 = 0 not supported in ICS Refer to ICS for Buffered Mode support. 0472F 0/2/04 4

5 ICS95080 Power Management PD# CPU_STOP# PCI_STOP# VCO CPU CPU# PCICLK 3v66 48MHz REF 0 X X STOP Iref*2 FLOAT LOW LOW LOW LOW RUN RUN RUN RUN RUN RUN RUN 0 RUN Iref*2 FLOAT RUN RUN RUN RUN 0 RUN RUN RUN LOW RUN RUN RUN RUN RUN RUN RUN RUN RUN RUN Note: PCI_F is not affected by PCI_STOP# and CPU_STOP# Tri-State Control of CPU Outputs State Byte0 bit6 Bytebit6 Pin Pin Stoppable Free-Running PD# Cpu_stop# PD# Cpu_Stop# CPU outputs CPU outputs Running Running Irefx6 Running Irefx2 Irefx Irefx2 Irefx2 4 0 Running Running Hi-Z Running Hi-Z Irefx Hi-Z Irefx2 8 0 Running Running Irefx6 Running Hi-Z Hi-Z Hi-Z Hi-Z 2 Running Running 3 0 Hi-Z Running 4 0 Hi-Z Hi-Z Hi-Z Hi-Z 0472F 0/2/04 5

6 ICS95080 Absolute Maximum Ratings Supply Voltage V Logic Inputs GND 0.5 V to V DD +0.5 V Ambient Operating Temperature C to +85 C Case Temperature C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0-70 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2 V DD +0.3 V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD -5 5 Input Low Current V I IN = 0 V; Inputs with no pull-up IL -5 resistors µa V I IN = 0 V; Inputs with pull-up IL2-200 resistors Operating Supply Current I DD3.3OP C L = Full load; 00 MHz ma I DD3.3OP C L =Full load; 33 MHz ma Powerdown Current I DD3.3PD IREF=2.32 ma ma Input Frequency F i V DD = 3.3 V 4.38 MHz Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C Output pin capacitance 6 pf C INX X & X2 pins pf Clk Stabilization,2 From PowerUp or deassertion of T STAB PowerDown to st clock..8 ms t PZH,t PZL Output enable delay (all outputs) 0 ns Delay t PHZ,t PLZ Output disable delay (all outputs) 0 ns Guaranteed by design, not 00% tested in production. 2 See timing diagrams for buffered and un-buffered timing requirements. 0472F 0/2/04 6

7 ICS95080 Electrical Characteristics - CPU (0.7V Select) T A = 0-70 C; VDD=3.3V +/-5%; C L = 0-20 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Source Output Impedance Zo V O = V x 3000 Ω Voltage High VHigh Statistical measurement on Voltage Low VLow single ended signal using mv Max Voltage Vovs Measurement on single ended Min Voltage Vuds signal using absolute value mv Crossing Voltage (abs) Vcross(abs) mv Crossing Voltage (var) d-vcross Variation of crossing over all edges mv Rise Time t r V OL = 0.75V, V OH = 0.525V ps Fall Time t f V OH = 0.525V V OL = 0.75V ps Rise Time Variation d-t r 0 25 ps Fall Time Variation d-t f 0 25 ps Measurement from differential Duty Cycle d t3 wavefrom % Skew t sk3 V T = 50% 6 00 ps Jitter, Cycle to cycle t jcyc-cyc V T = 50% ps Guaranteed by design, not 00% tested in production. 2 I OWT can be varied and is selectable thru the MULTSEL pin. Electrical Characteristics - PCICLK T A = 0-70 C; VDD=3.3V +/-5%; C L = 0-30 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP V O = V DD *(0.5) W Output High Voltage V OH I OH = - ma V Output Low Voltage V OL I OL = ma V Output High Current I OH V OH@MIN =.0 V V OH@MAX = 3.35 V ma Output Low Current I OL V =.95 V 30 0 V = 0.4 V ma Rise Time t r V OL = 0.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL = 0.4 V ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V ps Jitter,cycle to cyc t jcyc-cyc V T =.5 V ps Guaranteed by design, not 00% tested in production. 0472F 0/2/04 7

8 ICS95080 Electrical Characteristics - 3V66 Mode: 3V66 [5:0] T A = 0-70 C; VDD=3.3V +/-5%; C L = 0-30 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP V O = V DD *(0.5) Ω Output High Voltage V OH I OH = - ma V Output Low Voltage V OL I OL = ma V V OH@MIN =.0 V Output High Current I OH V OH@MAX = 3.35 V ma Output Low Current I OL V =.95 V 30 0 V = 0.4 V ma Rise Time t r V OL = 0.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL = 0.4 V ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V ps Jitter t jcyc-cyc V T =.5 V 3V ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB T A = 0-70 C; VDD=3.3V +/-5%; C L = 0-20 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP V O = V DD *(0.5) Ω Output High Voltage V OH I OH = - ma V Output Low Voltage V OL I OL = ma V V OH@MIN =.0 V Output High Current I OH V OH@MAX = 3.35 V ma V =.95 V 29 Output Low Current I OL V = 0.4 V 27 ma 48DOT Rise Time t r V OL = 0.4 V, V OH = 2.4 V ns 48DOT Fall Time t f V OH = 2.4 V, V OL = 0.4 V ns VCH 48 USB Rise Time t r V OL = 0.4 V, V OH = 2.4 V.37 2 ns VCH 48 USB Fall Time t f V OH = 2.4 V, V OL = 0.4 V.47 2 ns 48 DOT Duty Cycle d t V T =.5 V % VCH 48 USB Duty Cycle d t V T =.5 V % 48 DOT Jitter t jcyc-cyc V T =.5 V 350 ps 48 USB Jitter t jcyc-cyc V T =.5 V ps USB to DOT Skew t sk V T =.5 V (0 OR 80 degrees) ns VCH Jitter t jcyc-cyc V T =.5 V ps Guaranteed by design, not 00% tested in production. 0472F 0/2/04 8

9 ICS95080 Electrical Characteristics - REF T A = 0-70 C; VDD=3.3V +/-5%; C L = 0-20 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP V O = V DD *(0.5) Ω Output High Voltage V OH I OH = - ma V Output Low Voltage V OL I OL = ma V V OH@MIN =.0 V Output High Current I OH V OH@MAX = 3.35 V ma V =.95 V 30 0 Output Low Current I OL V = 0.4 V ma Rise Time t r V OL = 0.4 V, V OH = 2.4 V.69 2 ns Fall Time t f V OH = 2.4 V, V OL = 0.4 V.56 2 ns Duty Cycle d t V T =.5 V % Jitter t jcyc-cyc V T =.5 V ps Guaranteed by design, not 00% tested in production. 0472F 0/2/04 9

10 ICS95080 General I 2 C serial interface information The information in this section assumes familiarity with I 2 C programming. For more information, contact ICS for an I 2 C programming application note. How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Notes:. The ICS clock generator is a slave/receiver, I 2 C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 00K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. 0472F 0/2/04 Controller (Host) Start Bit Address D2 (H) Dummy Command Code Dummy Byte Count Byte 0 Byte Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Stop Bit How to Write: ICS (Slave/Receiver) Controller (Host) Start Bit Address D3 (H) Stop Bit How to Read: ICS (Slave/Receiver) Byte Count Byte 0 Byte Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 0

11 ICS95080 I2C Tables BYTE Affected Pin Bit Control Control Function 0 Pin # Name Type 0 PWD Bit 7 - Spread Enabled Spread Spectrum Control RW OFF ON 0 Bit 6 - CPU_T(2:0) Power down mode output level 0= CPU driven in power RW HIGH LOW 0 down = undriven Bit V66_/VCH_CLK VCH/66.66 Select RW Bit 4 53 CPU_STOP#* Reflects value of pin R Stop Active X Bit 3 34 PCI_STOP#* Reflects value of pin at power up. Also can be set. R/RW Stop Active Bit 2 40 FS2 Frequency Selection RW - - X Bit 55 FS Frequency Selection RW - - X Bit 0 54 FS0 Frequency Selection RW - - X BYTE Affected Pin Bit Control Control Function Type Pin # Name 0 PWD Bit 7 43 MULTSEL0* Reflects value of pin R - - x Bit 6 - CPU_T(2:0) CPU_Stop mode output level 0= CPU driven when stopped = undriven RW HIGH LOW 0 Bit 5 45, 44 Bit 4 49, 48 Bit 3 52, 5 Bit 2 45, 44 Bit 49, 48 Bit 0 52, 5 CPUCLKT2 CPUCLKC2 CPUCLKT CPUCLKC CPUCLKT0 CPUCLKC0 CPUCLKT2 CPUCLKC2 CPUCLKT CPUCLKC CPUCLKT2 CPUCLKC2 Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. RW RW RW Not Freerun Freerun 0 Not Freerun Freerun 0 Not Freerun Freerun 0 Output control RW Disable Enable Output control RW Disable Enable Output control RW Disable Enable 0472F 0/2/04

12 ICS95080 BYTE Affected Pin Bit Control Control Function Type 2 Pin # Name 0 PWD Bit () Bit 6 8 PCICLK6 Output control RW Disable Enable Bit 5 7 PCICLK5 Output control RW Disable Enable Bit 4 6 PCICLK4 Output control RW Disable Enable Bit 3 3 PCICLK3 Output control RW Disable Enable Bit 2 2 PCICLK2 Output control RW Disable Enable Bit PCICLK Output control RW Disable Enable Bit 0 0 PCICLK0 Output control RW Disable Enable BYTE Affected Pin Bit Control Control Function Type 3 Pin # Name 0 PWD Bit MHz_DOT Output control RW Disable Enable Bit MHz_USB Output control RW Disable Enable Bit 5 7 PCICLK_F2 Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 4 6 PCICLK_F Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 3 5 PCICLK_F0 Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 2 7 PCICLK_F2 Output control RW Disable Enable Bit 6 PCICLK_F Output control RW Disable Enable Bit 0 5 PCICLK_F0 Output control RW Disable Enable BYTE Affected Pin Bit Control Control Function Type 4 Pin # Name 0 PWD Bit () RW Disable Enable 0 Bit () RW Disable Enable 0 Bit V66_0 Output control RW Disable Enable Bit V66_/VCH_CLK Output control RW Disable Enable Bit V66_5 Output control RW Disable Enable Bit V66_4 Output control RW Disable Enable Bit 22 3V66_3 Output control RW Disable Enable Bit 0 2 3V66_2 Output control RW Disable Enable 0472F 0/2/04 2

13 ICS95080 BYTE Affected Pin Bit Control Control Function Type 5 Pin # Name 0 PWD Bit 7 X - () Bit 6 X - () Bit 5 X - () Bit 4 X - () Bit 3 X - () Bit 2 X - () Bit X - () Bit 0 X - () BYTE Affected Pin Bit Control Control Function Type 6 Pin # Name 0 PWD Bit 7 X Revision ID Bit 3 () R - - Bit 6 X Revision ID Bit 2 () R - - Bit 5 X Revision ID Bit () R - - Bit 4 X Revision ID Bit 0 () R - - Bit 3 X Vendor ID Bit 3 () R - - Bit 2 X Vendor ID Bit 2 () R - - Bit X Vendor ID Bit () R - - Bit 0 X Vendor ID Bit 0 () R F 0/2/04 3

14 ICS V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_ is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. 3V66 (:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci Skews at Common Transition Edges GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS PCI PCI t sk V T =.5 V ps 3V66 3V66 t sk V T =.5 V ps 3V66 to PCI S 3V66-PCI 3V66 (5:0) leads 33MHz PCI ns Guarenteed by design, not 00% tested in production. 0472F 0/2/04 4

15 ICS95080 CPU_STOP# - Assertion (transition from logic "" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I 2 C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition. When the I 2 C Bit 6 of Byte is programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven. When the I 2 C Bit 6 of Byte is programmed to '' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not be driven. Assertion of CPU_STOP# Waveforms CPU_STOP# CPUT CPUC CPU_STOP# Functionality CPU_STOP# CPUT CPUC Normal 0 iref * Mult Normal Float CPU_STOP# - De-assertion (transition from logic "0" to logic "") All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-assertion to active outputs is to be defined to be tetween 2-6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte is programmed to "" then the stopped CPU outputs will be driven High within 3 ns of CPU_Stop# de-assertion. De-assertion of CPU_STOP# Waveforms 0472F 0/2/04 5

16 ICS95080 PD# - Assertion (transition from logic "" to logic "0") When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '' then both CPU and CPU# are undriven. Note the example below shows CPU = 33 MHz and Bit 6 of Byte 0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 00, 33, 200 MHz. Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power Down Assertion of Waveforms 0ns 25ns 50ns PD # CPUT 00MHz CPUC 00MHz 3V66MHz PCI 33MHz USB 48MHz REF 4.38MHz Power Down De-Assertion Mode The power-up latency needs to be less than.8ms. this is the time from the de-asseration of the powerdown of the ramping of the power supply until the time that stable clocks are output from the clock chip. If the I 2 C Bit 6 of Byte 0 is programmed to "" then the stopped CPU outputs will be driven high within 3 ns of PD# de-asseration. 0472F 0/2/04 6

17 ICS95080 PCI_STOP# - Assertion (transition from logic "" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 0 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz tsu 0472F 0/2/04 7

18 ICS95080 INDEX AREA N 2 D E A E h x 45 c α L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e BASIC BASIC h L N SEE VARIATIONS SEE VARIATIONS α e b A 300 mil SSOP Package - C - SEATING PLANE.0 (.004) C VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, MO-8 Ordering Information Example: 0472F 0/2/04 ICS95080yFLF-T ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 8

19 ICS95080 INDEX AREA A2 N 2 D E A E c L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A A b c D E SEE VARIATIONS 8.0 BASIC SEE VARIATIONS 0.39 BASIC E e 0.50 BASIC BASIC L N SEE VARIATIONS SEE VARIATIONS α aaa e b A -C- - SEATING PLANE aaa C VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, MO mm. Body, 0.50 mm. pitch TSSOP (240 mil) (20 mil) Ordering Information ICS95080yGLF-T Example: ICS XXXX y G LF- T 0472F 0/2/04 Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 9