Programmable Timing Control Hub for P4

Transcription

1 ICS9522 Programmable Timing Control Hub for P4 Recommended Application: CK-48 clock for Intel 845 chipset. Output Features: 3 - Pairs of differential CPU 3.3V 3.3V V 3.3V fixed - 3.3V, 48MHz, 24Mhz or 66MHz - 3.3V, 4.38MHz Features/Benefits: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/write operations. Uses external 4.38MHz crystal. Key Specifications: CPU Output Jitter <5ps 3V66 Output Jitter <25ps CPU Output Skew <ps Pin Configuration VDDREF 2 GND *FS/PCICLK7 **FS/PCICLK8 VDDPCI GND *WDEN/PCICLK PCICLK PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_ 3V66_2 3V66_3 #RESET VDDA ICS Pin 3-mil SSOP. These outputs have 2 drive strength. * Internal Pull-up resistor of 2K to VDD ** these inputs have 2K internal pull-down to GND REF/FS2** CPUCLKT CPUCLKC VDDCPU CPUCLKT CPUCLKC GND VDDCPU CPUCLKT2 CPUCLKC2 MULTISEL* I REF GND 48MHz_USB/FS3** 48MHz_DOT/SEL_24_48* AVDD48 GND 3V66_/24_48MHZ#/FS4** VDD3V66 GND SCLK SDATA Vtt_PWRGD/PD#* GND Block Diagram Frequency Table 2 SEL24_48 WDEN MULTSEL FS (4:) SDATA SCLK Vtt_PWRGD# PD# PLL2 TAL OSC PLL Spread Spectrum Control Logic Config. Reg. /2 3V66 DIVDER 3 CPU DIVDER PCI DIVDER MHz_USB 48MHz_DOT 3V66 (3:) 3V66_/24_48MHZ# REF CPUCLKT (2:) CPUCLKC (2:) PCICLK (6:) Reset# I REF FS4 FS3 FS2 FS FS Power Groups VDDA = Analog Core PLL VDDREF = REF, tal AVDD48 = 48MHz CPUCLK MHz 3V66 MHz PCICLK MHz For additional frequency selections please refer to Byte. 467G 3/2/7

2 ICS9522 General The ICS9522 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC33 or DDR memory. It provides all necessary clock signals for such a system. The ICS9522 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to.mhz increment. Pin PIN NUMBER, 7, 3, 8, 3, 4, G 3/2/7 VDD , 8, 4, 9, 25, 29, 32, 36, 42 GND PIN NAME TYPE P WR 3.3V power supply. DESCRIPTION I N Crystal input, has internal load cap (33pF) and feedback resistor from 2. O UT Crystal output, nominally 4.38MHz. Has internal load cap (33pF). P WR Ground pins for 3.3V supply. 22, 2, 2 3V66 (3:) O UT 3.3V Fixed 66MHz clock outputs for HUB PCICLK7 FS PCICLK8 FS WDEN PCICLK 7, 6, 5, 2,, PCICLK (6:) 23 RESET# 24 VDDA OUT 3.3V PCI clock output I N Logic input frequency select bit. Input latched at power on. O UT 3.3V PCI clock output. I N Logic input frequency select bit. Input latched at power on. I N Hardware enable of watch dog circuit. Enabled when latched high. O UT 3.3V PCI clock output. O UT 3.3V PCI clock outputs. OUT Real time system reset signal This signal is active low. P WR Analog power 3.3V. for frequency value or watchdog timmer timeout. Vtt_PWRGD IN This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:) inputs are valid and are ready to be sampled (active high). 26 Asynchronous active low input pin used to power down the device into a low PD# IN power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 28 SCLK IN 2 Clock pin for I C circuitry 5V tolerant. 27 SDATA I/ O 2 Data pin for I C circuitry 5V tolerant. 3V66_/24_48MHZ# OUT 3.3V output selectable through I 2 C to be 66MHz from internal VCO or 3 48MHz/24MHz. FS4 I N Logic input frequency select bit. Input latched at power on. 33 AVDD48 P WR Analog power 3.3V. 48MHz_DOT O UT 3.3V Fixed 48MHz clock output for DOT. 34 This selects the frequency for the SEL24_48 output. SEL24_48 IN High = 24MHz, Low = 48MHz. 35 FS3 I N Logic input frequency select bit. Input latched at power on. 48MHz_USB O UT 3.3V Fixed 48MHz clock output for USB. 37 I REF OUT This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 38 MULTSEL IN 3.3V LVTTL input for selecting the current multiplier for CPU outputs 39, 43, 46 CPUCLKC (2:) OUT "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 4, 44, 47 CPUCLKT (2:) OUT "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 48 FS2 I N Logic input frequency select bit. Input latched at power on. REF O UT 3.3V, 4.38MHz reference clock output. 2

3 ICS9522 Maximum Allowed Current Condition Powerdown Mode (PWRDWN# = ) Full Active Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 4mA 36mA Host Swing Select Functions MULTISEL Board Target Trace/Term Z 5 ohms 5 ohms Reference R, Iref = V DD /(3*Rr) Rr = 22 %, Iref = 5.mA Rr = 475 %, Iref = 2.32mA Output Current Z Ioh = 4* I 5 Ioh = 6* I 5 467G 3/2/7 3

4 ICS9522 General SMBus serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) ACK ACK ACK ACK ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address D3 (H) RD ReaD ACK Data Byte Count = ACK Beginning Byte N ACK Byte N P Not acknowledge stop bit Byte N G 3/2/7 4

5 ICS9522 Byte : Functionality and frequency select register (Default=) (2,7:4) CPUCLK 3V66 PCICLK FS4 FS3 FS2 FS FS MHz MHz MHz Spread % /-.35% center spread to -.6% down spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread to -.6% down spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread /-.35% center spread to -.6% down spread to -.6% down spread - Frequency is selected by hardware select, latched inputs - Frequency is selected by 2,7:4 - Normal - Spread spectrum enable - Watch dog safe frequency will be selected by latch inputs - Watch dog safe frequency will be programmed by Byte bit (4:) Note Notes:. Default at power-up will be for latched logic inputs to define frequency, as displayed by G 3/2/7 5

6 ICS9522 Byte : Output Control Register ( = enable, = disable) B it Pin# 7 4, 39 CPUT/C , 43 CPUT/C 5 47, 46 CPUT/C 4 - FS4 Read back 3 - FS3 Read back 2 - FS2 Read back - FS Read back - FS Read back Byte 2: Output Control Register ( = enable, = disable) B it Pin# 7 - MULTSEL (Read back) 6 7 PCICLK_ PCICLK_ PCICLK_ PCICLK_ 3 2 PCICLK_ 2 PCICLK_ 9 PCICLK_ Byte 3: Output Control Register ( = enable, = disable) B it Pin# MHZ_DO T MHz_US B 5 - Reset gear shift detect = Enable, = Disable 4 - Reserved V66_/24_48MHZ#, (default) = 66.66MHz, = 24_48MHZ# 2 - Reserved 6 PCICLK8 5 PCICLK7 Byte 4: Output Control Register ( = enable, = disable) B it Pin# 7 - Async. 3V66 control bit : 3V66 / PCI = 64/32 MHz asynchronous with CPU : 3V66 / PCI = 66.6/33.3 MHz synchronous with CPU 6 - Reserved 5 - Reserved 4 3 3V66_/24_48MHZ # 3 - Reserved V66_ 3 2 3V66_ 2 2 3V66_ Notes:. = Power on Default 2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low. 467G 3/2/7 6

7 ICS9522 Byte 5: Programming Edge Rate ( = enable, = disable) B it Pin# 7 (Reserved ) 6 (Reserved ) 5 (Reserved ) 4 (Reserved ) 3 (Reserved ) 2 (Reserved ) (Reserved ) (Reserved ) Byte 6: Vendor ID Register ( = enable, = disable) 7 Revision ID 3 6 Revision ID 2 5 Revision ID 4 Revision ID 3 Vendor ID 3 (Reserved ) 2 Vendor ID 2 (Reserved ) Vendor ID (Reserved ) Vendor ID (Reserved ) Revision ID values will be based on individual device's revision Byte 7: Revision ID and Device ID Register 7 Device ID7 6 Device ID6 5 Device ID5 4 Device ID4 3 Device ID3 2 Device ID2 Device ID Device ID Device ID values will "22H" in this case. be based on individual device Byte 8: Byte Count Read Back Register 7 Byte7 6 Byte6 5 Byte5 4 Byte4 3 Byte3 2 Byte2 Byte Byte Note: Writing to this register will configure byte count and how many bytes will be read back, default is F H = 5 bytes. 467G 3/2/7 7

8 ICS9522 Byte 9: Watchdog Timer Count Register 7 WD7 6 WD6 5 WD5 4 WD4 3 WD3 2 WD2 WD WD The decimal representation of these 8 bits correspond to 29ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 8 29ms = 2.3 seconds. Byte : Programming Enable bit 8 Watchdog Control Register 7 Programming Enable bit Program = no programming. Frequencies are selected by HW latches or Byte Enable 2 = enable all I C programing. 6 WD Enable Watchdog Enable bit. This bit will over write WDEN latched value. = disable, = Enable. 5 WD Alarm Watchdog Alarm Status = normal = alarm status 4 SF4 3 SF3 Watchdog safe frequency bits. Writing to these bits will configure the safe 2 SF2 frequency corrsponding to Byte 2, 7:4 table SF SF Byte : VCO Frequency M Divider (Reference divider) Control Register 7 Ndiv 8 N divider bit 8 6 Mdiv 6 5 Mdiv 5 4 Mdiv 4 The decimal respresentation of Mdiv (6:) corresposd to the 3 Mdiv 3 reference divider value. Default at power up is equal to the 2 Mdiv 2 latched inputs selection. Mdiv Mdiv Byte 2: VCO Frequency N Divider (VCO divider) Control Register 7 Ndiv 7 6 Ndiv 6 5 Ndiv 5 4 Ndiv 4 3 Ndiv 3 2 Ndiv 2 Ndiv Ndiv The decimal representation of Ndiv (8:) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte. 467G 3/2/7 8

9 ICS9522 Byte 3: Spread Spectrum Control Register 7 SS 7 6 SS 6 5 SS 5 4 SS 4 3 SS 3 2 SS 2 SS SS The Spread Spectrum (2:) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider. Byte 4: Spread Spectrum Control Register 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 SS 2 Spread Spectrum 2 3 SS Spread Spectrum 2 SS Spread Spectrum SS 9 Spread Spectrum 9 SS 8 Spread Spectrum 8 Byte 5: Output Divider Control Register 7 CPU Div 3 6 CPU Div 2 5 CPU Div 4 CPU Div 3 CPU Div 3 2 CPU Div 2 CPU Div CPU Div CPU 2 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. CPU (:) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. Byte 6: Output Divider Control Register 7 Div 3 6 Div 2 5 Div 4 Div 3 Div 3 2 Div 2 Div Div 3V66_ clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. 3V66 (3:) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. 467G 3/2/7 9

10 ICS9522 Byte 7: Output Divider Control Register 7 3V66_INV 3V66_ Phase Inversion bit 6 3V66_INV 3V66 (3:) Phase Inversion bit 5 CPU_INV CPU 2 Phase Inversion bit 4 CPU_INV CPU (:) Phase Inversion bit 3 PCI Div 3 2 PCI Div 2 PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. PCI Div Default at power up is latched FS divider. PCI Div Table Table 2 Div (3:2) Div (:) / 2 / 4 / 8 /6 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 7 / 4 / 28 /56 Div (3:2) Div (:) / 4 / 8 / 6 /32 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 9 / 8 / 36 /72 Byte 8: Group Skew Control Register it 7 CPU_Skew These 2 bits delay the CPUCLKC/T2 with respect to CPUCLKC/T (:) CPU_Skew = ps = 25ps = 5ps =75ps Reserved Reserved B Reserved Reserved 3 CPU_Skew T hese 2 bits delay the CPUCLKC/T (:) CPUCLKC/T2 2 CPU_Skew = ps = 25ps = 5ps = 75ps Reserved Reserved Reserved Reserved clock with respect to Byte 9: Group Skew Control Register 7 3V66_Skew These 2 bits delay the 3V66 (3:) with respect to CPUCLK 6 3V66_Skew = ps = 25ps = 5ps =75ps 5 Reserved Reserved 4 Reserved Reserved 3 3V66_Skew These 2 bits delay the 3V66_ with respect to CPUCLK 2 3V66_Skew = ps = 25ps = 5ps =75ps Reserved Reserved Reserved Reserved 467G 3/2/7

11 ICS9522 Byte 2: Group Skew Control Register 7 PCI_Skew 3 These 4 bits can change the CPU to PCI (6:) skew from -.3ns 6 PCI_Skew 2.2ns. Default at power up is.5ns. Each binary increment or 5 PCI_Skew decrement of s (3:) will increase or decrease the delay of the 4 PCI_Skew PCI clocks by ps. 3 PCI_Skew 3 These 4 bits can change the CPU to PCI (8:7) skew from -.6ns 2 PCI_Skew 2.2ns. Default at power up is.4ns. Each binary increment or PCI_Skew decrement of (3:) will increase or decrease the delay of the PCI_Skew PCI clocks by ps. Byte 2: Slew Rate Control Register 7 Reserved Reserved 6 Reserved Reserved 5 PCIF Slew PCIF(:) clock slew rate control bits. 4 PCIF Slew = strong: = normal; = weak 3 3V66 (3:)_Slew 3V66 (3:) clock slew rate control bits. 2 3V66 (3:)_Slew = strong: = normal; = weak 3V66 Slew 3V66_ clock slew rate control bits. 3V66 Slew = strong: = normal; = weak Byte 22: Slew Rate Control Register 7 REF Slew REF clock slew rate control bits. 6 REF Slew = strong: = normal; = weak 5 PCI (6:4) Slew PCI (6:4) clock slew rate control bits. 4 PCI (6:4) Slew = strong: = normal; = weak B it 3 PCI (3:) Slew PCI (3:) clock slew rate control bits. B it 2 PCI (3:) Slew = strong: = normal; = weak PCI Slew PCI clock slew rate control bits. PCI Slew = strong: = normal; = weak Byte 23: Slew Rate Control Register 7 Reserved 6 Reserved Reserved 5 VCH Slew VCH clock slew rate control bits. 4 VCH Slew = strong: = normal; = weakk 3 48USB Slew 48USB clock slew rate control bits. 2 48USB Slew = strong: = normal; = weakk 48DOT Slew 48DOT clock slew rate control bits. 48DOT Slew = strong: = normal; = weak 467G 3/2/7

12 ICS9522 Absolute Maximum Ratings Supply Voltage V Logic Inputs GND.5 V to V DD +.5 V Ambient Operating Temperature C to +7 C Case Temperature C Storage Temperature C to +5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Input High Voltage V IH 2 V DD +.3 V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD -5 5 ma V I IN = V; Inputs with no pull-up IL resistors Input Low Current -5 ma I IL2 V IN = V; Inputs with pull-up resistors -2 Operating Supply Current I DD3.3OP C L = Full load ma Powerdown Current I DD3.3PD IREF=2.32 ma 2 25 ma Input Frequency F i V DD = 3.3 V 4.38 MHz Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C OUT Output pin capacitance 6 pf C IN & 2 pins pf Transition time T trans To st crossing of target frequency 3 ms Settling time From st crossing to % target T s frequency 3 ms Clk Stabilization From V T DD = 3.3 V to % target STAB frequency 3 ms Delay t PZH,t PZL Output enable delay (all outputs) ns t PHZ,t PLZ Output disable delay (all outputs) ns 3V66 to PCI S 3V66-PCI 3V66 (5:) leads 33MHz PCI ns Guaranteed by design, not % tested in production. 467G 3/2/7 2

13 ICS9522 Electrical Characteristics - CPU.7V Current Mode Differential Pair T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω Voltage High VHigh Statistical measurement on single ended signal using mv Voltage Low VLow oscilloscope math function Max Voltage Vovs Measurement on single ended mv Min Voltage Vuds signal using absolute value Crossing Voltage (abs) Vcross(abs) mv Crossing Voltage (var) d-vcross Variation of crossing over all edges 2 4 mv Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 2MHz nominal ns 2 2MHz spread ns MHz nominal ns 2 Average period Tperiod 66.66MHz spread ns MHz nominal ns MHz spread ns 2.MHz nominal ns 2.MHz spread ns 2 2MHz nominal ns,2 Absolute min period T absmin 66.66MHz nominal/spread ns, MHz nominal/spread ns,2.mhz nominal/spread ns,2 Rise Time t r V OL =.75V, V OH =.525V ps Fall Time t f V OH =.525V V OL =.75V ps Rise Time Variation d-t r 3 25 ps Fall Time Variation d-t f 3 25 ps Measurement from differential Duty Cycle d t3 wavefrom % Skew t sk3 V T = 5% 8 5 ps Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 6 5 ps Guaranteed by design, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 4.388MHz 467G 3/2/7 3

14 ICS9522 Electrical Characteristics - PCICLK T A = - 7 C; VDD=3.3V +/-5%; C L = -3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V V OH@MIN =. V, Output High Current I OH V OH@MA = 3.35 V ma V =.95 V, Output Low Current I OL V =.4 V 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL =.4 V ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 28 5 ps Jitter,cycle to cyc t jcyc-cyc V T =.5 V 2 5 ps Guaranteed by design, not % tested in production. Electrical Characteristics - 3V66 T A = - 7 C; VDD=3.3V +/-5%; C L = -3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V V OH@MIN =. V, Output High Current I OH V OH@MA = 3.35 V ma V =.95 V, Output Low Current I OL V =.4 V 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL =.4 V ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 6 25 ps Jitter t jcyc-cyc V T =.5 V 2 25 ps Guaranteed by design, not % tested in production. Note: 3V66@66Mhz- main PLL 467G 3/2/7 4

15 ICS9522 Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB T A = - 7 C; VDD=3.3V +/-5%; C L = -2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O V O = V DD *(.5) 48 MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma V Output Low Voltage V OL I OL = ma.9.55 V Output High Current I OH V OH@MIN =. V, V OH@MA = 3.35 V ma Output Low Current I OL V =.95 V, V =.4 V ma 48DOT Rise Time t r V OL =.4 V, V OH = 2.4 V.5.77 ns 48DOT Fall Time t f V OH = 2.4 V, V OL =.4 V.5.84 ns VCH 48 USB Rise Time t r V OL =.4 V, V OH = 2.4 V.2 2 ns VCH 48 USB Fall Time t f V OH = 2.4 V, V OL =.4 V.42 2 ns 48DOTDuty Cycle d t V T =.5 V % 48 USB Duty Cycle d t V T =.5 V % Jitter t jcyc-cyc V T =.5 V 3 35 ps Guaranteed by design, not % tested in production. Electrical Characteristics - REF T A = - 7 C; VDD=3.3V +/-5%; C L = -2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O 4.3 MHz Output Impedance R DSP V O = V DD *(.5) 2 6 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH V OH@MIN =. V, V OH@MA = 3.35 V ma Output Low Current I OL V =.95 V, V =.4 V ma Rise Time t r V OL =.4 V, V OH = 2.4 V.7 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.76 2 ns Duty Cycle d t V T =.5 V % Jitter t jcyc-cyc V T =.5 V 35 ps Guaranteed by design, not % tested in production. 467G 3/2/7 5

16 ICS9522 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 467G 3/2/7 6

17 ICS9522 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_ is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. 3V66 (:) 3V66 (4:2) 3V66_5 PCICLK_F (2:) PCICLK (6:) Tpci Group Skews at Common Transition Edges GROUP SYMBOL CONDITIONS MIN TYP MA UNITS 3V66 3V66 3V66 (5:) pin to pin skew 5 ps PCI PCI PCI_F (2:) and PCI (6:) pin to pin skew 5 ps 3V66 to PCI S 3V66-PCI 3V66 (5:) leads 33MHz PCI ns Guaranteed by design, not % tested in production. PD# Functionality CPU_STOP# CPUT CPUC 3V66 66MHz_OUT PCICLK_F PCICLK PCICLK USB/DOT 48MHz Normal Normal 66MHz 66MHz_IN 66MHz_IN 66MHz_IN 48MHz iref * Mult Float Low Low Low Low Low 467G 3/2/7 7

18 ICS9522 PCI_STOP# - Assertion (transition from logic "" to logic "") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:] and stoppable PCI_F[2,] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms PCI_STOP# PCI_F[2:] 33MHz PCI[6:] 33MHz tsu CPU_STOP# - Assertion (transition from logic "" to logic "") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I 2 C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL) (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms CPU_STOP# CPUT CPUC CPU_STOP# Functionality CPU_STOP# CPUT CPUC Normal iref * Mult Normal Float 467G 3/2/7 8

19 ICS9522 INDE AREA N 2 D E A E h x 45 c L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS α 8 8 e b A 3 mil SSOP Package -C- - SEATING PLANE. (.4) C -34 VARIATIONS D mm. D (inch) N MIN MA MIN MA Reference Doc.: JEDEC Publication 95, MO-8 Ordering Information ICS9522yFLFT Example: ICS y F LF - T 467G 3/2/7 Designation for tape and reel packaging RoHs Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 9

20 ICS9522 Revision History Rev. Issue Date Page # F 7/28/25 Added LF Ordering Information. 9 G 3/2/27 Updated Electrical Characteristics CPU Skew spec G 3/2/7 2