Programmable Timing Control Hub for Intel-based Servers

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1 Programmable Timing Control Hub for Intel-based Servers Recommended Application: CK41B clock for Intel-based servers Output Features: 4 -.7V current-mode differential CPU pairs 5 -.7V current-mode differential SRC pair 4 - PCI (33MHz) 3 - PCICLK_F, (33MHz) free-running 1-48MHz 2 - REF, MHz Key Specifications: CPU cycle-cycle jitter: < 5ps SRC cycle-cycle jitter: < 125ps PCI cycle-cycle jitter: < 5ps CPU output skew: < 5ps SRC output skew: < 25ps ± 3ppm frequency accuracy on all outputs except 48MHz ± 1ppm frequency accuracy on 48MHz Features/Benefits: Supports spread spectrum modulation, to -.5% down spread Uses external MHz crystal and external load capacitors for low ppm synthesis error CPU clocks independent of SRC/PCI clocks D2/D3 SMBus address 932S41 Functionality Pin Configuration FS_C 1 FS_B 1 FS_A 2 CPU SRC PCI REF USB MHz MHz MHz MHz MHz Reserved 1. FS_B and FS_C are three-level inputs. Please see V IL_FS and V IH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_A is a low-threshold input. Please see the V IL_FS and V IH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. VDDPCI 1 GNDPCI 2 PCICLK 3 PCICLK1 4 PCICLK2 5 PCICLK3 6 GNDPCI 7 VDDPCI 8 PCICLK_F 9 PCICLK_F1 1 PCICLK_F2 11 VDD MHz 13 GND4814 VDDSRC 15 SRCCLKT 16 SRCCLKC 17 SRCCLKC1 18 SRCCLKT1 19 GNDSRC 2 SRCCLKT2 21 SRCCLKC2 22 SRCCLKC3 23 SRCCLKT3 24 VDDSRC 25 SRCCLKT4 26 SRCCLKC4 27 VDDSRC FS_C/TEST_SEL 55 REF 54 REF1 53 VDDREF 52 X1 51 X2 5 GNDREF 49 FS_B/TEST_MODE 48 FS_A 47 VDDCPU 46 CPUCLKT 45 CPUCLKC 44 VDDCPU 43CPUCLKT1 42 CPUCLKC1 41 GNDCPU 4 CPUCLKT2 39 CPUCLKC2 38 VDDCPU 37 CPUCLKT3 36 CPUCLKC3 35 VDDA 34 GNDA 33 IREF 32 NC 31 Vtt_PwrGd#/PD 3 SDATA 29 SCLK 56-pin SSOP & TSSOP

2 Pin Description Pin # PIN NAME PIN TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GNDPCI PWR Ground pin for the PCI outputs 3 PCICLK OUT PCI clock output. 4 PCICLK1 OUT PCI clock output. 5 PCICLK2 OUT PCI clock output. 6 PCICLK3 OUT PCI clock output. 7 GNDPCI PWR Ground pin for the PCI outputs 8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 9 PCICLK_F OUT Free running PCI clock not affected by PCI_STOP#. 1 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP#. 11 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP#. 12 VDD48 PWR Power pin for the 48MHz output.3.3v 13 48MHz OUT 48MHz clock output. 14 GND48 PWR Ground pin for the 48MHz outputs 15 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 16 SRCCLKT OUT True clock of differential SRC clock pair. 17 SRCCLKC OUT Complement clock of differential SRC clock pair. 18 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 2 GNDSRC PWR Ground pin for the SRC outputs 21 SRCCLKT2 OUT True clock of differential SRC clock pair. 22 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 23 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 26 SRCCLKT4 OUT True clock of differential SRC clock pair. 27 SRCCLKC4 OUT Complement clock of differential SRC clock pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 2

3 Pin Description (Continued) Pin # PIN NAME Type Pin Description 29 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 3 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 31 Vtt_PwrGd#/PD IN Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 32 NC N/A No Connection. 33 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 34 GNDA PWR Ground pin for the PLL core. 35 VDDA PWR 3.3V power for the PLL core. 36 CPUCLKC3 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 37 CPUCLKT3 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 38 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 39 CPUCLKC2 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 4 CPUCLKT2 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 41 GNDCPU PWR Ground pin for the CPU outputs 42 CPUCLKC1 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 43 CPUCLKT1 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 44 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 45 CPUCLKC OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 46 CPUCLKT OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 47 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 48 FS_A IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. 49 FS_B/TEST_MODE IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. 5 GNDREF PWR Ground pin for the REF outputs. 51 X2 OUT Crystal output, Nominally MHz 52 X1 IN Crystal input, Nominally MHz. 53 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 54 REF1 OUT MHz reference clock. 55 REF OUT MHz reference clock. 56 FS_C/TEST_SEL IN 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 3

4 General Description is a main clock synthesizer for CK41-generation Intel server platforms. is driven with a MHz crystal. It generates CPU outputs up to 4MHz and PCI-Express clocks at 1 or 2 MHz. The 48 MHz USB clock is an exact 48. MHz clock. The generates all clocks with less the +/- 3 ppm error. Block Diagram REF(1:) X1 X2 XTAL OSC. FIXED PLL DIVIDER 48MHz CPU PLL DIVIDERS CPUCLK(2:) SRC/PCI PLL DIVIDERS SRCCLK(4:) PCICLK(3:), PCICLK_F(2:) FS(C:A) TEST_SEL CONTROL LOGIC VTT_PWRGD#/PD SDATA SCLK IREF Power Groups Pin Number VDD GND Description 53 5 Xtal, Ref 1,8 2,7 PCICLK outputs 15,25,28 2 SRCCLK outputs Master clock, CPU Analog MHz, PLL_48 47,44,38 41 CPUCLK clocks 4

5 Absolute Max Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage V DD +.5V V VDD_In 3.3V Logic Input Supply Voltage GND -.5 V DD +.5V V Ts Storage Temperature C Tambient Ambient Operating Temp 7 C Tcase Case Temperature 115 C ESD prot Input ESD protection human body model 2 V Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage V IH 3.3 V +/-5% 2 V DD +.3 V Input Low Voltage V IL 3.3 V +/-5% V SS V Input High Current I IH V IN = V DD -5 5 ua Input Low Current I IL1 V IN = V; Inputs with no pullup resistors -5 ua I IL2 V IN = V; Inputs with pull-up resistors -2 ua Low Threshold Input High Voltage V IH_FS 3.3 V +/-5%.7 V DD +.3 V Low Threshold Input Low Voltage V IL_FS 3.3 V +/-5% V SS V Operating Supply Current I DD3.3OP 3.3 V +/-5%, Full Load ma Powerdown Current I DD3.3PD all diff pairs driven 6 9 ma all differential pairs tri-stated 9 15 ma Input Frequency 3 F i V DD = 3.3 V MHz 3 Pin Inductance 1 L pin 7 nh 1 C IN Logic Inputs 5 pf 1 Input Capacitance 1 C OUT Output pin capacitance 6 pf 1 C INX X1 & X2 pins 5 pf 1 Clk Stabilization 1,2 From V T DD Power-Up or deassertion of PD# to 1st clock STAB 1.8 ms 1,2 Modulation Frequency Triangular Modulation 3 33 khz 1 Tdrive_PD# CPU output enable after PD# de-assertion 3 us 1 Tfall_Pd# PD# fall time of 5 ns 1 Trise_Pd# PD# rise time of 5 ns 2 SMBus Voltage V IMAX Max. Voltage on SCLK/SDAT 5.5 V 1 Low-level Output Voltage V I PULLUP.4 V 1 Current sinking at V OL =.4 V I PULLUP 4 ma 1 SCLK/SDATA Clock/Data Rise Time T RI2C (Max VIL -.15) to (Min VIH +.15) 1 ns 1 SCLK/SDATA Clock/Data Fall Time T FI2C (Min VIH +.15) to (Max VIL -.15) 3 ns 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal MHz to meet ppm accuracy on PLL outputs. 5

6 Electrical Characteristics - CPU.7V Current Mode Differential Pair T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω 1 Voltage High VHigh Statistical measurement on single Voltage Low VLow ended signal using oscilloscope math function mv 1 Max Voltage Vovs Measurement on single ended mv Min Voltage Vuds signal using absolute value Crossing Voltage (abs) Vcross(abs) mv 1 Crossing Voltage (var) d-vcross Variation of crossing over all edges 9 14 mv 1 Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 4MHz nominal ns 2 4MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2 Average period Tperiod 2MHz nominal ns 2 2MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2 1.MHz nominal ns 2 1.MHz spread ns 2 4MHz nominal/spread ns 1, MHz nominal/spread ns 1, MHz nominal/spread ns 1,2 Absolute min period T absmin 2MHz nominal/spread ns 1, MHz nominal/spread ns 1, MHz nominal/spread ns 1,2 1.MHz nominal/spread ns 1,2 Rise Time t r V OL =.175V, V OH =.525V ps 1 Fall Time t f V OH =.525V V OL =.175V ps 1 Rise Time Variation d-t r ps 1 Fall Time Variation d-t f ps 1 Measurement from differential Duty Cycle d t3 wavefrom % 1 Skew t sk3 CPU (3:) V T = 5% 33 5 ps 1 Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 38 5 ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at MHz 6

7 Electrical Characteristics - SRC.7V Current Mode Differential Pair T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Zo V O = V x 3 Ω 1 Impedance Voltage High VHigh Statistical measurement on single mv Voltage Low VLow ended signal using oscilloscope Max Voltage Vovs Measurement on single ended mv Min Voltage Vuds signal using absolute value Crossing Voltage (abs) Vcross(abs) mv 1 Crossing Voltage (var) d-vcross Variation of crossing over all edges mv 1 Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 Average period Tperiod 1.MHz nominal ns 2 1.MHz spread ns 2 Absolute min period Tabsmin 1.MHz nominal/spread ns 1,2 Rise Time t r V OL =.175V, V OH =.525V ps 1 Fall Time t f V OH =.525V V OL =.175V ps 1 Rise Time Variation d-t r ps 1 Fall Time Variation d-t f ps 1 Measurement from differential Duty Cycle d t3 wavefrom % 1 Skew t sk3 SRC(4:), V T = 5% ps 1 Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at MHz 7

8 Electrical Characteristics - PCICLK/PCICLK_F T A = - 7 C; V DD = 3.3 V +/-5%; C L = 5 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values ppm 1,2 Clock period T period 33.33MHz output nominal ns MHz output spread ns 2 Absolute Min/Max Clock 33.33MHz output nominal ns 2 T abs period 33.33MHz output spread ns 2 Clk High Time t h1 12 N/A ns 1 Clock Low Time t l1 12 N/A ns 1 Output High Voltage V OH I OH = -1 ma 2.4 V Output Low Voltage V OL I OL = 1 ma.55 V Output High Current I OH V = 1. V -33 ma V MAX = V -33 ma Output Low Current I OL V MIN = 1.95 V 3 ma V MAX =.4 V 38 ma Rise Time t r1 V OL =.4 V, V OH = 2.4 V ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V ns 1 Duty Cycle d t1 V T = 1.5 V % 1 Skew t sk1 V T = 1.5 V 43 5 ps 1 Jitter t jcyc-cyc V T = 1.5 V 98 5 ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at MHz Electrical Characteristics - 48MHz T A = - 7 C; V DD = 3.3 V +/-5%; C L = 5 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -1 1 ppm 1,2 Clock period T period 48.MHz output nominal ns 2 Absolute Min/Max Clock period T abs Nominal ns 2 Clk High Time t h ns 1 Clock Low Time t l ns 1 Output High Current I OH V MIN = 1. V -33 ma V MAX = V -33 ma Output Low Current I OL V = 1.95 V 3 ma V MAX =.4 V 38 ma Rise Time t r1 V OL =.4 V, V OH = 2.4 V ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V ns 1 Duty Cycle d t1 V T = 1.5 V % 1 Jitter, Cycle to cycle t jcyc-cyc V T = 1.5 V ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at MHz 8

9 Electrical Characteristics - REF MHz T A = - 7 C; V DD = 3.3 V +/-5%; C L = 5 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1 Clock period T period MHz output nominal ns 1 Absolute Min/Max Clock period T abs Nominal ns 2 Output High Voltage V OH I OH = -1 ma 2.4 V 1 Output Low Voltage V OL I OL = 1 ma.4 V 1 V = 1. V, Output High Current I OH V = V ma 1 V = 1.95 V, Output Low Current I OL V =.4 V ma 1 Rise Time t r1 V OL =.4 V, V OH = 2.4 V ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V ns 1 Skew t sk1 V T = 1.5 V 26 5 ps 1 Duty Cycle d t1 V T = 1.5 V % 1 Jitter t jcyc-cyc V T = 1.5 V ps 1 1 Guaranteed by design, not 1% tested in production. 9

10 Single-ended Output Terminations Rs Zo CL=5pF SEPP Output Buffer (Single Ended Push Pull) Test Load Rs Zo CL=5pF Rs Zo CL=5pF SEPP Output Buffer (Single Ended Push Pull) The singled-ended outputs of the ICS 932S41E default to a drive strength of 2 loads. The REF clocks can be turned down to 1-load strength via the SMBus. Suggested termination resistors are as follows for transmission lines with Zo = 5 ohms: Single-ended outputs at 2-load strength (Power up default for all single-ended outputs) Single-ended outputs at 1-load strength (REF clock only) Driving 1 load, Rs = 33 ohms Driving 2 loads, Rs = 7.5 ohms Driving 1 load, Rs = 22 ohms 1

11 General SMBus serial interface information for the How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N Byte N + X - 1 P stop bit X Byte ICS (Slave/Receiver) ACK ACK ACK ACK ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address D3 (H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte N P Not acknowledge stop bit Byte N + X

12 SMBus Table: SRC Output Enable Register Byte Pin # Name Control Function Type 1 PWD Bit 7 NA SRCCLK7 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 6 NA SRCCLK6 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 5 NA SRCCLK5 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 4 26,27 SRCCLK4 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 3 23,24 SRCCLK3 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 2 21,22 SRCCLK2 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 1 18,19 SRCCLK1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 16,17 SRCCLK Enable Output Enable RW Disable-Hi-Z Enable 1 SMBus Table: CPU, REF and 48 MHz Output Enable Register Byte 1 Pin # Name Control Function Type 1 PWD Bit 7 54 REF1 Enable Output Enable RW Disable-Low Enable 1 Bit 6 55 REF Enable Output Enable RW Disable-Low Enable 1 Bit 5 36,37 CPUCLK3 Output Enable RW Disable-Hi-Z Enable 1 Bit 4 39,4 CPUCLK2 Output Enable RW Disable-Hi-Z Enable 1 Bit 3 RESERVED Bit 2 42,43 CPUCLK1 Output Enable RW Disable-Hi-Z Enable 1 Bit 1 45,46 CPUCLK Output Enable RW Disable-Hi-Z Enable 1 Bit CPU, SRC, PCI Spread Spectrum Enable Spread Off/On RW Spread Off Spread On SMBus Table: PCI and PCICLK_F Output Enable Register Byte 2 Pin # Name Control Function Type 1 PWD Bit 7 6 PCICLK3 Output Enable RW Disable-Low Enable 1 Bit 6 5 PCICLK2 Output Enable RW Disable-Low Enable 1 Bit 5 4 PCICLK1 Output Enable RW Disable-Low Enable 1 Bit 4 3 PCICLK Output Enable RW Disable-Low Enable 1 Bit 3 11 PCICLK_F2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 1 PCICLK_F1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 9 PCICLK_F Enable Output Enable RW Disable-Low Enable 1 Bit 13 48MHz Enable Output Enable RW Disable-Low Enable 1 SMBus Table: PCICLK_F and SRC Stop Control Register Byte 3 Pin # Name Control Function Type 1 PWD Bit 7 11 PCICLK_F2 Stop En RW Free-Running Stoppable 1 Bit 6 1 PCICLK_F1 Stop En RW Free-Running Stoppable 1 Bit 5 9 PCICLK_F Stop En RW Free-Running Stoppable 1 Free-Running Control, Default: not Bit 4 26,27 SRCCLK4 Stop En RW Free-Running Stoppable 1 affected by PCI/SRC_STOP Bit 3 23,24 SRCCLK3 Stop En (Byte 6, bit 3) RW Free-Running Stoppable 1 Bit 2 21,22 SRCCLK2 Stop En RW Free-Running Stoppable 1 Bit 1 18,19 SRCCLK1 Stop En RW Free-Running Stoppable 1 Bit 16,17 SRCCLK Stop En RW Free-Running Stoppable 1 12

13 SMBus Table: CPU and SRC Stop and Power Down Mode Drive Control Register Byte 4 Pin # Name Control Function Type 1 PWD Bit 7 36,37 CPUCLK3 PD Drive Drive Mode in PD RW Driven Hi-Z Bit 6 39,4 CPUCLK2 PD Drive Drive Mode in PD RW Driven Hi-Z Bit 5 42,43 CPUCLK1 PD Drive Drive mode in PD RW Driven Hi-Z Bit 4 45,46 CPUCLK PD Drive Drive mode in PD RW Driven Hi-Z Bit 3 36,37 CPUCLK3 Stop En RW Free-Running Stoppable 1 Bit 2 39,4 CPUCLK2 Stop En Free-Running Control, Default: not RW Free-Running Stoppable 1 Bit 1 42,43 CPUCLK1 Stop En affected by CPU_STOP RW Free-Running Stoppable 1 Bit 45,46 CPUCLK Stop En RW Free-Running Stoppable 1 SMBus Table: Output and Spread Spectrum Control Register Byte 5 Pin # Name Control Function Type 1 PWD Bit 7 RESERVED Bit 6 SRC SRC Stop Drive Mode Driven in STOP RW Driven Hi-Z Bit 5 SRC SRC PD Drive Mode Driven in PD RW Driven Hi-Z Bit 4 RESERVED Bit 3 36,37 CPUCLK3 Stop Drive Drive Mode in Stop RW Driven Hi-Z Bit 2 39,4 CPUCLK2 Stop Drive Drive Mode in Stop RW Driven Hi-Z Bit 1 42,43 CPUCLK1 Stop Drive Drive Mode in Stop RW Driven Hi-Z Bit 45,46 CPUCLK Stop Drive Drive Mode in Stop RW Driven Hi-Z SMBus Table: Device ID Register Byte 6 Pin # Name Control Function Type 1 PWD Test Mode Selection Test Mode Selection RW Hi-Z REF/N Test Clock Mode Entry Test Mode RW Disable Enable RESERVED Bit 4 54,55 REF Drive Strength 1X or 2X RW 1X 2X 1 Bit 3 PCI, SRC PCI_STOP Control Stop non-free running PC and SRC clocks. RW Stop Run 1 FS_C FS_C readback R Latch See 932S41 Functionality FS_B FS_B readback R Latch Table Bit - FS_A FS_A readback R Latch SMBus Table: Vendor & Revision ID Register Byte 7 Pin # Name Control Function Type 1 PWD RID3 R - - X RID2 R - - X REVISION ID RID1 R - - X RID R - - X Bit 3 - VID3 R - - VID2 R - - VENDOR ID VID1 R - - Bit - VID R

14 SMBus Table: Byte Count Register Byte 8 Pin # Name Control Function Type 1 PWD BC7 RW BC6 RW BC5 RW Writing to this register will configure how many bytes will BC4 RW Byte Count Programming b(7:) be read back, default is 8 Bit 3 - BC3 RW bytes. BC2 RW ( to 7) 1 BC1 RW 1 Bit - BC RW 1 SMBus Table: Device ID Register Byte 9 Pin # Name Control Function Type 1 PWD Bit 7 DID7 R - - Bit 6 DID6 R - - Bit 5 DID5 R - - Bit 4 DID4 Device ID R - - Bit 3 DID3 (B hex) R Bit 2 DID2 R - - Bit 1 DID1 R Bit DID R SMBus Table: M/N Programming & Control Register Byte 1 Pin # Name Control Function Type 1 PWD M/N_EN CPU and SRC M/N Programming Enable RW Disable Enable Bit 6 CPU CPU_STOP Control Stop non-free running PC and SRC clocks. RW Stop Run 1 RESERVED RESERVED Bit 3 SRC, PCI SRC Alternate Frequency (96% of Nominal) Set SRC = 96 MHz and PCI = 32 MHz Only active if Byte 1, bit 2 = 1 RW Normal Alternate Frequency Bit 2 CPU CPU Alternate Frequency Set alternate CPU frequency: (96% of Nominal) Only Alternate 166 MHz to 16 MHz RW Normal active if latched frequency Frequency 333 MHz to 32 MHz is 166 MHz or 333 MHz. Bit 1 55 REF Drive Strength 1X or 2X RW See REF Drive Strength 1 Bit 54 REF1 Drive Strength 1X or 2X RW Functionality Table 1 14

15 SMBus Table: CPU Frequency Control Register Byte 11 Pin # Name Control Function Type 1 PWD CPU N Div8 N Divider Prog bit 8 RW X The decimal representation of CPU N Div9 N Divider Prog bit 9 RW X M and N Divider in Byte 11 and CPU M Div5 RW 12 will configure the CPU VCO X CPU M Div4 RW frequency. Default at power X Bit 3 - CPU M Div3 M Divider Programming RW up = latch-in or Byte Rom X CPU M Div2 bit (5:) RW table. VCO Frequency = X x [NDiv(9:)+8] / CPU M Div1 RW X [MDiv(5:)+2] Bit - CPU M Div RW X SMBus Table: CPU Frequency Control Register Byte 12 Pin # Name Control Function Type 1 PWD CPU N Div7 RW X The decimal representation of CPU N Div6 RW X M and N Divider in Byte 11 and CPU N Div5 RW 12 will configure the CPU VCO X CPU N Div4 N Divider Programming Byte12 RW frequency. Default at power X Bit 3 - CPU N Div3 bit(7:) and Byte11 bit(7:6) RW up = latch-in or Byte Rom X CPU N Div2 RW table. VCO Frequency = X x [NDiv(9:)+8] / CPU N Div1 RW X [MDiv(5:)+2] Bit - CPU N Div RW X SMBus Table: CPU Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 1 PWD CPU SSP7 RW X CPU SSP6 RW X CPU SSP5 RW X These Spread Spectrum bits in CPU SSP4 Spread Spectrum Programming RW X Byte 13 and 14 will program Bit 3 - CPU SSP3 bit(7:) RW the spread pecentage of CPU X CPU SSP2 RW X CPU SSP1 RW X Bit - CPU SSP RW X SMBus Table: CPU Spread Spectrum Control Register Byte 14 Pin # Name Control Function Type 1 PWD Reserved CPU SSP14 RW X CPU SSP13 RW X CPU SSP12 RW These Spread Spectrum bits in X Spread Spectrum Programming Bit 3 - CPU SSP11 RW Byte 13 and 14 will program X bit(14:8) CPU SSP1 RW the spread pecentage of CPU X CPU SSP9 RW X Bit - CPU SSP8 RW X 15

16 SMBus Table: SRC Frequency Control Register Byte 15 Pin # Name Control Function Type 1 PWD SRC N Div8 N Divider Prog bit 8 RW X The decimal representation of SRC N Div9 N Divider Prog bit 9 RW X M and N Divider in Byte 15 and SRC M Div5 RW 16 will configure the SRC VCO X SRC M Div4 RW frequency. Default at power X Bit 3 - SRC M Div3 RW up = latch-in or Byte Rom X M Divider Programming bits SRC M Div2 RW table. VCO Frequency = X x [NDiv(9:)+8] / SRC M Div1 RW X [MDiv(5:)+2] Bit - SRC M Div RW X SMBus Table: SRC Frequency Control Register Byte 16 Pin # Name Control Function Type 1 PWD SRC N Div7 RW X The decimal representation of SRC N Div6 RW X M and N Divider in Byte 15 and SRC N Div5 RW 16 will configure the SRC VCO X SRC N Div4 RW frequency. Default at power X N Divider Programming b(7:) Bit 3 - SRC N Div3 RW up = latch-in or Byte Rom X SRC N Div2 RW table. VCO Frequency = X x [NDiv(9:)+8] / SRC N Div1 RW X [MDiv(5:)+2] Bit - SRC N Div RW X SMBus Table: SRC Spread Spectrum Control Register Byte 17 Pin # Name Control Function Type 1 PWD SRC SSP7 RW X SRC SSP6 RW X SRC SSP5 RW X These Spread Spectrum bits in SRC SSP4 RW X Spread Spectrum Programming b(7:) Byte 17 and 18 will program Bit 3 - SRC SSP3 RW the spread pecentage of SRC X SRC SSP2 RW X SRC SSP1 RW X Bit - SRC SSP RW X SMBus Table: SRC Spread Spectrum Control Register Byte 18 Pin # Name Control Function Type 1 PWD Reserved Reserved R - - SRC SSP14 RW X SRC SSP13 RW X SRC SSP12 RW These Spread Spectrum bits in X Spread Spectrum Programming Bit 3 - SRC SSP11 RW Byte 17 and 18 will program X b(14:8) SRC SSP1 RW the spread pecentage of SRC X SRC SSP9 RW X Bit - SRC SSP8 RW X 16

17 SMBus Table: CPU Programmable Output Divider Register Byte 19 Pin # Name Control Function Type 1 PWD CPUDiv3 RW X CPUDiv2 RW See CPU, SRC and PCI X CPU Divider Ratio Programming Bits CPUDiv1 RW Divider Ratios Table X CPUDiv RW X Bit 3 RESERVED X Bit 2 RESERVED X Bit 1 RESERVED X Bit RESERVED X SMBus Table: SRC and PCI Programmable Output Divider Register Byte 2 Pin # Name Control Function Type 1 PWD PCIDiv3 RW X PCIDiv2 RW See CPU, SRC and PCI X PCI Divider Ratio Programming Bits PCIDiv1 RW Divider Ratios Table X PCIDiv RW X Bit 3 - SRC_Div3 RW X SRC_Div2 RW See CPU, SRC and PCI X SRC_ Divider Ratio Programming Bits SRC_Div1 RW Divider Ratios Table X Bit - SRC_Div RW X SMBusTable: Test Byte Register Byte 21 Test Test Function Type Test Result PWD Bit 7 ` ICS ONLY TEST RW Reserved Bit 6 ICS ONLY TEST RW Reserved Bit 5 ICS ONLY TEST RW Reserved Bit 4 ICS ONLY TEST RW Reserved Bit 3 ICS ONLY TEST RW Reserved Bit 2 ICS ONLY TEST RW Reserved Bit 1 ICS ONLY TEST RW Reserved Bit ICS ONLY TEST RW Reserved Note: Do NOT write to Bit 21. Erratic device operation will result! 17

18 REF Drive Strength Functionality Byte6, bit 4 Byte 1, bit 1 Byte 1, bit REF1 REF X X 1x 1x 1 1x 1x 1 1 1x 2x 1 1 2x 1x x 2x CPU, SRC and PCI Divider Ratios Div(3:) Divider

19 PD, Power Down PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down. When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is de-asserted. PD C PU CPU # S RC SRC# PCIF/PCI USB REF Note 1 Normal Normal Normal Normal 33MHz 48MHz MHz 1 Iref * 2 or Float Float Iref * 2 or Float Float Low Low Low 1 Notes: 1. Refer to SMBus Byte 4 for additional information. PD Assertion PD# should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode corresponding to the CPU or SRC clock of interest is set to '' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated. See SMBus Byte 4 for additional information. PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 1MHz SRC#, 1MHz USB, 48MHz PCI, 33MHz REF,

20 PD De-assertion The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 2mV in less than 3µs of PD deassertion. PWRDWN# Tstable <1.8mS CPU, 133MHz CPU#, 133MHz SRC, 1MHz SRC# 1MHz USB, 48MHz PCI, 33MHz REF, Tdrive_PwrDwn# <3µS, >2mV Test Clarification Table Comments Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FS_C./TEST_SEL -->3-level latched input If power-up w/ V>2.V (-.3V) then use TEST_SEL If power-up w/ V<2.V (-.3V) then use FS_C FS_B/TEST_MODE -->low Vth input TEST_MODE is a If TEST_SEL HW pin is during power-up, test mode can be invoked through B6b6. If test mode is invoked by B6b6, only B6b7 is used to select HI-Z or REF/N FS_B/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control HW FS_C/TEST FS_B/TEST _SEL _MODE HW PIN HW PIN TEST ENTRY BIT B6b6 SW REF/N or HI-Z B6b7 OUTPUT X X NORMAL 1 X HI-Z 1 X 1 REF/N 1 1 X REF/N 1 1 X 1 REF/N X 1 HI-Z X 1 1 REF/N B6b6: 1= ENTER TEST MODE, Default = (NORMAL OPERATION) B6b7: 1= REF/N, Default = (HI-Z) 2

21 INDEX AREA N 1 2 D E1 E h x 45 c α L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS a 8 8 A VARIATIONS D mm. D (inch) N MIN MAX MIN MAX A1 Reference Doc.: JEDEC Publication 95, MO-118 -C e b SEATING PLANE.1 (.4) C 21

22 INDEX AREA N 1 2 D E1 E c L 6.1 mm. Body,.5 mm. Pitch TSSOP (24 mil) (2 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A A b c D E SEE VARIATIONS 8.1 BASIC SEE VARIATIONS.319 BASIC E e.5 BASIC.2 BASIC L N SEE VARIATIONS SEE VARIATIONS α 8 8 aaa A2 e b A1 A - C - SEATING PLANE VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, MO aaa C Ordering Information Part / Order Number Shipping Packaging Package Temperature 932S41EFLF Tubes 56-pin SSOP to +7 C 932S41EFLFT Tape and Reel 56-pin SSOP to +7 C 932S41EGLF Tubes 56-pin TSSOP to +7 C 932S41EGLFT Tape and Reel 56-pin TSSOP to +7 C LF suffix to the part number denotes Pb-Free configuration, RoHS compliant. 22

23 Revision History Rev. Issue Date Description Page # 1. Updated Electrical Characterisitcs tables with typical data A 5/2/25 2. Added Notes on Termination of Single-ended outputs 5-1 B 5/18/26 1. Changed Max CPU Skew from 1ps to 5ps. 6 C 5/3/26 Updated Key Specifications: CPU output skew. 1 D 8/22/26 Updated Single-ended Output Terminations. 1 E 9/11/26 Updated SMBus. Bytes -7 to match CK41B F 6/13/27 Updated operating supply and power down current values 5 1. Updated Byte 3 table. G 8/24/29 2. Added new ordering information table

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