ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Functionality. 48-Pin SSOP

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1 ICS94802 Pentium/Pro TM System Clock Chip General Description Features Pin Configuration Block Diagram 48Pin SSOP Functionality Pentium is a trademark on Intel Corporation Rev C /26/99 SEL CPUCLK, SDRAM PCICLK () () ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

2 ICS94802 Pin Descriptions P NUMBER, 3, 0, 7, 24, 3, 37, 43 P NAME 2 REF (0:) GND TYPE OUT Reference clock Output P WR Ground (common) DESCRIPTION 4 X Crystal or reference input, has internal crystal load cap 5 X2 OUT Crystal output, has internal load cap and feedback resistor to X 6 MODE Input function selection. If Mode is HIGH, then pins 26 & 27 are ured as outputs (SDRAM7 and SDRAM6). If Mode is LOW, then, pins 26 & 27 are ured as inputs (PCI_STOP# and CPU_STOP#). 7, 5 VDD2 PWR Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V 8 PCICLK_ F O UT Free running PCI clock, not affected by PCI_STOP# 9,, 2, 3, 4, 6 PCICLK (0:5) OUT PCI clocks 8 SEL66/60# Selects 60 or 66.6 for SDRAM and CPU 9 SDAT A I 2 C data input 20 SCLK I 2 C clock input 2 VDD4 PWR Supply for 48/24A, 48/24B, nominal 3.3V 22 48/24A OUT 48/24 driver output for USB or Super I/ O 23 48/24B OUT 48/24 driver output for USB or Super I/ O 25 VDD PWR Supply for PLL core, nominal 3.3V 26 SDRAM7 O UT SDRAM clock 60/66.6 (selected) PCI_STOP# Halts PCI Bus (0:5) at logic "0" level when low 27 SDRAM6 O UT SDRAM clock 60/66.6 (selected) CPU_STOP# Halts CPU clocks at logic "0" level when low 28, 34 VDD3 PWR Supply for SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, nominal 3.3V 40 VDDL2 PWR Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal 42, 4, 39, 38 CPUCLK (0:3) OUT CPUCLK clock output, powered by VDDL2 36, 35, 33, 32, 30, 29 SDRAM (0:5) O UT SDRAMs clock at 60 or 66.6 (selected) 44 PWR_DWN# Powers down chip, active low 45 IOAPIC OUT IOAPIC clock output, (4.38) powered by VDDL 46 VDDL PWR Supply for IOAPIC, either 2.5 or 3.3V nominal 47 CPU3.32.5# 3.3 or 2.5 VDD buffer strength selection, has pullup to VDD, nominal 30K resistor. When connected to VDD, 3.3V Buffer strength is selected. When connected to GND, 2.5V Buffer strength is selected. 48 VDD PWR Supply for REF (0:), X, X2, nominal 3.3V Power Groups

3 ICS94802 PowerOn Conditions PowerOn Default Conditions LOCK C P POWERU AT CONDITION DEFAULT (0:) EF R z MH OAPIC I z MH /24 4 z MH 48 66/60# EL S E OD M # P N ESCRIPTIO D N FUNCTIO 42 4, 39, 8, 3 s PUCLK C e enable/disabl w/serial , 33, 35, 36, 26 27, 29, 30, DRAM S s SDRAM output All , 3, 4, 6, 8 9,, CICLKs P e enable/disabl w/serial , 39, 8, 3 s PUCLK C e enable/disabl w/serial 60 32, 33, 35, 36, 26 27, 29, 30, DRAM S e enable/disabl w/serial 60 2, 3, 4, 6, 8 9,, CICLKs P e enable/disabl w/serial # PCI_STOP Clocks (0:5) PCI Management, Power low when Stopped 7 2 # CPU_STOP Clocks CPU (0:5) Management, Power low when Stopped 8 F PCICLK_ for running Free Clock PCI Management Power 42 4, 39, 8, 3 s CPUCLK and Control Stop w/external CPU Clocks 66.6 enable/disable. individual serial 32, 33, 35, 36, 29 30, SDRAM individual w/serial SDRAM Clocks 66.6 enable/disable. 2, 3, 4, 6, 9, PCICLKs and control Stop w/external Clocks PCI 33.3 enable/disable. individual serial # PCI_STOP Clocks (0:5) PCI Management, Power low when Stopped 7 2 # CPU_STOP Clocks CPU (0:5) Management, Power low when Stopped 8 F PCICLK_ Power for running Free Clock PCI 30 Management 42 4, 39, 8, 3 s CPUCLK and control Stop w/external CPU Clocks 60 enable/disable. individual serial 32, 33, 35, 36, 29 30, SDRAM individual w/serial SDRAM Clocks 60 enable/disable. 2, 3, 4, 6, 9, PCICLKs and control Stop w/external Clocks PCI 30 enable/disable. individual serial

4 ICS94802 Technical Pin Function Descriptions

5 ICS94802 Technical Pin Function Descriptions

6 ICS94802 General I 2 C serial interface information Clock Generator Address (7 bits) A(6:0) & R/W# D 2(H) ACK + 8 bits dummy command code ACK + 8 bits dummy Byte count Clock Generator Address (7 bits) A(6:0) & R/W# D 3(H) ACK Byte 0 ACK Byte ACK ACK Serial Configuration Command maps B IT P# DESCRIPTION PWD 7 Reserved 0 6 Must be 0 for normal operation 0 5 In Spread Spectrum, Controls type (0=centered, =down spread) 0 4 In Spread Spectrum, Controls Spreading (0=.8% =0.6%) /24 (Frequency Select) =48, 0= /24 (Frequency Select) =48, 0=24 0 TriState 0 Spread Spectrum Enable Testmode Normal operation

7 ICS94802 Functionality Tristate CPU HI Z PCI, PCI_F HI SDRAM REF Z HI Z HI Z IOAPIC HI Z 24 Selection HI Z 48 Selection HI Z Testmode TCLK/ 2 TCLK/ 4 TCLK/ 2 TCLK TCLK TCLK/ 4 CLK/ 2 T B IT P# PWD DESCRIPTION /24 (Act/Inact) /24 (Act/Inact) 5 Reserved 4 Reserved 3 38 CPUCLK3 (Act/Inact) 2 39 CPUCLK2 (Act/Inact) 4 CPUCLK (Act/Inact) 0 42 CPUCLK0 (Act/Inact) B IT P# PWD DESCRIPTION 7 Reserved 6 8 PCICLK_F (Act/Inact) 5 6 PCICLK5 (Act/Inact) 4 4 PCICLK4 (Act/Inact) 3 3 PCICLK3 (Act/Inact) 2 2 PCICLK2 (Act/Inact) PCICLK (Act/Inact) 0 9 PCICLK0 (Act/Inact) B IT P# PWD DESCRIPTION 7 26 SDRAM7 (Act/Inact) 6 27 SDRAM6 (Act/Inact) 5 29 SDRAM5 (Act/Inact) 4 30 SDRAM4 (Act/Inact) 3 32 SDRAM3 (Act/Inact) 2 33 SDRAM2 (Act/Inact) 35 SDRAM(Act/Inact) 0 36 SDRAM0 (Act/Inact) B IT P# PWD DESCRIPTION 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved Reserved 0 Reserved

8 ICS94802 B IT P# PWD DESCRIPTION 7 Reserved 6 Reserved 5 Reserved 4 45 IOAPIC0 (Act/Inact) 3 Reserved 2 Reserved REF (Act/Inact) 0 2 REF0 (Act/Inact) B IT P# PWD DESCRIPTION 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved Reserved 0 Reserved Power Management C PU_STOP# P CI_STOP# PWR_DWN# CPUCLK X X 0 Low 0 0 Low 0 Low 0 6.6/60 6.6/60 PCICLK Other Clocks, SDRAM, REF, IOAPICs, 48/24 A 48/24 B Stopped Crystal Low Low 6 Low 33.3/ /30 Off VCOs Off SIGNAL SIGNAL STAT E Latency No. of rising edges of free running PCICLK C PU_ STOP# 2 0 (Disabled) (Enabled) P CI_STOP# 2 0 (Disabled) (Enabled) P WR_DWN# 3 (Normal Operation) 3mS 4 0 (Power Down) 2max

9 ICS94802 CPU_STOP# Timing Diagram PCI_STOP# Timing Diagram

10 ICS94802 PD# Timing Diagram

11 ICS94802 Absolute Maximum Ratings Electrical Characteristics Input/Supply/Common Output Parameters TA = 0 70C; Supply Voltage VDD = VDDL = 3.3 V +/5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Input High Voltage VIH 2 VDD+0.3 V Input Low Voltage VIL VSS V Input High Current IIH V = VDD 0. 5 µa Input Low Current IIL V = 0 V; Inputs with no pullup resistors µa Input Low Current IIL2 V = 0 V; Inputs with pullup resistors µa Operating IDD3.3OP CL = 0 pf; 66M ma Supply Current Power Down IDD3.3PD CL = 0 pf; With input address to Vdd or GND µa Supply Current Input frequency Fi VDD = 3.3 V; 4.38 Input Capacitance C Logic Inputs 5 pf CX X & X2 pins ps Transition Time Ttrans To st crossing of target Freq. 3 ms Settling Time Ts From st crossing to % target Freq. ms Clk Stabilization TSTAB From VDD = 3.3 V to % target Freq. 3 ms Skew TCPUSDRAM VT =.5 V ps TCPUPCI VT =.5 V; ns Guaranteed by design, not 00% tested in production. Electrical Characteristics Input/Supply/Common Output Parameters TA = 0 70C; Supply Voltage VDD = 3.3 V +/5%, VDDL = 2.5 V +/5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Operating IDD2.5OP CL = 0 pf; 66M 5 20 ma Supply Current Power Down IDD2.5PD CL = 0 pf; µa Supply Current Skew TCPUSDRAM2 VT =.5 V; VTL =.25 V; SDRAM Leads ps TCPUPCI2 VT =.5 V; VTL =.25 V; CPU Leads ns Guaranteed by design, not 00% tested in production.

12 ICS94802 Electrical Characteristics CPU TA = 0 70C; VDD = VDDL = 3.3 V +/5%; CL = 0 20 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Output Frequency FO Output Impedance RDSP2A VO = VDD*(0.5) 0 20 Ω Output Impedance RDSN2A VO = VDD*(0.5) 0 20 Ω Output High Voltage VOH2A IOH = 28 ma V Output Low Voltage VOL2A IOL = 27 ma V Output High Current IOH2A VOH = 2.0 V ma Output Low Current IOL2A VOL = 0.8 V ma Rise Time tr2a VOL = 0.4 V, VOH = 2.4 V ns Fall Time tf2a VOH = 2.4 V, VOL = 0.4 V ns Duty Cycle dt2a VT =.5 V % Skew tsk2a VT =.5 V ps tjcyccyc2a VT =.5 V ps Jitter tjs2a VT =.5 V ps tjabs2a VT =.5 V ps Guaranteed by design, not 00% tested in production. Electrical Characteristics CPU TA = 0 70C; VDD = 3.3 V +/5%, VDDL = 2.5 V +/5%; CL = 0 20 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Output Frequency FO Output Impedance RDSP2B VO = VDD*(0.5) 0 25 Ω Output Impedance RDSN2B VO = VDD*(0.5) 0 25 Ω Output High Voltage VOH2B IOH = 3.0 ma V Output Low Voltage VOL2B IOL = 4 ma V Output High Current IOH2B VOH =.7 V 20 6 ma Output Low Current IOL2B VOL = 0.7 V ma Rise Time tr2b VOL = 0.4 V, VOH = 2.0 V.42.6 ns Fall Time tf2b VOH = 2.0 V, VOL = 0.4 V ns Duty Cycle dt2b VT =.25 V ns Skew tsk2b VT =.25 V ps tjcyccyc2b VT =.25 V ps Jitter tjs2b VT =.25 V ps tjabs2b VT =.25 V ps Guaranteed by design, not 00% tested in production.

13 ICS94802 Electrical Characteristics PCI TA = 0 70C; VDD = VDDL = 3.3 V +/5%; CL = 30 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Output Frequency FO Output Impedance RDSP VO = VDD*(0.5) 2 55 Ω Output Impedance RDSN VO = VDD*(0.5) 2 55 Ω Output High Voltage VOH IOH = 4.5 ma V Output Low Voltage VOL IOL = 9.4 ma V Output High Current IOH VOH = 2.0 V ma Output Low Current IOL VOL = 0.8 V ma Rise Time tr VOL = 0.4 V, VOH = 2.4 V.5 2 ns Fall Time tf VOH = 2.4 V, VOL = 0.4 V. 2 ns Duty Cycle dt VT =.5 V % Skew tsk VT =.5 V ps Jitter tjs VT =.5 V ps tjabs VT =.5 V ps Guaranteed by design, not 00% tested in production. Electrical Characteristics SDRAM TA = 0 70C; VDD = VDDL = 3.3 V +/5%; CL = pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Output Frequency FO Output Impedance RDSP3 VO = VDD*(0.5) 0 24 Ω Output Impedance RDSN3 VO = VDD*(0.5) 0 24 Ω Output High Voltage VOH3 IOH = 24 ma V Output Low Voltage VOL3 IOL = 23 ma V Output High Current IOH3 VOH = 2.0 V ma Output Low Current IOL3 VOL = 0.8 V ma Rise Time Tr3 VOL = 0.4 V, VOH = 2.4 V.45.7 ns Fall Time Tf3 VOH = 2.4 V, VOL = 0.4 V.2.5 ns Duty Cycle Dt3 VT =.5 V % Skew Tsk3 VT =.5 V ps Jitter Tjs3 VT =.5 V ps Tjabs3 VT =.5 V ps Guaranteed by design, not 00% tested in production.

14 ICS94802 Electrical Characteristics REF0 TA = 0 70C; VDD = VDDL = 3.3 V +/5%; CL = pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Output Frequency FO Output Impedance RDSP7 VO = VDD*(0.5) 0 24 Ω Output Impedance RDSN7 VO = VDD*(0.5) 0 24 Ω Output High Voltage VOH7 IOH = 24 ma V Output Low Voltage VOL7 IOL = 23 ma V Output High Current IOH7 VOH = 2.0 V ma Output Low Current IOL7 VOL = 0.8 V ma Rise Time Tr7 VOL = 0.4 V, VOH = 2.4 V.8 2 ns Fall Time Tf7 VOH = 2.4 V, VOL = 0.4 V.4 2 ns Duty Cycle Dt7 VT =.5 V % Jitter Tjs7 VT =.5 V ps Tjabs7 VT =.5 V ps Guarenteed by design, not 00% tested in production. Electrical Characteristics 24M, 48M, REF TA = 0 70C; VDD = VDDL = 3.3 V +/5%; CL = 0 20 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS M TYP MAX UNITS Output Frequency FO24M 24 Output Frequency FO48M 48 Output Frequency FOREF 4.38 Output Impedance RDSP5 VO = VDD*(0.5) Ω Output Impedance RDSN5 VO = VDD*(0.5) Ω Output High Voltage VOH5 IOH = 6 ma V Output Low Voltage VOL5 IOL = 9 ma V Output High Current IOH5 VOH = 2.0 V ma Output Low Current IOL5 VOL = 0.8 V 6 25 ma Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V.8 4 ns Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V.7 4 ns Duty Cycle dt5 VT =.5 V % Jitter tjs5a VT =.5 V; Fixed Clocks ps tjs5b VT =.5 V; Ref Clocks tjabs5a VT =.5 V; Fixed Clocks tjabs5b VT =.5 V; Ref Clocks ps Guarenteed by design, not 00% tested in production.

15 ICS94802

16 ICS94802 Ordering Information ICS948F02 ICS XXXX F PPP SSOP Package SYMBOL COMMON DIMENSIONS VARIATIONS D N M. N OM. M AX. M. N OM. MAX. A AC A AD A B C D See Variations E e BSC H h L N See Variations X ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Power Groups. Ground Groups. 28 pin SOIC and SSOP

ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Power Groups. Ground Groups. 28 pin SOIC and SSOP Integrated Circuit Systems, Inc. ICS948-60 Pentium/Pro TM System Clock Chip General Description The ICS948-60 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style