Programmable Timing Control Hub for P4
|
|
- Naomi Carter
- 5 years ago
- Views:
Transcription
1 ICS9598 Programmable Timing Control Hub for P4 Recommended Application: VIA Pro266/PN266/CLE266/CM4 chipset for PIII/Tualatin/C3 Processor Output Features: - Pair of differential CPU 3.3V (CK48)/ - Pair of differential open drain CPU clocks (K7) 2 - Push pull CPUT_CS 2.5V V V - 3.3V fixed - 3.3V V, 4.38MHz Key Specifications: CPU_CS - CPUT/C: <±25ps CPU_CS - AGP: <±25ps CPU - DDR/SD: <±25ps PCI - PCI: <5ps Features/Benefits: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/write operations. Uses external 4.38MHz crystal. Frequency Table FS3 FS2 FS FS MULTISEL Board Target Trace/Term Z 5 ohms 5 ohms CPUCLK MHz Reference R, Iref = /(3*Rr V D D ) Rr = 22 %, Iref = 5.mA Rr = 475 %, Iref = 2.32mA AGP MHz Output Current PCICLK MHz Z Ioh = 4* I 5 Ioh = 6* I 5 *FS/REF GND VDDAGP 5 *MODE/AGPCLK 6 *SEL_48/K7/AGPCLK 7 *(PCI_STOP#)AGPCLK2 8 GNDAGP 9 **FS/PCICLK_F **SEL_SDR/DDR#/PCICLK *MULTSEL/PCICLK2 2 GNDPCI 3 PCICLK3 4 PCICLK4 5 VDDPCI 6 PCICLK5 7 *(CLK_STOP#)/PCICLK6 8 GND48 9 *FS3/48MHz 2 *FS2/24_48MHz 2 AVDD48 22 VDD 23 GND 24 IREF 25 *(PD#)RESET# 26 SCLK 27 SDATA 28 Pin Configuration ICS Vtt_PWRGD#**/REF 55 VDDREF 54 GND 53 CPUCLKT/CPUCLKODT 52 CPUCLKC/CPUCLKODC 5 VDDCPU3.3 5 VDDCPU CPUT_CS 48 CPUT_CS 47 GND 46 FBOUT 45 BUF_IN 44 DDRT/SDRAM 43 DDRC/SDRAM 42 DDRT/SDRAM2 4 DDRC/SDRAM3 4 VDD3.3_ GND 38 DDRT2/SDRAM4 37 DDRC2/SDRAM5 36 DDRT3/SDRAM6 35 DDRC3/SDRAM7 34 VDD3.3_ GND 32 DDRT4/SDRAM8 3 DDRC4/SDRAM9 3 DDRT5/SDRAM 29 DDRC5/SDRAM * Internal 2K pull-up resistor to VDD. ** Internal 2K pull-down resistor to GND. 56-Pin 3-mil SSOP 653A 7/26/4 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
2 ICS9598 General The ICS9598 is a single chip clock solution for desktop designs using the VIA Pro266/PN266/CLE266/CM4 chipset with PC33 or DDR memory. The ICS9598 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to.mhz increment. Block Diagram (:) FBOUT Mode SEL_SDR/DDR# BUF_IN SEL_48/K7# Power Groups Pin Number VDD GND 55 2 tal, Ref 5 9 AGP [:2], CPU digital, CPU PLL 6 3 PCI [:5], PCI_F outputs MHz, Fix Digital, Fix Analog Master clock, CPU Analog 34, 4 33, 39 DDR/SDR outputs V CPUT_CS output V CPUT/C & CPUOD_T/C 653A 7/26/4 2
3 ICS9598 Pin PIN PIN PIN # NAME TYPE DESCRIPTION *FS/REF I/O Frequency select latch input pin / 4.38 MHz reference clock. 2 GND PWR Ground pin. 3 IN Crystal input, Nominally 4.38MHz. 4 2 OUT Crystal output, Nominally 4.38MHz 5 VDDAGP PWR Power supply for AGP clocks, nominal 3.3V 6 *MODE/AGPCLK I/O Function select latch input pin, =Desktop Mode, =Mobile Mode / AGP clock output. 7 *SEL_48/K7/AGPCLK I/O CPU output type select latch input pin = K7, = CK48 / AGP clock output. 8 *(PCI_STOP#)AGPCLK2 I/O Stops all PCICLKs besides the PCICLK_F clocks at logic level, when input low. This input is activated by the MODE selection pin / AGP clock output. 9 GNDAGP PWR Ground pin for the AGP outputs **FS/PCICLK_F I/O Frequency select latch input pin / 3.3V PCI free running clock output. **SEL_SDR/DDR#/PCICLK I/O Memory type select latch input pin = DDR, = PC33 SDRAM / 3.3V PCI clock output. 2 *MULTSEL/PCICLK2 I/O 3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock output. 3 GNDPCI PWR Ground pin for the PCI outputs 4 PCICLK3 OUT PCI clock output. 5 PCICLK4 OUT PCI clock output. 6 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 7 PCICLK5 OUT PCI clock output. 8 *(CLK_STOP#)/PCICLK6 I/O Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic level, when input low. This input is activated by the MODE selection pin / PCI clock output. 9 GND48 PWR Ground pin for the 48MHz outputs 2 *FS3/48MHz I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 2 *FS2/24_48MHz I/O Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V. 22 AVDD48 PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V 23 VDD PWR Power supply, nominal 3.3V 24 GND PWR Ground pin. 25 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 26 *(PD#)RESET# I/O Asynchronous active low input pin used to power down the device into a low power state. This input is activated by the MODE selection pin / Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 27 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 28 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2 drive strength Pin description continued on next page. 653A 7/26/4 3
4 ICS9598 Pin Continued PIN PIN PIN # NAME TYPE DESCRIPTION 29 DDRC5/SDRAM OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 3 DDRT5/SDRAM OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 3 DDRC4/SDRAM9 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 32 DDRT4/SDRAM8 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 33 GND PWR Ground pin. 34 VDD3.3_2.5 PWR 2.5V or 3.3V nominal power supply voltage. 35 DDRC3/SDRAM7 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 36 DDRT3/SDRAM6 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 37 DDRC2/SDRAM5 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 38 DDRT2/SDRAM4 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 39 GND PWR Ground pin. 4 VDD3.3_2.5 PWR 2.5V or 3.3V nominal power supply voltage. 4 DDRC/SDRAM3 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 42 DDRT/SDRAM2 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 43 DDRC/SDRAM OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 44 DDRT/SDRAM OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 45 BUF_IN IN Input Buffers for memory outputs. 46 FBOUT OUT Memory feed back output. 47 GND PWR Ground pin. 48 CPUT_CS OUT True clock of differential pair 2.5V push-pull CPU outputs. 49 CPUT_CS OUT True clock of differential pair 2.5V push-pull CPU outputs. 5 VDDCPU2.5 PWR Power pin for the CPUCLKs. 2.5V 5 VDDCPU3.3 PWR Power pin for the CPUCLKs. 3.3V 52 CPUCLKC/CPUCLKODC OUT "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias / "Complementary" clocks of differential pair CPU outputs. These open drain outputs need an external.5v pull-up / 2.5V CPU clock output. 53 CPUCLKT/CPUCLKODT OUT "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias / "True" clocks of differential pair CPU outputs. These open drain outputs need an external.5v pull-up / 2.5V CPU clock output. 54 GND PWR Ground pin. 55 VDDREF PWR Ref, TAL power supply, nominal 3.3V 56 Vtt_PWRGD#**/REF I/O This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. / 4.38 MHz reference clock. Mode Pin - Power Management Input Control MODE, Pin 6 (Latched Input) Pin 26 Pin 8 Pin 8 PD# (Input) RESET# (Output) CPU_STOP# (Input) PCICLK5 (Output) PCI_STOP# (Input) AGP2 (Output) 653A 7/26/4 4
5 ICS9598 General I 2 C serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) ACK ACK ACK ACK ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address D3 (H) RD ReaD ACK Data Byte Count = ACK Beginning Byte N ACK Byte N P Not acknowledge stop bit Byte N + - *See notes on the following page. 653A 7/26/4 5
6 ICS9598 Byte : Functionality and frequency select register (Default=) (2,7:4) CPUCLK AGPCLK PCICLK FS3 FS2 FS FS MHz MHz MHz Spread % /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.5% Center Spread /-.5% Center Spread /-.5% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread /-.3% Center Spread to -.6% Down Spread to -.6% Down Spread to -.6% Down Spread to -.6% Down Spread - Frequency is selected by hardware select, latched inputs - Frequency is selected by 2,7:4 - Normal - Spread spectrum enable - Running - Tristate all outputs Notes, 2 Notes:. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bb2 default =. 653A 7/26/4 6
7 ICS9598 Byte : CPU Active/Inactive Register ( = enable, = disable) B it Pin# 7 29 SDRAM/DDRC5 (Active/Inactive ) 6 PCICLK_F (Active/Inactive ) 5 3 SDRAM/DDRT5 (Active/Inactive ) 4 3 SDRAM9/DDRC4 (Active/Inactive ) 3 49 CPUT_CS Free running control; = free running; = not free runnin g 2 32 SDRAM8/DDRT4 (Active/Inactive ) 53, 52 CPUCLKT/C (Active/Inactive ) 48 CPUCLKT_CS (Active/Inactive ) Byte 2: PCI Active/Inactive Register ( = enable, = disable) B it Pin# 7 46 FB_OUT Free running control; = free running; = not free runnin g 6 8 PCICLK5 (Active/Inactive ) 5 7 PCICLK4 (Active/Inactive ) 4 5 PCICLK3 (Active/Inactive ) 3 4 PCICLK2 (Active/Inactive ) 2 2 PCICLK (Active/Inactive ) PCICLK (Active/Inactive ) 53, 52 CPUCLKT/C Free running control; = free running; = not free runnin g Byte 3: Active/Inactive Register ( = enable, = disable) B it Pin# 7 46 F B_OUT (Active/Inactive ) 6 - SEL 24_48, =24Mhz =48MHz 5 - SD/DDR free running control; = free running; not free runnin g 4 56 R EF (Active/Inactive ) 3 48 CPUT_CS free running control; = free running; not free runnin g 2 8 A GPCLK 2 (Active/Inactive ) 7 AGPCLK (Active/Inactive ) 6 A GPCLK (Active/Inactive ) Byte 4: Frequency Select Active/Inactive Register ( = enable, = disable) B it Pin# 7 - Latched FS3 6 - Latched FS2 5 - Latched FS 4 - Latched FS MHz (Active/Inactive ) _48MHz (Active/Inactive ) 49 CPUT_CS (Active/Inactive ) REF (Active/Inactive ) 653A 7/26/4 7
8 ICS9598 Byte 5: Peripheral Active/Inactive Register ( = enable, = disable) B it Pin# 7 35 SDRAM7/DDRC3 (Active/Inactive ) 6 36 SDRAM6/DDRT3 (Active/Inactive ) 5 37 SDRAM5/DDRC2 (Active/Inactive ) 4 38 SDRAM4/DDRT2 (Active/Inactive ) 3 4 SDRAM3/DDRC (Active/Inactive ) 2 42 SDRAM2/DDRT (Active/Inactive ) 43 SDRAM/DDRC (Active/Inactive ) 44 SDRAM/DDRT (Active/Inactive ) Byte 6: Vendor ID Register ( = enable, = disable) 7 Revision ID 3 6 Revision ID 2 5 Revision ID 4 Revision ID 3 Vendor ID 3 (Reserved ) 2 Vendor ID 2 (Reserved ) Vendor ID (Reserved ) Vendor ID (Reserved ) Revision ID values will be based on individual device's revision Byte 7: Revision ID and Device ID Register 7 Device ID7 6 Device ID6 5 Device ID5 4 Device ID4 3 Device ID3 2 Device ID2 Device ID Device ID Device ID values will "h" in this case. be based on individual device Byte 8: Byte Count Read Back Register 7 Byte7 6 Byte6 5 Byte5 4 Byte4 3 Byte3 2 Byte2 Byte Byte Note: Writing to this register will configure byte count and how many bytes will be read back, default is F H = 5 bytes. 653A 7/26/4 8
9 ICS9598 Byte 9: Watchdog Timer Count Register 7 WD7 6 WD6 5 WD5 4 WD4 3 WD3 2 WD2 WD WD The decimal representation of these 8 bits correspond to 29ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 6 29ms = 4.6 seconds. Byte : Programming Enable bit 8 Watchdog Control Register 7 Programming Enable bit Program = no programming. Frequencies are selected by HW latches or Byte Enable 2 = enable all I C programing. 6 WD Enable Software Watchdog Enable bit. This bit will over write WDEN latched value. = disable, = Enable. 5 WD Alarm Watchdog Alarm Status = normal = alarm status 4 SF4 3 SF3 Watchdog safe frequency bits. Writing to these bits will configure the safe 2 SF2 frequency corrsponding to Byte 2, 7:4 table SF SF Byte : VCO Frequency M Divider (Reference divider) Control Register 7 Ndiv 8 N divider bit 8 6 Mdiv 6 5 Mdiv 5 4 Mdiv 4 The decimal respresentation of Mdiv (6:) corresposd to the 3 Mdiv 3 reference divider value. Default at power up is equal to the 2 Mdiv 2 latched inputs selection. Mdiv Mdiv Byte 2: VCO Frequency N Divider (VCO divider) Control Register 7 Ndiv 7 6 Ndiv 6 5 Ndiv 5 4 Ndiv 4 3 Ndiv 3 2 Ndiv 2 Ndiv Ndiv The decimal representation of Ndiv (8:) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte. 653A 7/26/4 9
10 ICS9598 Byte 3: Spread Spectrum Control Register 7 SS 7 6 SS 6 5 SS 5 4 SS 4 3 SS 3 2 SS 2 SS SS The Spread Spectrum (2:) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider. Byte 4: Spread Spectrum Control Register 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 SS 2 Spread Spectrum 2 3 SS Spread Spectrum 2 SS Spread Spectrum SS 9 Spread Spectrum 9 SS 8 Spread Spectrum 8 Byte 5: Output Divider Control Register 7 CPU Div 3 6 CPU Div 2 5 CPU Div 4 CPU Div 3 CPU Div 3 2 CPU Div 2 CPU Div CPU Div CPUCLKC/T clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. CPUCLKT_CS clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. Byte 6: Output Divider Control Register 7 AGP Div 3 6 AGP Div 2 5 AGP Div 4 AGP Div 3 Reserved - 2 Reserved - Reserved - Reserved - AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. Reserved 653A 7/26/4
11 ICS9598 Byte 7: Output Divider Control Register 7 AGP_INV AGP Phase Inversion bit 6 Reserved Reserved 5 CPU_INV CPU T/C Phase Inversion bit 4 CPU_INV CPUT/C_CS Phase Inversion bit 3 PCI Div 3 2 PCI Div 2 PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. PCI Div Default at power up is latched FS divider. PCI Div Table Table 2 Div (3:2) Div (:) / 2 / 4 / 8 /6 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 7 / 4 / 28 /56 Div (3:2) Div (:) / 4 / 8 / 6 /32 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 9 / 8 / 36 /72 Byte 8: Group Skew Control Register 7 CPUCLKT_CS These 2 bits delay the CPUCLKT/C_CS with respect to Group Skew CPUCLKT_CS 6 Control = ps = 25ps = 5ps =75ps 5 CPUCLKT/ C hese 2 bits delay the CPUCLKT/ C clock with respect to Group Skew CPUCLKT/C_CS 4 Control = ps = 25ps = 5ps = 75ps 3 AGPCLK These 2 bits delay the AGPCLK clocks with respect to CPUCLK Group Skew 2 = ps = 25ps = 5ps = 75ps Control Reserved Reserved Reserved Reserved Byte 9: Group Skew Control Register 7 6 Reserved 5 Reserved 4 3 PCICLK(5:) These 4 bits can change the CPU to PCI (5:) skew from.4ns ns. Default at power up is - 2.5ns. Each binary increment or Group Skew decrement of s (3:) will increase or decrease the delay of the Control PCI clocks by ps. 653A 7/26/4
12 ICS9598 Byte 2: Group Skew Control Register 7 These 4 bits can change the CPU to PCIF skew from.4ns - PCICLK_F 6 2.9ns. Default at power up is - 2.5ns. Each binary increment or Group Skew 5 decrement of (3:) will increase or decrease the delay of the Control 4 PCI clocks by ps. 3 2 Reserved Reserved Byte 2: Slew Rate Control Register 7 6 Reserved 5 Reserved 4 3 CPUCLKT/ C CPUCLKT/C OD/CS clock slew rate control bits. 2 OD/CS = strong: = normal; = weak AGP_ AGP_ clock slew rate control bits. Slew Rate Control = strong: = normal; = weak Byte 22: Slew Rate Control Register B it 7 AGP(2:) AGP(2:) clock slew rate control bits. 6 Slew Rate Control = strong: = normal; = weak 5 PCICLK_ F PCICLK_F clock slew rate control bits. 4 Slew Rate Control = strong: = normal; = weak B it 3 PCICLK(7:4 ) PCICLK(7:4) clock slew rate control bits. 2 Slew Rate Control = strong: = normal; = weak B it PCICLK(3: ) PCICLK(3:) clock slew rate control bits. Slew Rate Control = strong: = normal; = weak Byte 23: Slew Rate Control Register B it 7 REF (:) REF clock slew rate control bits. 6 Slew Rate Control = strong: = normal; = weak 5 Reserved 4 Reserved 3 48MHz 48MHz clock slew rate control bits. 2 Slew Rate Control = strong: = normal; = weak 24_48MHz 24_48MHz clock slew rate control bits. Slew Rate Control = strong: = normal; = weak 653A 7/26/4 2
13 ICS9598 Absolute Maximum Ratings Supply Voltage V Logic Inputs GND.5 V to V DD +.5 V Ambient Operating Temperature C to +7 C Case Temperature C Storage Temperature C to +5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Input High Voltage V IH 2 V DD +.3 V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD -5 5 ma Input Low Current I IL V IN = V; Inputs with no pull-up resistors -5 ma Input Low Current I IL2 V IN = V; Inputs with pull-up resistors -2 ma Operating C L = pf; 66M ma I DD3.3OP Supply Current C L = Full load 28 ma Power Down IREF= ma I Supply Current DD3.3PD IREF= 5mA 37 ma Input frequency F i V DD = 3.3 V; MHz Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C out Out put pin capacitance 6 pf C IN & 2 pins pf Transition Time T trans To st crossing of target Freq. 3 ms Settling Time T s From st crossing to % target Freq. 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target Freq. 3 ms Delay t PZH,t PZH output enable delay (all outputs) ns t PLZ,t PZH output disable delay (all outputs) ns Guaranteed by design, not % tested in production. 653A 7/26/4 3
14 ICS9598 Electrical Characteristics - CPUCLKC/T T A = - 7º C; V DD = 3.3 V +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Current Source Output Impedance Z O V O = V 3 W Output High Voltage V OH.7.2 V V R = 475Ω +%; IREF = 2.32mA; I OH = 6*IREF Output High Current I OH ma Rise Time t r V OL = 2%, V OH = 8% 75 7 ps Differential Crossover Voltage V Note % Duty Cycle d t V T = 5% % Skew, CPU to CPU t sk V T = 5% 5 ps Jitter, Cycle-to-cycle t jcyc-cyc V T = V 2 ps Notes: - Guaranteed by design, not % tested in production. Electrical Characteristics - CPUCLKT/C_CS T A = - 7ÜC; V DD = 2.5 V +/-5%; C L = 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH2B I OH = -2. ma 2 V Output Low Voltage V OL2B I OL = 2 ma.4 V Output High Current I OH2B V OH =.7 V -9 ma Output Low Current I OL2B V OL =.7 V 9 ma Rise Time t r2b V OL =.4 V, V OH = 2. V.6 ns Differential Crossover Voltage V Note % Duty Cycle d t2b V T =.25 V % Skew t sk2b V T =.25 V 75 ps Jitter, Cycle-to-cycle t jcyc-cyc2b V T =.25 V 25 ps Jitter, One Sigma t js2b V T =.25 V 5 ps Jitter, Absolute t jabs2b V T =.25 V ps Guaranteed by design, not % tested in production. 653A 7/26/4 4
15 ICS9598 Electrical Characteristics - SDRAM T A = - 7 C; V DD = 3.3V +/-5%, V DDL = 2.5V +/-5%; C L = 3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH3 I OH = -28 ma 2.4 V Output Low Voltage V OL3 I OL = 2 ma.4 V Output High Current I OH3 V OH = 2. V -4 ma Output Low Current I OL3 V OL =.8 V 4 ma Rise Time t r3 V OL =.4 V, V OH = 2.4 V 2 ns Fall Time t f3 V OH = 2.4 V, V OL =.4 V 2 ns Duty Cycle d t3 V T =.5 V % Skew window t sk3 V T =.5 V 25 ps Propagation Time (Buffer In to Output) Tprop V T =.5 V 5 ns Guaranteed by design, not % tested in production. Electrical Characteristics - DDRT/C T A = - 7 C; V DDL = 2.5 V +/-5%, C L = 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH3 I OH = - ma 2 V Output Low Voltage V OL3 I OL = ma.4 V Output High Current I OH3 V OH = 2. V -2 ma Output Low Current I OL3 V OL =.8 V 2 ma Rise Time T r3 2% to 8% 2.2 ns Fall Time T f3 8% to 2% 2.2 ns Duty Cycle D t3 V T = 5% % Skew (window) T sk VT = 5% 25 ps Jitter t jcyc-cyc V T =.25 V 25 ps 653A 7/26/4 5
16 ICS9598 Electrical Characteristics - PCICLK T A = - 7 C; V DD = 3.3 V +/-5%; C L = -3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F MHz Output Impedance R DSN V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA= ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 5 ps Jitter t jcyc-cyc V T =.5 V 25 ps Guaranteed by design, not % tested in production. Electrical Characteristics - AGP T A = - 7 C; V DD = 3.3 V +/-5%; C L =-3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA= ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 5 ps Jitter tjcyc-cyc V T =.5 V 25 ps Guaranteed by design, not % tested in production. 653A 7/26/4 6
17 ICS9598 Electrical Characteristics - 48MHz T A = - 7 C; V DD = 3.3 V +/-5%; C L = -3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O V O = V DD *(.5) 48 MHz Output Impedance R DSN V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA= ma 48DOT Rise Time t r V OL =.4 V, V OH = 2.4 V.5 ns 48DOT Fall Time t f V OH = 2.4 V, V OL =.4 V.5 ns VCH 48 USB Rise Time t r V OL =.4 V, V OH = 2.4 V 2 ns VCH 48 USB Fall Time tf V OH = 2.4 V, V OL =.4 V 2 ns 48 DOT to 48 USB Skew tskew VT=.5V ns Duty Cycle d t V T =.5 V % Jitter t jcyc-cyc V T =.5 V 35 ps Guaranteed by design, not % tested in production. Electrical Characteristics - REF T A = - 7 C; V DD = 3.3 V +/-5%; C L =-2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) 2 6 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA= ma Rise Time t r V OL =.4 V, V OH = 2.4 V 4 ns Fall Time t f V OH = 2.4 V, V OL =.4 V 4 ns Duty Cycle d t V T =.5 V % Jitter t jcyc-cyc V T =.5 V 5 ps Guaranteed by design, not % tested in production. 653A 7/26/4 7
18 ICS9598 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 653A 7/26/4 8
19 ICS9598 Power Down Waveform ns 25ns 5ns VCO Internal 2 CPU MHz 3.3V 66MHz PCI 33MHz APIC 6.7MHz PD# SDRAM MHz REF 4.38MHZ 48MHZ Note. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for MHz 653A 7/26/4 9
20 ICS9598 ns ns 2ns 3ns 4ns Cycle Repeats CPU 66MHz CPU MHz CPU 33MHz SDRAM MHz SDRAM 33MHz 3.5V 66MHz PCI 33MHz APIC 6.7MHz REF 4.38MHz USB 48MHz Group Offset Waveforms 653A 7/26/4 2
21 ICS9598 INDE AREA N 2 D E A E h x 45 c L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS α 8 8 e b A -C- - SEATING PLANE. (.4) C VARIATIONS D mm. D (inch) N MIN MA MIN MA Reference Doc.: JEDEC Publication 95, MO-8-34 Ordering Information Example: 653A 7/26/4 ICS9598yFLF-T ICS y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 2
22 ICS9598 INDE AREA A2 e N 2 D b E E A A c -C- - SEATING PLANE aaa C α L 56-Lead 6. mm. Body,.5 mm. Pitch TSSOP (24 mil) (2 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A A A b c D E SEE VARIATIONS 8. BASIC SEE VARIATIONS.39 BASIC E e.5 BASIC.2 BASIC L N SEE VARIATIONS SEE VARIATIONS a 8 8 aaa VARIATIONS D mm. D (inch) N MIN MA MIN MA Reference Doc.: JEDEC Publication 95, MO Ordering Information Example: ICS9598yGLF-T ICS y G LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 653A 7/26/4 22
Programmable Timing Control Hub for P4
ICS9592 Programmable Timing Control Hub for P4 Recommended Application: VIA P4/P4M/KT/KN266/333 style chipsets. Output Features: - Pair of differential CPU clocks @ 3.3V (CK48)/ - Pair of differential
More informationProgrammable Timing Control Hub for PII/III
ICS9562 Programmable Timing Control Hub for PII/III Recommended Application: VIA Mobile PL33T and PLE33T Chipsets. Output Features: 2 - CPU clocks @ 2.5V - Pairs of differential CPU clocks @ 3.3V 7 - PCI
More informationProgrammable Timing Control Hub for PII/III
ICS9558 Programmable Timing Control Hub for PII/III Recommended Application: 8/8E/85 and 85 B-Step type chipset Output Features: 2 - CPUs @ 2.5V 3 - SDRAM @ 3.3V 3-3V66 @ 3.3V 8 - PCI @3.3V - 24/48MHz@
More informationProgrammable Timing Control Hub for P4
ICS9529 Programmable Timing Control Hub for P4 Recommended Application: CK-48 clock for Intel 845 chipset with P4 processor. Output Features: 3 - Pairs of differential CPU clocks (differential current
More informationProgrammable Frequency Generator & Integrated Buffers for Pentium III Processor VDDA *(AGPSEL)REF0 *(FS3)REF1 GND X1 X2
Integrated Circuit Systems, Inc. ICS9590 Programmable Frequency Generator & Integrated Buffers for Pentium III Processor Recommended Application: Single chip clock solution for IA platform. Output Features:
More informationFrequency Generator & Integrated Buffers for Celeron & PII/III TM *SEL24_48#/REF0 VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI
Integrated Circuit Systems, Inc. ICS9248-38 Frequency Generator & Integrated Buffers for Celeron & PII/III TM Recommended Application: 80/80E and Solano type chipset. Output Features: 2- CPUs @ 2.5V 9
More informationProgrammable Timing Control Hub TM for P4 TM
ICS9522 Programmable Timing Control Hub TM for P4 TM Recommended Application: CK-48 clock for Intel 845 chipset. Output Features: 3 - Pairs of differential CPU clocks @ 3.3V 3-3V66 @ 3.3V 9 - PCI @ 3.3V
More informationProgrammable Frequency Generator & Integrated Buffers for Pentium III Processor VDDA *(AGPSEL)REF0 *(FS3)REF1 GND X1 X2
Integrated Circuit Systems, Inc. ICS94209 Programmable Frequency Generator & Integrated Buffers for Pentium III Processor Recommended Application: Single chip clock solution 630S chipset. Output Features:
More informationFrequency Generator & Integrated Buffers for Celeron & PII/III GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1
Integrated Circuit Systems, Inc. ICS92-2 Frequency Generator & Integrated Buffers for Celeron & PII/III Recommended Application: 8/8E and Solano type chipset Output Features: 2 - CPUs @ 2.V, up to.mhz.
More informationICS AMD - K8 System Clock Chip. Integrated Circuit Systems, Inc. Pin Configuration ICS Recommended Application: AMD K8 Systems
Integrated Circuit Systems, Inc. ICS950401 AMD - K8 System Clock Chip Recommended Application: AMD K8 Systems Output Features: 2 - Differential pair push-pull CPU clocks @ 3.3V 7 - PCI (Including 1 free
More informationProgrammable Timing Control Hub for P4
ICS9522 Programmable Timing Control Hub for P4 Recommended Application: CK-48 clock for Intel 845 chipset. Output Features: 3 - Pairs of differential CPU clocks @ 3.3V 3-3V66 @ 3.3V 9 - PCI @ 3.3V 2-48MHz
More informationICS AMD-K7 TM System Clock Chip. Integrated Circuit Systems, Inc. Pin Configuration. 48-Pin SSOP & TSSOP
Integrated Circuit Systems, Inc. ICS95403 AMD-K7 TM System Clock Chip Recommended Application: ATI chipset with K7 systems Output Features: 3 differential pair open drain CPU clocks (.5V external pull-up;
More informationICS Frequency Generator & Integrated Buffers for PENTIUM/Pro TM. Integrated Circuit Systems, Inc. General Description.
Integrated Circuit Systems, Inc. ICS9248-39 Frequency Generator & Integrated Buffers for PENTIUM/Pro TM General Description The ICS9248-39 generates all clocks required for high speed RISC or CISC microprocessor
More informationFrequency Timing Generator for Transmeta Systems
Integrated Circuit Systems, Inc. ICS9248-92 Frequency Timing Generator for Transmeta Systems Recommended Application: Transmeta Output Features: CPU(2.5V or 3.3V selectable) up to 66.6MHz & overclocking
More informationFrequency Generator & Integrated Buffers for PENTIUM II III TM & K6
Integrated Circuit Systems, Inc. ICS948-195 Frequency Generator & Integrated Buffers for PENTIUM II III TM & K6 Recommended Application: 440BX, MX, VIA PM/PL/PLE 133 style chip set, with Coppermine or
More informationICS Low EMI, Spread Modulating, Clock Generator. Integrated Circuit Systems, Inc. Pin Configuration. Functionality. Block Diagram FSIN_1 FSIN_0
Integrated Circuit Systems, Inc. ICS9720 Low EMI, Spread Modulating, Clock Generator Features: ICS9720 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized
More informationFrequency Generator with 200MHz Differential CPU Clocks MHz_USB MHz_DOT 3V66_5 3V66_3 3V66_(4,2) REF CPUCLKT (2:0) 3 CPUCLKC (2:0)
Integrated Circuit Systems, Inc. ICS95080 Frequency Generator with 200MHz Differential CPU Clocks Recommended Application: CK-408 clock for BANIAS processor/ ODEM and MONTARA-G chipsets. Output Features:
More informationGeneral Purpose Frequency Timing Generator
Integrated Circuit Systems, Inc. ICS951601 General Purpose Frequency Timing Generator Recommended Application: General Purpose Clock Generator Output Features: 17 - PCI clocks selectable, either 33.33MHz
More informationICS Frequency Generator & Integrated Buffers. Integrated Circuit Systems, Inc. Pin Configuration. 48-Pin SSOP. Block Diagram.
Integrated Circuit Systems, Inc. ICS9248-28 Frequency Generator & Integrated Buffers Recommended Application: SIS 530/620 style chipset Output Features: - 3 CPU @ 2.5V/3.3V up to 33.3 MHz. - 6 PCI @ 3.3V
More informationFrequency Generator & Integrated Buffers for Celeron & PII/III
Integrated Circuit Systems, Inc. ICS950-8 Frequency Generator & Integrated Buffers for Celeron & PII/III Recommended Application: 80/80E and 85 type chipset. Output Features: CPU (.5V) (up to 33 achievable
More informationFrequency Timing Generator for Pentium II Systems
Integrated Circuit Systems, Inc. ICS9248-6 Frequency Timing Generator for Pentium II Systems General Description The ICS9248-6 is the Main clock solution for Notebook designs using the Intel 440BX style
More informationFrequency Timing Generator for PENTIUM II/III Systems
Integrated Circuit Systems, Inc. ICS9250-2 Frequency Timing Generator for PENTIUM II/III Systems General Description The ICS9250-2 is a main clock synthesizer chip for Pentium II based systems using Rambus
More informationICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Power Groups. Ground Groups. 28 pin SOIC and SSOP
Integrated Circuit Systems, Inc. ICS948-60 Pentium/Pro TM System Clock Chip General Description The ICS948-60 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style
More informationICS Frequency Generator & Integrated Buffers. General Description. Block Diagram. Pin Configuration. Power Groups.
Integrated Circuit Systems, Inc. ICS9248-8 Frequency Generator & Integrated Buffers General Description The ICS9248-8 is the single chip clock solution for Desktop/ Notebook designs using the SIS style
More informationICS Preliminary Product Preview
Integrated Circuit Systems, Inc. ICS954 AMD - K8 System Clock Chip Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset Output Features: 3 - Differential pair push-pull CPU clocks
More information932S806. Clock Chip for 2 and 4-way AMD K8-based servers 932S806. Pin Configuration
Clock Chip for 2 and 4-way AMD K8-based servers Recommended Application: Serverworks HT2100-based systems using AMD K8 processors Output Features: 6 - Pairs of AMD K8 clocks 5 - Pairs of SRC/PCI Express*
More informationICS Frequency Generator & Integrated Buffers for PENTIUM/Pro TM. Integrated Circuit Systems, Inc. General Description.
Integrated Circuit Systems, Inc. ICS9248-39 Frequency Generator & Integrated Buffers for PENTIUM/Pro TM General Description The ICS9248-39 generates all clocks required for high speed RISC or CISC microprocessor
More informationIDT Programmable Timing Control Hub TM for Next Gen P4 TM Processor ICS932S208 ICS932S208 DATASHEET. 56-pin SSOP & TSSOP
Programmable Timing Control Hub TM for Next Gen P4 TM Processor Recommended Application: CK409B clock, Intel Yellow Cover part, Server Applications Output Features: 4-0.7V current-mode differential CPU
More informationICS2510C. 3.3V Phase-Lock Loop Clock Driver. Integrated Circuit Systems, Inc. General Description. Pin Configuration.
Integrated Circuit Systems, Inc. ICS250C 3.3V Phase-Lock Loop Clock Driver General Description The ICS250C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology
More informationICS Low Skew Fan Out Buffers. Integrated Circuit Systems, Inc. General Description. Pin Configuration. Block Diagram. 28-Pin SSOP & TSSOP
Integrated Circuit Systems, Inc. ICS979-03 Low Skew Fan Out Buffers General Description The ICS979-03 generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as
More informationFrequency Generator with 200MHz Differential CPU Clocks ICS ICS DATASHEET. Block Diagram. Frequency Select.
Frequency Generator with 200MHz Differential CPU Clocks Recommended Application: CK-408 clock with Buffered/Unbuffered mode supporting Almador, Brookdale, ODEM, and Montara-G chipsets with PIII/ P4 processor.
More informationICS Pin Configuration. Features/Benefits. Specifications. Block Diagram DATASHEET LOW EMI, SPREAD MODULATING, CLOCK GENERATOR.
DATASHEET LW EMI, SPREAD MDULATING, CLCK GENERATR ICS9730 Features/Benefits ICS9730 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized clock signal
More informationICS9P935 ICS9P935. DDR I/DDR II Phase Lock Loop Zero Delay Buffer 28-SSOP/TSSOP DATASHEET. Description. Pin Configuration
DATASHEET ICS9P935 Description DDR I/DDR II Zero Delay Clock Buffer Output Features Low skew, low jitter PLL clock driver Max frequency supported = 400MHz (DDRII 800) I 2 C for functional and output control
More informationDDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9
Integrated Circuit Systems, Inc. ICS93738 DDR and SDRAM Buffer Recommended Application: DDR & SDRAM fanout buffer, for VIA P4X/KT66/333 chipsets. Product Description/Features: Low skew, fanout buffer to
More informationICS Low Cost DDR Phase Lock Loop Clock Driver. Pin Configuration. Functionality. Block Diagram. Integrated Circuit Systems, Inc.
Integrated Circuit Systems, Inc. ICS93716 Low Cost DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Product Description/Features: Low skew, low jitter PLL clock driver I 2 C for
More informationProgrammable Timing Control Hub for Next Gen P4 processor
ICS9549 Programmable Timing Control Hub for Next Gen P4 processor Recommended Application: CK4 compliant clock Output Features: 2 -.7V current-mode differential CPU pairs -.7V current-mode differential
More informationICS9P936. Low Skew Dual Bank DDR I/II Fan-out Buffer DATASHEET. Description. Pin Configuration
DATASHEET Description Dual DDR I/II fanout buffer for VIA Chipset Output Features Low skew, fanout buffer SMBus for functional and output control Single bank 1-6 differential clock distribution 1 pair
More informationICS9FG107. Programmable FTG for Differential P4 TM CPU, PCI-Express & SATA Clocks DATASHEET. Description
DATASHEET Programmable FTG for Differential P4 TM CPU, PCI-Express & SATA Clocks ICS9FG107 Description ICS9FG107 is a Frequency Timing Generator that provides 7 differential output pairs that are compliant
More informationSystem Clock Chip for ATI RS400 P4 TM -based Systems
System Clock Chip for ATI RS400 P4 TM -based Systems Recommended Application: ATI RS400 systems using Intel P4 TM processors Output Features: 6 - Pairs of SRC/PCI-Express clocks 2 - Pairs of ATIG (SRC/PCI
More informationProgrammable Timing Control Hub for Intel-based Servers
Programmable Timing Control Hub for Intel-based Servers Recommended Application: CK41B clock for Intel-based servers Output Features: 4 -.7V current-mode differential CPU pairs 5 -.7V current-mode differential
More informationICS9214. Rambus TM XDR TM Clock Generator. General Description. Pin Configuration. Block Diagram ICS9214. Integrated Circuit Systems, Inc.
Rambus TM XDR TM Clock Generator General Description The clock generator provides the necessary clock signals to support the Rambus XDR TM memory subsystem and Redwood logic interface. The clock source
More informationPI6C :8 Clock Driver for Intel PCI Express Chipsets. Description. Features. Pin Configuration. Block Diagram
Features Eight Pairs of Differential Clocks Low skew < 50ps Low Cycle-to-cycle jitter < 50ps Output Enable for all outputs Outputs Tristate control via SMBus Power Management Control Programmable PLL Bandwidth
More informationICS309 SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH. Description. Features. Block Diagram DATASHEET
DATASHEET ICS309 Description The ICS309 is a versatile serially-programmable, triple PLL with spread spectrum clock source. The ICS309 can generate any frequency from 250kHz to 200 MHz, and up to 6 different
More informationICS DIMM Buffer. Integrated Circuit Systems, Inc. General Description. Block Diagram. Pin Configuration
Integrated Circuit Systems, Inc. ICS9179-12 3 DIMM Buffer General Description The ICS9179-12 is a buffer intended for reduced pin count 2 - chip Intel BX chipset designs An I 2 C interface is included,
More informationProgrammable System Clock Chip for ATI RS400 P4 TM -based Systems
Programmable System Clock Chip for ATI RS4 P4 TM -based Systems Recommended Application: ATI RS4 systems using Intel P4 TM processors Output Features: 6 - Pairs of SRC/PCI Express* clocks 2 - Pairs of
More informationICS High Performance Communication Buffer. Integrated Circuit Systems, Inc. General Description. Block Diagram.
Integrated Circuit Systems, Inc. ICS905 High Performance Communication Buffer General Description The ICS905 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology
More informationICS Low Skew PCI / PCI-X Buffer. General Description. Block Diagram. Pin Configuration. Pin Descriptions OE CLK0
Low Skew PCI / PCI-X Buffer General Description The ICS9112-27 is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X applications
More informationPROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV126 FEATURES: One high precision PLL for CPU, SSC, and N programming One high precision PLL for SRC/PCI, SSC, and N programming One high precision PLL for
More informationMK DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER. Features. Description. Block Diagram DATASHEET
DATASHEET MK1493-05 Description The MK1493-05 is a spread-spectrum clock generator used as a companion chip with a CK410 system clock. The device is used in a PC or embedded system to substantially reduce
More informationIDT TM Programmable Timing Control Hub TM for Intel Systems ICS9E4101 DATASHEET. 56-pin SSOP
DATASHEET Recommended Application: I-temp CK41 clock, Intel Yellow Cover part Output Features: 2 -.7V current-mode differential CPU pairs 6 -.7V current-mode differential SRC pair for SATA and PCI-E 1
More informationICSSSTVA DDR 14-Bit Registered Buffer. Pin Configuration. Truth Table Pin TSSOP 6.10 mm. Body, 0.50 mm. pitch = TSSOP. Block Diagram H H H
DDR 14-Bit Registered Buffer Recommended Applications: DDR Memory Modules Provides complete DDR DIMM logic solution with ICS93857 or ICS95857 SSTL_2 compatible data registers DDR400 recommended (backward
More informationICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS180-51 Description The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology
More informationICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA
BUFFER Description The ICS552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for glitch-free switching between two clock sources. It is part
More informationWinbond Clock Generator W83195CG-NP. For Intel Napa Platform
Winbond Clock Generator For Intel Napa Platform Date: Dec./2007 Revision: 1.1 Datasheet Revision History Pages Dates Version Web Version 1 n.a. 11/01/2005 0.5 n.a. 2 n.a. 01/27/2006 1.0 1.0 3 12/20/2007
More informationICS NETWORKING AND PCI CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET Description The is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental
More information2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features
DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential
More informationICS9112A-16. Low Skew Output Buffer. General Description. Pin Configuration. Block Diagram. 8 pin SOIC, TSSOP
Low Skew Output Buffer General Description The ICS92A-6 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF
More informationFeatures VDD 1 CLK1. Output Divide PLL 2 OE0 GND VDD. IN Transition Detector CLK1 INB. Output Divide PLL 2 OE0 GND
DATASHEET ICS58-0/0 Description The ICS58-0/0 are glitch free, Phase Locked Loop (PLL) based clock multiplexers (mux) with zero delay from input to output. They each have four low skew outputs which can
More informationPCK2010RA CK98R (100/133MHz) RCC spread spectrum system clock generator
INTEGRATED CIRCUITS CK98R (100/133MHz) RCC spread spectrum Supersedes data of 2000 Dec 01 ICL03 PC Motherboard ICs; Logic Products Group 2001 Apr 02 FEATURES Mixed 2.5 V and 3.3 V operation Four CPU clocks
More information440BX AGPset Spread Spectrum Frequency Synthesizer
440BX APset Spread Spectrum Frequency Synthesizer Features Maximized electromagnetic interference (EMI) suppression using Cypress s Spread Spectrum technology Single-chip system frequency synthesizer for
More informationTRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
More informationICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS. Description. Features. Block Diagram PRELIMINARY DATASHEET
PRELIMINARY DATASHEET ICS1493-17 Description The ICS1493-17 is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device
More informationICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Functionality. 48-Pin SSOP
ICS94802 Pentium/Pro TM System Clock Chip General Description Features Pin Configuration Block Diagram 48Pin SSOP Functionality Pentium is a trademark on Intel Corporation. 94802 Rev C /26/99 SEL CPUCLK,
More informationICS OSCILLATOR, MULTIPLIER, AND BUFFER WITH 8 OUTPUTS. Description. Features (all) Features (specific) DATASHEET
DATASHEET ICS552-01 Description The ICS552-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. Unlike other clock drivers, these parts do not require a separate
More informationPCI-EXPRESS CLOCK SOURCE. Features
DATASHEET ICS557-01 Description The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.
More informationICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS180-01 Description The ICS180-01 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase Locked Loop (PLL) technology
More informationICS2304NZ-1 LOW SKEW PCI/PCI-X BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS2304NZ-1 Description The ICS2304NZ-1 is a high-performance, low skew, low jitter PCI/PCI-X clock driver. It is designed to distribute high-speed signals in PCI/PCI-X applications operating
More informationSERIALLY PROGRAMMABLE CLOCK SOURCE. Features
DATASHEET ICS307-02 Description The ICS307-02 is a versatile serially programmable clock source which takes up very little board space. It can generate any frequency from 6 to 200 MHz and have a second
More informationICS558A-02 LVHSTL TO CMOS CLOCK DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS558A-02 Description The ICS558A-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs
More informationWinbond Clock Generator W83195BR-118/W83195BG-118 For Intel 915/945 Chipsets. Date: May/02/2006 Revision: 0.81
Winbond Clock Generator W83195BR-118/W83195BG-118 For Intel 915/945 Chipsets Date: May/02/2006 Revision: 0.81 1 W83195BR-118 Datasheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS n.a.
More informationSG500. Low Jitter Spectrum Clock Generator for PowerPC Designs. Approved Product. FREQUENCY TABLE (MHz) PRODUCT FEATURES CONNECTION DIAGRAM
PRODUCT FEATURES Supports Power PC CPU s. Supports simultaneous PCI and Fast PCI Buses. Uses external buffer to reduce EMI and Jitter PCI synchronous clock. Fast PCI synchronous clock Separated 3.3 volt
More informationICS QUAD PLL CLOCK SYNTHESIZER. Description. Features. Block Diagram PRELIMINARY DATASHEET
PRELIMINARY DATASHEET ICS348-22 Description The ICS348-22 synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock
More informationMK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-01 Description The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks
More informationMK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-02 Description The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low
More informationFIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER. Features VDD PLL1 PLL2 GND
DATASHEET ICS252 Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 khz to 200 MHz using up to two independently
More informationICS LOW EMI CLOCK GENERATOR. Features. Description. Block Diagram DATASHEET
DATASHEET ICS10-52 Description The ICS10-52 generates a low EMI output clock from a clock or crystal input. The device uses ICS proprietary mix of analog and digital Phase-Locked Loop (PLL) technology
More information100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs
0 Features CY2280 100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs Mixed 2.5V and 3.3V operation Clock solution for Pentium II, and other similar processor-based
More informationICS LOW PHASE NOISE CLOCK MULTIPLIER. Features. Description. Block Diagram DATASHEET
DATASHEET ICS601-01 Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase
More informationMK AMD GEODE GX2 CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK1491-09 Description The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked
More informationICS PCI-EXPRESS CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET ICS557-0 Description The ICS557-0 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 00 MHz in a small 8-pin SOIC package.
More informationICS512 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS512 Description The ICS512 is the most cost effective way to generate a high-quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. The name
More informationLOW PHASE NOISE CLOCK MULTIPLIER. Features
DATASHEET Description The is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase noise multiplier. Using
More informationPI6C557-03B. PCIe 3.0 Clock Generator with 2 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TSSOP) Block Diagram
Features ÎÎPCIe 3.0 compliant à à PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V
More informationMK1413 MPEG AUDIO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET
DATASHEET MK1413 Description The MK1413 is the ideal way to generate clocks for MPEG audio devices in computers. The device uses IDT s proprietary mixture of analog and digital Phase-Locked Loop (PLL)
More informationICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET ICS660 Description The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses
More informationDescription. Applications. ÎÎNetworking systems ÎÎEmbedded systems ÎÎOther systems
Features ÎÎ3.3V ±10% supply voltage ÎÎ25MHz XTAL or reference clock input ÎÎFive PCIe 2.0 Compliant 100MHz selectable HCSL outputs with -0.5% spread default is spread off ÎÎTwo 25MHz LVCMOS output ÎÎIndustrial
More informationICS542 CLOCK DIVIDER. Features. Description. Block Diagram DATASHEET. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
DATASHEET ICS542 Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide
More informationLOCO PLL CLOCK MULTIPLIER. Features
DATASHEET ICS501A Description The ICS501A LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
More informationIDT9170B CLOCK SYNCHRONIZER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET IDT9170B Description The IDT9170B generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5 V VDD). Using IDT s proprietary phase-locked loop
More informationPCK MHz I 2 C differential 1:10 clock driver INTEGRATED CIRCUITS
INTEGRATED CIRCUITS 70 190 MHz I 2 C differential 1:10 clock driver Product data Supersedes data of 2001 May 09 File under Integrated Circuits, ICL03 2001 Jun 12 FEATURES Optimized for clock distribution
More informationPCK2021 CK00 (100/133 MHz) spread spectrum differential system clock generator
INTEGRATED CIRCUITS CK00 (100/133 MHz) spread spectrum differential 2001 Oct 11 File under Integrated Circuits, ICL03 CK00 (100/133 MHz) spread spectrum differential FEATURES 3.3 V operation Six differential
More informationICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS511 Description The ICS511 LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
More informationICS NETWORKING CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET Description The generates four high-quality, high-frequency clock outputs. It is designed to replace multiple crystals and crystal oscillators in networking applications. Using ICS patented Phase-Locked
More information1.8V Low-Power Wide-Range Frequency Clock Driver CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT2 CLK_INT CLK_INC CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 AGND
Integrated Circuit Systems, Inc. ICS98ULPA877A.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR2 DIMM logic solution
More informationICS502 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS502 Description The ICS502 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The
More informationLOCO PLL CLOCK MULTIPLIER. Features
DATASHEET ICS501 Description The ICS501 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
More informationICS97U2A845A Advance Information
Integrated Circuit Systems, Inc. ICS97U2A845A 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR DIMM logic solution
More informationCLOCK DISTRIBUTION CIRCUIT. Features
DATASHEET CLCK DISTRIBUTIN CIRCUIT IDT6P30006A Description The IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCX or LVCMS input and generates eight high-quality
More informationPI6C557-03AQ. PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications. Description. Features. Pin Configuration (16-Pin TSSOP)
PCIe.0 Clock Generator with HCSL Outputs for Automotive Applications Features ÎÎPCIe.0 compliant à à Phase jitter -.1ps RMS (typ) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal
More informationICS553 LOW SKEW 1 TO 4 CLOCK BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS553 Description The ICS553 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest skew, small clock buffer. See the ICS552-02 for
More information