IDT TM Programmable Timing Control Hub TM for Intel Systems ICS9E4101 DATASHEET. 56-pin SSOP

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1 DATASHEET Recommended Application: I-temp CK41 clock, Intel Yellow Cover part Output Features: 2 -.7V current-mode differential CPU pairs 6 -.7V current-mode differential SRC pair for SATA and PCI-E 1 -.7V current-mode differential CPU/SRC selectable pair 6 - PCI (33MHz) 3 - PCICLK_F, (33MHz) free-running 1 - USB, 48MHz 1 - DOT, 96MHz,.7V current differential pair 1 - REF, MHz Pin Configuration ICS9E411 Features/Benefits: Supports tight ppm accuracy clocks for Serial-ATA and PCI-Express Supports spread spectrum modulation, to -.5% down spread Supports CPU clks up to 4MHz Uses external MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, SRC pair in PD# for power management. Key Specifications: CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter <125ps PCI outputs cycle-cycle jitter < 5ps +/- 3ppm frequency accuracy on CPU & SRC clocks Functionality FS_C 1 FS_B 2 FS_A 2 CPU SRC PCI REF USB DOT MHz MHz MHz MHz MHz MHz RESERVED 1 RESERVED RESERVED RESERVED 1. FS_C is a three-level input. Please see V IL_FS and V IH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_B and FS_A are low-threshold inputs. Please see the V IL_FS and V IH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. VDDPCI 1 GND 2 PCICLK3 3 PCICLK4 4 PCICLK5 5 GND 6 VDDPCI 7 ITP_EN/PCICLK_F 8 PCICLK_F1 9 PCICLK_F2 1 VDD48 11 USB_48MHz 12 GND 13 DOTT_96MHz 14 DOTC_96MHz 15 FS_B/TEST_MODE 16 Vtt_PwrGd#/PD 17 FS_A_41 18 SRCCLKT1 19 SRCCLKC1 2 VDDSRC 21 SRCCLKT2 22 SRCCLKC2 23 SRCCLKT3 24 SRCCLKC3 25 SRCCLKT4_SATA 26 SRCCLKC4_SATA 27 VDDSRC 28 ICS9E PCICLK2 55 PCICLK1 54 PCICLK 53 FS_C/TEST_SEL 52 REFOUT 51 GND 5 X1 49 X2 48 VDDREF 47 SDATA 46 SCLK 45 GND 44 CPUCLKT 43 CPUCLKC 42 VDDCPU 41 CPUCLKT1 4 CPUCLKC1 39 IREF 38 GNDA 37 VDDA 36 CPUCLKT2_ITP/SRCCLKT_7 35 CPUCLKC2_ITP/SRCCLKC_7 34 VDDSRC 33 SRCCLKT6 32 SRCCLKC6 31 SRCCLKT5 3 SRCCLKC5 29 GND 56-pin SSOP IDT TM 148A 1/25/1 1

2 ICS9E411 Pin Description Pin # PIN NAME PIN TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK3 OUT PCI clock output. 4 PCICLK4 OUT PCI clock output. 5 PCICLK5 OUT PCI clock output. 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 8 ITP_EN/PCICLK_F I/O Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair = SRC pair 9 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP#. 1 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP#. 11 VDD48 PWR Power pin for the 48MHz output.3.3v 12 USB_48MHz OUT 48.MHz USB clock 13 GND PWR Ground pin. 14 DOTT_96MHz OUT True clock of differential pair for 96.MHz DOT clock. 15 DOTC_96MHz OUT Complement clock of differential pair for 96.MHz DOT clock. 16 FS_B/TEST_MODE IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. 17 Vtt_PwrGd#/PD IN Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 18 FS_A_41 IN 3.3V tolerant low threshold input for CPU frequency selection. This pin requires CK41 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS threshold values. 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 2 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 21 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 22 SRCCLKT2 OUT True clock of differential SRC clock pair. 23 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 26 SRCCLKT4_SATA OUT True clock of differential SRC/SATA pair. 27 SRCCLKC4_SATA OUT Complement clock of differential SRC/SATA pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal IDT TM 148A 1/25/1 2

3 ICS9E411 Pin Description (continued) Pin # PIN NAME TYPE DESCRIPTION 29 GND PWR Ground pin. 3 SRCCLKC5 OUT Complement clock of differential SRC clock pair. 31 SRCCLKT5 OUT True clock of differential SRC clock pair. 32 SRCCLKC6 OUT Complement clock of differential SRC clock pair. 33 SRCCLKT6 OUT True clock of differential SRC clock pair. 34 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 35 CPUCLKC2_ITP/SRCCLKC_7 OUT Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. 36 CPUCLKT2_ITP/SRCCLKT_7 OUT True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. 37 VDDA PWR 3.3V power for the PLL core. 38 GNDA PWR Ground pin for the PLL core. 39 IREF OUT This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 4 CPUCLKC1 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 41 CPUCLKT1 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 42 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 43 CPUCLKC OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 44 CPUCLKT OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 45 GND PWR Ground pin. 46 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 47 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 48 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 49 X2 OUT Crystal output, Nominally MHz 5 X1 IN Crystal input, Nominally MHz. 51 GND PWR Ground pin. 52 REFOUT OUT Reference Clock output 53 FS_C/TEST_SEL IN 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 54 PCICLK OUT PCI clock output. 55 PCICLK1 OUT PCI clock output. 56 PCICLK2 OUT PCI clock output. IDT TM 148A 1/25/1 3

4 ICS9E411 General Description ICS9E411 follows Intel CK41 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9E411 is driven with a MHz crystal. It generates CPU outputs up to 4MHz. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Block Diagram 48MHz, USB X1 X2 XTAL PLL2 Frequency Dividers 96MHz_DOTT_ 96MHz_DOTC_ REFOUT CPUCLKT (2:) CPUCLKC (2:) SCLK SDATA Vtt_PWRGD#/PD FS_A FS_B FS_C ITP_EN TEST_MODE TEST_SEL Control Logic Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic SRCCLKT (7:1) SRCCLKC (7:1) PCICLK (5:) PCICLKF (2:) I REF Power Groups Pin Number VDD GND Description Xtal, Ref 1,7 2,6 PCICLK outputs 21,28,34 29 SRCCLK outputs Master clock, CPU Analog DOT, USB, PLL_ CPUCLK clocks IDT TM 148A 1/25/1 4

5 ICS9E411 General I 2 C serial interface information for the ICS9E411 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit T Index Block Write Operation Controller (Host) ICS (Slave/Receiver) start bit Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD P Byte N + X - 1 stop bit X Byte X Byte Data Byte Count = X Beginning Byte N N P Not acknowledge stop bit Byte N + X - 1 IDT TM 148A 1/25/1 5

6 ICS9E411 I 2 C Table: Read-Back Register Byte Pin # Name Control Function Type 1 PWD Bit 7 35,36 CPUCLK2/RCCLK7 Enable Output Enable RW DISABLE ENABLE 1 Bit 6 32,33 SRCCLK6 Enable Output Enable RW DISABLE ENABLE 1 Bit 5 3,31 SRCCLK5 Enable Output Enable RW DISABLE ENABLE 1 Bit 4 26,27 SRCCLK4 Enable Output Enable RW DISABLE ENABLE 1 Bit 3 24,25 SRCCLK3 Enable Output Enable RW DISABLE ENABLE 1 Bit 2 22,23 SRCCLK2 Enable Output Enable RW DISABLE ENABLE 1 Bit 1 19,2 SRCCLK1 Enable Output Enable RW DISABLE ENABLE 1 Bit - RESERVED I 2 C Table: Spreading and Device Behavior Control Register Byte 1 Pin # Name Control Function Type 1 PWD Bit 7 54 PCI_F Enable Output Enable RW Disable Enable 1 Bit 6 14,15 DOT_96MHz Output Enable RW Disable Enable 1 Bit 5 12 USB_48MHz Enable Output Enable RW Disable Enable 1 Bit 4 52 REFOUT Enable Output Enable RW Disable Enable 1 Bit 3 RESERVED 1 Bit 2 4,41 CPUT1/CPUC1 Output Enable RW Disable Enable 1 Bit 1 43,44 CPUT/CPUC Output Enable RW Disable Enable 1 Bit - Spread Spectrum Mode Spread Off RW SPREAD OFF SPREAD ON I 2 C Table: Output Control Register Byte 2 Pin # Name Control Function Type 1 PWD Bit 7 5 PCICLK5 Output Enable RW Disable Enable 1 Bit 6 4 PCICLK4 Output Enable RW Disable Enable 1 Bit 5 3 PCICLK3 Output Enable RW Disable Enable 1 Bit 4 56 PCICLK2 Output Enable RW Disable Enable 1 Bit 3 55 PCICLK1 Output Enable RW Disable Enable 1 Bit 2 54 PCICLK Output Enable RW Disable Enable 1 Bit 1 1 PCI_F2 Enable Output Enable RW Disable Enable 1 Bit 9 PCI_F1 Enable Output Enable RW Disable Enable 1 I 2 C Table: Output Control Register Byte 3 Pin # Name Control Function Type 1 PWD Bit 7 35,35 CPU_ITP/SRCCLK7 RW Free-Running Stoppable Free-Running Bit 6 32,33 SRCCLK6 RW Free-Running Stoppable Control Bit 5 3,31 SRCCLK5 RW Free-Running Stoppable default: Bit 4 26,27 SRCCLK4 RW Free-Running Stoppable not affected by Bit 3 24,25 SRCCLK3 RW Free-Running Stoppable PCI/SRC_STOP Bit 2 22,23 SRCCLK2 RW Free-Running Stoppable (Byte 6, bit 3) Bit 1 19,2 SRCCLK1 RW Free-Running Stoppable Bit - RESERVED I 2 C Table: Output Control Register Byte 4 Pin # Name Control Function Type 1 PWD 1 Bit 6 14,15 DOT_96MHz Driven in PD RW Driven Hi-Z 1 Bit 5 1 PCI_F2 Free-Running RW Free-Running Stoppable 1 Bit 4 9 PCI_F1 Control RW Free-Running Stoppable 1 Bit 3 8 PCI_F not affected by RW Free-Running Stoppable 1 Bit 2 RESERVED 1 Bit 1 RESERVED 1 Bit RESERVED 1 IDT TM 148A 1/25/1 6

7 ICS9E411 I 2 C Table: Output Control Register Byte 5 Pin # Name Control Function Type 1 PWD Bit 7 19,2,22,23, Drive Mode in 24,25,26,27,3,31, SRC Stop Drive Mode PCI_Stop 32,33,35,36 RW Driven Hi-Z Bit 4 RESERVED 19,2,22,23, Bit 3 24,25,26,27,3,31, SRC PD Drive Mode Drive Mode in PD RW Driven Hi-Z 32,33,35,36 Bit 2 35,36 CPUCLK_ITP Drive Mode in PD RW Driven Hi-Z Bit 1 4,41 CPUCLK1 Drive mode in PD RW Driven Hi-Z Bit 43,44 CPUCLK Drive mode in PD RW Driven Hi-Z I 2 C Table: Output Control Register Byte 6 Pin # Name Control Function Type 1 PWD Bit 7 - Test Mode Selection Test Mode Selection RW Hi-Z REF/N Test Clock Mode Entry Test Mode RW Disable Enable RESERVED Bit 4 52 REFOUT Strength Strength Prog RW 1X 2X 1 Bit 3 17,18,19,2,22,23, Enabled, all Disabled, all 24,25,26,27,3,31, stoppable PCI Stop all PCI and stoppable PCI 32,33,35,36 PCI/SRC_STOP RW and SRC SRC clocks and SRC clocks 54,55,56,3,4,5,8,9, clocks are are running 1 stopped. 1 FS_C readback R - - LATCHED FS_B readback R - - LATCHED Bit - FS_A readback R - - LATCHED I 2 C Table: Vendor & Revision ID Register Byte 7 Pin # Name Control Function Type 1 PWD Bit 7 - RID3 R - - RID2 R - - REVISION ID RID1 R - - RID R - - VID3 R - - VID2 R - - VENDOR ID VID1 R - - Bit - VID R I 2 C Table: Byte Count Register Byte 8 Pin # Name Control Function Type 1 PWD Bit 7 - BC7 RW - - BC6 Writing to this RW - - BC5 register will RW - - BC4 configure how RW - - BC3 many bytes will be RW BC2 read back, default RW - - BC1 is 8 = 8 bytes. RW - - Bit - BC RW - - IDT TM 148A 1/25/1 7

8 ICS9E411 I 2 C Table: Watchdog Timer Register Byte 9 Pin # Name Control Function Type 1 PWD WD4 RW - - WD3 Enables RW - - WD2 prograaming bytes RW - - WD RW - - Bit - WD RW - - I 2 C Table: VCO Control Select Bit & WD Timer Control Register Byte 1 Pin # Name Control Function Type 1 PWD M/N Programming Bit 7 - M/NEN Enable RW Disable Enable WDEN Watchdog Enable R Disable Enable 1 Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit RESERVED I 2 C Table: VCO Frequency Control Register Byte 11 Pin # Name Control Function Type 1 PWD Bit 7 - N Div8 N Divider Bit 8 RW - - X M Div6 The decimal RW - - X M Div5 representation of M RW - - X M Div4 Div (6:) is equal to RW - - X M Div3 reference divider RW - - X M Div2 value. Default at RW - - X M Div1 power up = latch-in RW - - X Bit - M Div or Byte Rom RW - - X I 2 C Table: VCO Frequency Control Register Byte 12 Pin # Name Control Function Type 1 PWD Bit 7 - N Div7 RW - - X The decimal N Div6 RW - - X representation of N N Div5 RW - - X Div (8:) is equal to N Div4 RW - - X VCO divider value. N Div3 RW - - X Default at power up N Div2 RW - - X = latch-in or Byte N Div1 RW - - X Rom table. Bit - N Div RW - - X I 2 C Table: Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 1 PWD Bit 7 - SSP7 These Spread RW - - X SSP6 Spectrum bits will RW - - X SSP5 program the spread RW - - X SSP4 pecentage. It is RW - - X SSP3 recommended to RW - - X SSP2 use ICS Spread % RW - - X SSP1 table for spread RW - - X Bit - SSP programming. RW - - X IDT TM 148A 1/25/1 8

9 ICS9E411 I 2 C Table: Spread Spectrum Control Register Byte 14 Pin # Name Control Function Type 1 PWD SSP13 RW - - X SSP12 It is recommended RW - - X SSP11 to use ICS Spread RW - - X SSP1 % table for spread RW - - X SSP9 programming. RW - - X Bit - SSP8 RW - - X I 2 C Table: Output Divider Control Register Byte 15 Pin # Name Control Function Type 1 PWD Bit 7 - SRC Div3 SRC divider ratio RW X SRC Div2 can be configured RW See Table: Divider Ratio X SRC Div1 via these 4 bits RW Combination Table X SRC Div individually. RW X CPU Div3 CPU divider ratio RW X CPU Div2 can be configured RW See Table: Divider Ratio X CPU Div1 via these 4 bits RW Combination Table X Bit - CPU Div individually. RW X I 2 C Table: Output Divider Control Register Byte 16 Pin # Name Control Function Type 1 PWD Bit 4 RESERVED PCI Div3 PCI divider ratio RW X PCI Div2 can be configured RW See Table: Divider Ratio X PCI Div1 via these 4 bits RW Combination Table X Bit - PCI Div individually. RW X I 2 C Table: Vendor & Revision ID Register Byte 17 Pin # Name Control Function Type 1 PWD PCIINV PCI Phase Invert RW Default Inverse SRCINV SRC Phase Invert RW Default Inverse CPUINV CPU Phase Invert RW Default Inverse Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit RESERVED I 2 C Table: Group Skew Control Register Byte 18 Pin # Name Control Function Type 1 PWD Bit 7 - SRC_Skw3 RW SRC_Skw2 RW See Table: 7-Steps Skew SRC Skew Control SRC_Skw1 RW Programming Table SRC_Skw RW CPU_Skw3 RW CPU_Skw2 RW See Table: 7-Steps Skew CPU Skew Control CPU_Skw1 RW Programming Table Bit - CPU_Skw RW IDT TM 148A 1/25/1 9

10 ICS9E411 I 2 C Table: Group Skew Control Register Byte 19 Pin # Name Control Function Type 1 PWD Bit 4 RESERVED PCI_Skw3 RW PCI_Skw2 RW See Table: 7-Steps Skew PCI Skew Control PCI_Skw1 RW Programming Table Bit - PCI_Skw RW I 2 C Table: Slew Rate Control Register Byte 2 Pin # Name Control Function Type 1 PWD Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit RESERVED I 2 C Table: Slew Rate Control Register Byte 21 Pin # Name Control Function Type 1 PWD Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit RESERVED I 2 C Table: Slew Rate Control Register Byte 22 Pin # Name Control Function Type 1 PWD Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit RESERVED I 2 C Table: Slew Rate Control Register Byte 23 Pin # Name Control Function Type 1 PWD Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit RESERVED IDT TM 148A 1/25/1 1

11 ICS9E411 I 2 C Table: Slew Rate Control Register Byte 24 Pin # Name Control Function Type 1 PWD Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit RESERVED I 2 C Table: Test Byte Register Byte 25 Test Test Function Type Test Result PWD Bit 7 - ICS ONLY TEST RW Reserved ICS ONLY TEST RW Reserved ICS ONLY TEST RW Reserved ICS ONLY TEST RW Reserved ICS ONLY TEST RW Reserved ICS ONLY TEST RW Reserved ICS ONLY TEST RW Reserved Bit - ICS ONLY TEST RW Reserved IDT TM 148A 1/25/1 11

12 ICS9E411 Absolute Max Symbol Parameter Min Typ Max Units VDD_A 3.3V Core Supply Voltage V DD +.5V V VDD_In 3.3V Logic Input Supply Voltage GND -.5 V DD +.5V V Ts Storage Temperature C Tambient Ambient Operating Temp C Tcase Case Temperature 115 C Input ESD protection ESD prot human body model 2 V Θ JA Thermal Resistance Junction to Ambient 57.4 C/W Θ JC Thermal Resistance Junction to Case 38.8 C/W Electrical Characteristics - Input/Supply/Common Output Parameters T A = -4 to 85 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage V IH 3.3 V +/-5% 2 V DD +.3 V Input Low Voltage V IL 3.3 V +/-5% V SS V Input High Current I IH V IN = V DD -5 5 ua Input Low Current I IL1 V IN = V; Inputs with no pullup resistors -5 ua I IL2 V IN = V; Inputs with pull-up resistors -2 ua Low Threshold Input High Voltage V IH_FS 3.3 V +/-5%.7 V DD +.3 V Low Threshold Input Low Voltage V IL_FS 3.3 V +/-5% V SS V Operating Supply Current I DD3.3OP 3.3 V +/-5%, Full Load 35 5 ma Powerdown Current I DD3.3PD all diff pairs driven 7 ma all differential pairs tri-stated 12 ma Input Frequency 3 F i V DD = 3.3 V MHz 3 Pin Inductance 1 L pin 7 nh 1 C IN Logic Inputs 5 pf 1 Input Capacitance 1 C OUT Output pin capacitance 6 pf 1 C INX X1 & X2 pins 5 pf 1 Clk Stabilization 1,2 From V T DD Power-Up or deassertion of PD# to 1st clock STAB 1.8 ms 1,2 Modulation Frequency Triangular Modulation 3 33 khz 1 Tdrive_PD# CPU output enable after PD# de-assertion 3 us 1 Tfall_Pd# PD# fall time of 5 ns 1 Trise_Pd# PD# rise time of 5 ns 2 SMBus Voltage V DD V 1 Low-level Output Voltage V I PULLUP.4 V 1 Current sinking at V OL =.4 V I PULLUP 4 ma 1 SCLK/SDATA Clock/Data Rise Time T RI2C (Max VIL -.15) to (Min VIH +.15) 1 ns 1 SCLK/SDATA Clock/Data Fall Time T FI2C (Min VIH +.15) to (Max VIL -.15) 3 ns 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal MHz to meet ppm accuracy on PLL outputs. IDT TM 148A 1/25/1 12

13 ICS9E411 Electrical Characteristics - CPU.7V Current Mode Differential Pair T A = -4 to 85 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω 1 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope mv Voltage Low VLow math function Max Voltage Vovs Measurement on single ended mv Min Voltage Vuds signal using absolute value Crossing Voltage (abs) Vcross(abs) mv 1 Crossing Voltage (var) d-vcross Variation of crossing over all edges 14 mv 1 Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 4MHz nominal ns 2 4MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2 Average period Tperiod 2MHz nominal ns 2 2MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2 1.MHz nominal ns 2 1.MHz spread ns 2 4MHz nominal/spread ns 1, MHz nominal/spread ns 1, MHz nominal/spread ns 1,2 Absolute min period T absmin 2MHz nominal/spread ns 1, MHz nominal/spread ns 1, MHz nominal/spread ns 1,2 1.MHz nominal/spread ns 1,2 Rise Time t r V OL =.175V, V OH =.525V ps 1 Fall Time t f V OH =.525V V OL =.175V ps 1 Rise Time Variation d-t r 125 ps 1 Fall Time Variation d-t f 125 ps 1 Measurement from differential Duty Cycle d t3 wavefrom % 1 Skew t sk3 CPU (1:) V T = 5% 1 ps 1 Skew t sk4 CPU (1:) to CPU_ITP, V T = 5% 15 ps 1 Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 85 ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at MHz IDT TM 148A 1/25/1 13

14 ICS9E411 Electrical Characteristics - SRC.7V Current Mode Differential Pair T A = -4 to 85 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω 1 Voltage High VHigh Statistical measurement on single mv Voltage Low VLow ended signal using oscilloscope Max Voltage Vovs Measurement on single ended mv Min Voltage Vuds signal using absolute value Crossing Voltage (abs) Vcross(abs) mv 1 Crossing Voltage (var) d-vcross Variation of crossing over all edges mv 1 Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 Average period Tperiod 1.MHz nominal ns 2 1.MHz spread ns 2 Absolute min period Tabsmin 1.MHz nominal/spread ns 1,2 Rise Time t r V OL =.175V, V OH =.525V ps 1 Fall Time t f V OH =.525V V OL =.175V ps 1 Rise Time Variation d-t r ps 1 Fall Time Variation d-t f ps 1 Measurement from differential Duty Cycle d t3 wavefrom % 1 Skew t sk3 SRC(7:), V T = 5% 25 ps 1 Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 125 ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at MHz IDT TM 148A 1/25/1 14

15 ICS9E411 Electrical Characteristics - PCICLK/PCICLK_F T A = -4 to 85 C; V DD = 3.3 V +/-5%; C L = 3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 Clock period T period 33.33MHz output nominal ns MHz output spread ns 2 Absolute Min/Max Clock 33.33MHz output nominal ns 2 T abs period 33.33MHz output spread ns 2 Clk High Time t h1 12 N/A ns 1 Clock Low Time t l1 12 N/A ns 1 Output High Voltage V OH I OH = -1 ma 2.4 V Output Low Voltage V OL I OL = 1 ma.55 V Output High Current I OH V = 1. V -33 ma V MAX = V -33 ma Output Low Current I OL V MIN = 1.95 V 3 ma V MAX =.4 V 38 ma Edge Rate Rising edge rate 1 4 V/ns 1 Edge Rate Falling edge rate 1 4 V/ns 1 Rise Time t r1 V OL =.4 V, V OH = 2.4 V.5 2 ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V.5 2 ns 1 Duty Cycle d t1 V T = 1.5 V % 1 Skew t sk1 V T = 1.5 V 5 ps 1 Jitter t jcyc-cyc V T = 1.5 V 5 ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at MHz Electrical Characteristics - USB_48MHz T A = -4 to 85 C; V DD = 3.3 V +/-5%; C L = 2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -1 1 ppm 1,2 Clock period T period 48.MHz output nominal ns 2 Absolute Min/Max Clock period T abs Nominal ns 2 Clk High Time t h ns 1 Clock Low Time t l ns 1 Output High Current I OH V MIN = 1. V -33 ma V MAX = V -33 ma Output Low Current I OL V = 1.95 V 3 ma V MAX =.4 V 38 ma Edge Rate Rising edge rate 1 2 V/ns 1 Edge Rate Falling edge rate 1 2 V/ns 1 Rise Time t r1 V OL =.4 V, V OH = 2.4 V ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V ns 1 Duty Cycle d t1 V T = 1.5 V % 1 Jitter, Cycle to cycle t jcyc-cyc V T = 1.5 V 35 ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at MHz IDT TM 148A 1/25/1 15

16 ICS9E411 Electrical Characteristics - DOT, 96MHz.7V Current Mode Differential Pair T A = -4 to 85 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω 1 Voltage High VHigh Statistical measurement mv Voltage Low VLow on single ended signal Max Voltage Vovs Measurement on single mv Min Voltage Vuds ended signal using -3 1 Crossing Voltage (abs) Vcross(abs) mv 1 Crossing Voltage Variation of crossing over d-vcross (var) all edges 14 mv 1 Long Accuracy ppm see Tperiod min-max values -1 1 ppm 1,2 Average period Tperiod 96.MHz nominal ns 2 Absolute min period Tabsmin 96.MHz nominal ns 1,2 V Rise Time t OL =.175V, V OH = r.525v ps 1 V Fall Time t OH =.525V V OL = f.175v ps 1 Rise Time Variation d-t r 125 ps 1 Fall Time Variation d-t f 125 ps 1 Measurement from Duty Cycle d t3 differential wavefrom % 1 Measurement from Jitter, Cycle to cycle t jcyc-cyc differential wavefrom 25 ps 1 1 Guaranteed by design, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at MHz Electrical Characteristics - REF MHz T A = -4 to 85 C; V DD = 3.3 V +/-5%; C L = 2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1 Clock period T period MHz output nominal ns 1 Absolute Min/Max Clock period T abs Nominal ns 2 Output High Voltage V OH I OH = -1 ma 2.4 V 1 Output Low Voltage V OL I OL = 1 ma.4 V 1 V = 1. V, Output High Current I OH V = V ma 1 V = 1.95 V, Output Low Current I OL V =.4 V ma 1 Rise Time t r1 V OL =.4 V, V OH = 2.4 V 1 2 ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V 1 2 ns 1 Skew t sk1 V T = 1.5 V 5 ps 1 Duty Cycle d t1 V T = 1.5 V % 1 Jitter t jcyc-cyc V T = 1.5 V 1 ps 1 1 Guaranteed by design, not 1% tested in production. IDT TM 148A 1/25/1 16

17 ICS9E411 Test Clarification Table Comments FS_C/TEST_SEL is a 3-level latched input. o Power-up w/ V >= 2.V to select TEST o Power-up w/ V < 2.V to have pin function as FS_C. When pin is FS_C, VIH_FS and VIL_FS levels apply. FS_B/TEST_MODE is a low-threshold input o VIH_FS and VIL_FS levels apply. o TEST_MODE is a real time input TEST_SEL can be invoked after power up through SMBus B6b6. o If TEST is selected by B6b6, only B6b7 controls TEST_MODE. The FS_B/TEST_Mode pin is not used. Power must be cycled to exit TEST. B6b6: 1= ENTER TEST MODE, Default = (NORMAL OPERATION) B6b7: 1= REF/N, Default = (HI-Z) HW SW FS_C/TEST FS_B/TEST TEST ENTRY REF/N or _SEL HW PIN _MODE HW PIN BIT B6b6 HI-Z B6b7 OUTPUT X X NORMAL 1 X HI-Z 1 X 1 REF/N 1 1 X REF/N 1 1 X 1 REF/N X 1 HI-Z X 1 1 REF/N IDT TM 148A 1/25/1 17

18 ICS9E411 INDEX AREA N 1 2 D E1 A E h x 45 c α L 56-Lead, 3 mil Body, 25 mil, SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS a 8 8 e b A1 -C- - SEATING PLANE VARIATIONS D mm. D (inch) N MIN MAX MIN MAX (.4) C Reference Doc.: JEDEC Publication 95, MO Ordering Information Example: 9E411yFILFT XXXX y F I LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Industrial Temperature Range Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type IDT TM 148A 1/25/1 18

19 ICS9E411 Revision History Rev. Issue Date Description Page #.1 1/25/7 Initial Release -.2 7/11/8 Corrected operating temperature range on "Absolute Max" electrical characteristics table /6/8 Corrected typo on ordering information /7/9 Removed "Advanced Information" from document header. Various.5 2/17/9 Added thermal chars. 12 A 1/25/1 Released to final. Updated document template. Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 624 Silver Creek Valley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #2-3 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE TM 29 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 19