Programmable System Clock Chip for ATI RS400 P4 TM -based Systems

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1 Programmable System Clock Chip for ATI RS4 P4 TM -based Systems Recommended Application: ATI RS4 systems using Intel P4 TM processors Output Features: 6 - Pairs of SRC/PCI Express* clocks 2 - Pairs of programmable SRC/PCI Express (ATIG) clocks 3 - Pairs of Intel P4 clocks MHz REF clocks 1-48MHz USB clock 1-33 MHz PCI clock seed Features/Benefits: 2 - Programmable Clock Request pins for SRC clocks Supports CK41 or CK49 frequency table mapping Spread Spectrum for EMI reduction Outputs may be disabled via SMBus External crystal load capacitors for maximum frequency accuracy Key Specifications: CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter <125ps PCI outputs cycle-cycle jitter < 25ps +/- 3ppm frequency accuracy on CPU & SRC clocks Functionality - (CK41# = ) FS_C 1 FS_B 1 FS_A 1 CPU SRC PCI REF USB MHz MHz MHz MHz MHz RESERVED Functionality - (CK41# = 1) FS_C 1 Byte6 bit5 1 FS_B 1 FS_A 1 CPU MHz SRC MHz PCI MHz REF MHz USB MHz FS_C, FS_B and FS_A are low-threshold inputs. Please see the V IL_FS and V IH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration X1 1 X2 2 VDD48 3 USB_48MHz 4 GND 5 VTT_PWRGD#/PD 6 SCLK 7 SDATA 8 **FS_C 9 **CLKREQA# 1 **CLKREQB# 11 SRCCLKT7 12 SRCCLKC7 13 VDDSRC 14 GNDSRC 15 SRCCLKT6 16 SRCCLKC6 17 SRCCLKT5 18 SRCCLKC5 19 GNDSRC 2 VDDSRC 21 SRCCLKT4 22 SRCCLKC4 23 SRCCLKT3 24 SRCCLKC3 25 GNDSRC 26 ATIGCLKT1 27 ATIGCLKC VDDREF 55 GND 54 **FS_A/REF 53 **FS_B/REF1 52 **TEST_SEL/REF2 51 VDDPCI 5 **CK41#/PCICLK 49 GNDPCI 48 *CPU_STOP# 47 CPUCLKT 46 CPUCLKC 45 VDDCPU 44 GNDCPU 43 CPUCLKT1 42 CPUCLKC1 41 CPUCLKT2_ITP 4 CPUCLKC2_ITP 39 VDDA 38 GNDA 37 IREF 36 GNDSRC 35 VDDSRC 34 SRCCLKT 33 SRCCLKC 32 VDDATI 31 GNDATI 3 ATIGCLKT 29 ATIGCLKC Note: Pins preceeded by '**' have a 12 Kohm Internal Pull Down resistor Pins preceeded by '*' have a 12 Kohm Internal Pull Up resistor 56-pin SSOP & TSSOP *Other names and brands may be claimed as the property of others.

2 Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 X1 IN Crystal input, Nominally MHz. 2 X2 OUT Crystal output, Nominally MHz 3 VDD48 PWR Power pin for the 48MHz output.3.3v 4 USB_48MHz OUT 48.MHz USB clock 5 GND PWR Ground pin. Vtt_PwrGd# is an active low input used to determine when latched inputs are 6 VTT_PWRGD#/PD IN ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 7 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 8 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 9 **FS_C IN Frequency select latch input pin 1 **CLKREQA# IN Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. = enabled, 1 = tri-stated 11 **CLKREQB# IN Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. = enabled, 1 = tri-stated 12 SRCCLKT7 OUT True clock of differential SRC clock pair. 13 SRCCLKC7 OUT Complement clock of differential SRC clock pair. 14 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 15 GNDSRC PWR Ground pin for the SRC outputs 16 SRCCLKT6 OUT True clock of differential SRC clock pair. 17 SRCCLKC6 OUT Complement clock of differential SRC clock pair. 18 SRCCLKT5 OUT True clock of differential SRC clock pair. 19 SRCCLKC5 OUT Complement clock of differential SRC clock pair. 2 GNDSRC PWR Ground pin for the SRC outputs 21 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 22 SRCCLKT4 OUT True clock of differential SRC clock pair. 23 SRCCLKC4 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 26 GNDSRC PWR Ground pin for the SRC outputs 27 ATIGCLKT1 OUT True clock of differential ATIGCLK clock pair. 28 ATIGCLKC1 OUT Complementary clock of differential ATIGCLK clock pair. 2

3 Pin Description (Continued) PIN # PIN NAME PIN TYPE Pin Description 29 ATIGCLKC OUT Complementary clock of differential ATIGCLK clock pair. 3 ATIGCLKT OUT True clock of differential ATIGCLK clock pair. 31 GNDATI PWR Ground for ATI Gclocks, nominal 3.3V 32 VDDATI PWR Power supply ATI Gclocks, nominal 3.3V 33 SRCCLKC OUT Complement clock of differential SRC clock pair. 34 SRCCLKT OUT True clock of differential SRC clock pair. 35 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 36 GNDSRC PWR Ground pin for the SRC outputs This pin establishes the reference current for the differential current-mode 37 IREF OUT output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 38 GNDA PWR Ground pin for the PLL core. 39 VDDA PWR 3.3V power for the PLL core. 4 CPUCLKC2_ITP Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. 41 CPUCLKT2_ITP True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. 42 CPUCLKC1 Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. 43 CPUCLKT1 True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. 44 GNDCPU PWR Ground pin for the CPU outputs 45 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 46 CPUCLKC Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. 47 CPUCLKT True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. 48 *CPU_STOP# IN Stops all CPUCLK, except those set to be free running clocks 49 GNDPCI PWR Ground pin for the PCI outputs 5 **CK41#/PCICLK I/O FS Table select latch input pin / 3.3V PCI clock output. = CK41 FS Table, 1 = CK49 FS Table 51 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 52 **TEST_SEL/REF2 I/O TEST_SEL: latched input to select TEST MODE / MHz reference clock. 1 = All outputs are CK41 REF/N test mode = All outputs behave normally. 53 **FS_B/REF1 I/O Frequency select latch input pin / MHz reference clock. 54 **FS_A/REF I/O Frequency select latch input pin / MHz reference clock. 55 GND PWR Ground pin. 56 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 3

4 General Description provides a single-chip clocking solution for the ATI RS4-based systems using the latest Intel P4 processors. is driven with a MHz crystal. It generates CPU outputs up to 4MHz and also provides highly accurate SRC clocks for PCI-Express support. Two Clock Request pins are provided for Express-Card TM support. Two of the SRC outputs (ATIGCLK(1:)) are frequency programmable. Block Diagram REF(2:) X1 X2 XTAL OSC. FIXED PLL USB_48MHz PCI33 DIV PCICLK CPU PLL CK41# FS_(C:A) CLKREQA# CLKREQB# CPU_STOP# CONTROL LOGIC CPU DIV CPUCLK(2:) VTT_PWRGD#/PD SDATA SCLK SRC PLL SRC DIV2 /8/7/6/5 ATIGCLK(1:) SRC DIV1 SRCCLK(7:3,) IREF Power Groups Pin Number VDD GND Description Xtal, REF PCICLK output CPUCLK Outputs 14, 21, 35 15, 2, 26, 36 SRCCLK outputs ATIGCLK outputs Analog, CPU PLL 3 5 USB_48MHz output 4

5 General SMBus serial interface information for the How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit T Index Block Write Operation Controller (Host) ICS (Slave/Receiver) start bit Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N ACK ACK ACK ACK Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD ACK ACK ACK P Byte N + X - 1 stop bit X Byte ACK ACK ACK X Byte Data Byte Count = X Beginning Byte N N P Not acknowledge stop bit Byte N + X - 1 5

6 Table1: CPU Frequency Selection Table Bit 4 Bit 3 Bit2 Bit1 Bit CPU FS4 Byte,bit6 FSC FSB FSA (CK41#) (SS_EN) CPU (MHz) PCI33 (MHz) Spread % No Spread Reserved % Reserved No Spread % C K 4 1 C K 4 9 6

7 Table2: SRC & ATIG Frequency Selection Table Bit4 SRC FS4 (SS_EN) Bit3 SRC FS3 Bit2 FS2 Bit1 FS1 Bit FS SRC(7:3,), ATIG(1:) (MHz) Spread % SRC OverClock % % % % % % % % % % % % % % % % 1.4 7

8 Table 3: CPU Divider Ratios Divider (3:2) Bit MSB LSB Address Div Address Div Address Div Address Div Divider (1:) Table 4: PCI Divider Ratios Divider (3:2) Bit MSB LSB Address Div Address Div Address Div Address Div Divider (1:) Table 5: SRC, ATIG Divider Ratios Divider (3:2) Bit MSB LSB Address Div Address Div Address Div Address Div Divider (1:) Table 6: Test Clarification Table Comments 1. Power-up w/ TEST_SEL/REF2 > 2.V to enter test mode. 2. Cycle power to disable test mode HW TEST_SEL/REF2 HW PIN <.8V >2.V OUTPUT NORMAL HI-Z 8

9 SMBus Table: Frequency Select Register Byte Pin # Name Control Function Type 1 PWD Bit 7 - FS Source Latched Input or SMBus Frequency Select Latched Inputs SMBus Bit 6 - CPU FS3 CPU Freq Select Bit3 (SS_EN) (Spread Enable) OFF ON Bit 5 - Reserved Reserved Reserved Reserved X Bit 4 - CK41# CPU Freq Select Bit 4 Latched Bit 3 - Reserved Reserved See Table 1: CPU Bit 2 - CPU FS_C CPU Freq Select Bit 2 Frequency Selection Latched Bit 1 - CPU FS_B CPU Freq Select Bit 1 Table Latched Bit - CPU FS_A CPU Freq Select Bit Latched NOTE: Byte 5 Bit 4 must also set to "1" in order to enable spread for SRC and ATIG clocks SMBus Table: Output Control Register Byte 1 Pin # Name Control Function Type 1 PWD Bit 7 5 PCICLK Output Enable Disable Enable 1 Bit 6 41,4 CPUCLK2 Output Enable Disable Enable 1 Bit 5 4 USB_48MHz Output Enable Disable Enable 1 Bit 4 54 REF Output Enable Disable Enable 1 Bit 3 53 REF1 Output Enable Disable Enable 1 Bit 2 52 REF2 Output Enable Disable Enable 1 Bit 1 47,46 CPUCLK Output Enable Disable Enable 1 Bit 43,42 CPUCLK1 Output Enable Disable Enable 1 SMBus Table: CLKREQB# Output Control Register Byte 2 Pin # Name Control Function Type 1 PWD Bit 7 12,13 REQBSRC7 CLKREQB# Controls Does not SRC7 control Controls Bit 6 16,17 REQBSRC6 CLKREQB# Controls Does not SRC6 control Controls Bit 5 18,19 REQBSRC5 CLKREQB# Controls Does not SRC5 control Controls Bit 4 22,23 REQBSRC4 CLKREQB# Controls Does not SRC4 control Controls Bit 3 24,25 REQBSRC3 CLKREQB# Controls Does not SRC3 control Controls = CPU is free-run Bit 2 47,46 CPU_Stop_En 1 = CPU is stopped by Free-Run Stoppable 1 CPU_STOP# Bit 1 - Reserved Reserved Reserved X Bit 34,33 REQBSRC CLKREQB# Controls Does not SRC control Controls NOTE: CPU_Stop_En (Byte2, bit 2) only exists in devices with REV ID = 2 or higher 9

10 SMBus Table: SRCCLK(7:3,), CLKREQA# Output Control Register Byte 3 Pin # Name Control Function Type 1 PWD Bit 7 12,13 SRCCLK7 Disable Enable 1 Bit 6 16,17 SRCCLK6 Master Output control. Disable Enable 1 Bit 5 18,19 SRCCLK5 Enables or disables Disable Enable 1 Bit 4 22,23 SRCCLK4 output, regardless of Disable Enable 1 Bit 3 24,25 SRCCLK3 CLKREQ# inputs. Disable Enable 1 Bit 2 34,33 SRCCLK Disable Enable 1 Bit 1 24,25 REQASRC3 CLKREQA# Controls Does not SRC3 control Controls Bit 34,33 REQASRC CLKREQA# Controls Does not SRC control Controls SMBus Table: SRCCLK(3,), ATIGCLK Output Control Register Byte 4 Pin # Name Control Function Type 1 PWD Bit 7 12,13 REQASRC7 CLKREQA# Controls Does not SRC7 control Controls Bit 6 16,17 REQASRC6 CLKREQA# Controls Does not SRC6 control Controls Bit 5 18,19 REQASRC5 CLKREQA# Controls Does not SRC5 control Controls Bit 4 22,23 REQASRC4 CLKREQA# Controls Does not SRC4 control Controls Bit 3 27,28 ATIGCLK1 Output Enable These outputs cannot Disabled Enabled 1 Bit 2 3,29 ATIGCLK be controlled by CLKREQ# pins. Disabled Enabled 1 Bit 1 Differential CPU, SRC, Hi-Z or driven when Output Disable ATIG disabled Mode Driven Hi-Z Bit 4 USB_48Str 48MHz Strength Control 1X 2X 1 NOTE: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output. Behavior of the device is undefined under these conditions. SMBus Table: Output Drive and ATIG Frequency Control Register Byte 5 Pin # Name Control Function Type 1 PWD Bit 7 52 REF2Str REF2 Strength Control 1X 2X 1 Bit 6 41,4 CPU2_Stop_En = CPU is free-run Free-Run Stoppable 1 1 = CPU is stopped by Bit 5 43,42 CPU1_Stop_En CPU_STOP# Free-Run Stoppable 1 Bit 4 - SRCFS4 Freq Select Bit 4 (SS_EN) (SS_EN) Bit 3 - SRCFS3 Freq Select Bit 3 See Table 2 SRC Bit 2 - SRCFS2 Freq Select Bit 2 Frequency Selection Bit 1 - SRCFS1 Freq Select Bit 1 Bit - SRCFS Freq Select Bit NOTE: CPU(1:2)_Stop_En (Byte5, bit 6:5) only exist in devices with REV ID = 2 or higher 1

11 SMBus Table: Device ID Register Byte 6 Pin # Name Control Function Type 1 PWD Bit 7 - DevID 7 Device ID MSB R - - Bit 6 - DevID 6 Device ID 6 R - - Bit 5 - DevID 5 Device ID 5 R - - Bit 4 - DevID 4 Device ID4 R Bit 3 - DevID 3 Device ID3 R - - Bit 2 - DevID 2 Device ID2 R - - Bit 1 - DevID 1 Device ID1 R Bit - DevID Device ID LSB R SMBus Table: Vendor ID Register Byte 7 Pin # Name Control Function Type 1 PWD Bit 7 - RID3 R - - X Revision ID Bit 6 - RID2 R - - X Starts at hex for A Bit 5 - RID1 R - - X revsion. Bit 4 - RID R - - X Bit 3 - VID3 R - - Bit 2 - VID2 VENDOR ID R - - Bit 1 - VID1 (1 = ICS) R - - Bit - VID R SMBus Table: Byte Count Register Byte 8 Pin # Name Control Function Type 1 PWD Bit 7 - BC7 Bit 6 - BC6 Bit 5 - BC5 Writing to this register Bit 4 - BC4 Byte Count will configure how many Bit 3 - BC3 Programming b(7:) bytes will be read back, 1 Bit 2 - BC2 default is 9 bytes. Bit 1 - BC1 Bit - BC 1 SMBus Table: WD TimeR Control Register Byte 9 Pin # Name Control Function Type 1 PWD Bit 7 - WDH_EN Watchdog Hard Alarm Enable Disable Enable Bit 6 - WDS_EN Watchdog Soft Alarm Enable Disable Enable Bit 5 - WD Hard Status WD Hard Alarm Status R Normal Alarm X Bit 4 - WD Soft Status WD Soft Alarm Status R Normal Alarm X Bit 3 - WDTCtrl Watch Dog Time base 116ms 29ms Base Control Base Bit 2 - WD2 WD Timer Bit 2 These bits represent X*29ms (or 1.16S) the 1 Bit 1 - WD1 WD Timer Bit 1 watchdog timer waits before it goes to alarm 1 Bit - WD WD Timer Bit mode. Default is 7 X 29ms = 2s. 1 11

12 SMBus Table: M/N Programming & WD Safe Frequency Control Register Byte 1 Pin # Name Control Function Type 1 PWD Bit 7 - M/N_EN PLLS M/N Programming Enable Disable Enable Bit 6 - Reserved Reserved - - Bit 5 - WD Safe Freq Latch WD Safe Freq Source B1b(4:) Source Inputs Bit 4 - WD SF4 Writing to these bit will Bit 3 - WD SF3 Watch Dog Safe Freq configure the safe Bit 2 - WD SF2 Programming bits frequency as Byte bit Bit 1 - WD SF1 (4:). Bit - WD SF SMBus Table: CPU Frequency Control Register Byte 11 Pin # Name Control Function Type 1 PWD Bit 7 - N Div8 N Divider Prog bit 8 The decimal X Bit 6 - N Div9 N Divider Prog bit 9 representation of M and X N Divier in Byte 11 and Bit 5 - M Div5 12 will configure the X Bit 4 - M Div4 M Divider Programming CPU VCO frequency. X Bit 3 - M Div3 Default at power up = X latch-in or Byte Rom Bit 2 - M Div2 X table. VCO Frequency = Bit 1 - M Div1 bit (5:) x [NDiv(9:)+8] / X Bit - M Div [MDiv(5:)+2] X SMBus Table: CPU Frequency Control Register Byte 12 Pin # Name Control Function Type 1 PWD Bit 7 - N Div7 The decimal X Bit 6 - N Div6 representation of M and X N Divier in Byte 11 and Bit 5 - N Div5 12 will configure the X N Divider Programming Bit 4 - N Div4 CPU VCO frequency. X Byte12 bit(7:) and Bit 3 - N Div3 Byte11 bit(7:6) Default at power up = X latch-in or Byte Rom Bit 2 - N Div2 X table. VCO Frequency = Bit 1 - N Div x [NDiv(9:)+8] / X Bit - N Div [MDiv(5:)+2] X SMBus Table: CPU Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 1 PWD Bit 7 - SSP7 X Bit 6 - SSP6 X Bit 5 - SSP5 These Spread Spectrum X Bit 4 - SSP4 Spread Spectrum bits in Byte 13 and 14 X Bit 3 - SSP3 Programming bit(7:) will program the spread X Bit 2 - SSP2 pecentage of CPU X Bit 1 - SSP1 X Bit - SSP X 12

13 SMBus Table: CPU Spread Spectrum Control Register Byte 14 Pin # Name Control Function Type 1 PWD Bit 7 - Reserved Reserved R - - Bit 6 - SSP14 X Bit 5 - SSP13 X These Spread Spectrum Bit 4 - SSP12 X Spread Spectrum bits in Byte 13 and 14 Bit 3 - SSP11 X Programming bit(14:8) will program the spread Bit 2 - SSP1 X pecentage of CPU Bit 1 - SSP9 X Bit - SSP8 X SMBus Table: SRC Frequency Control Register Byte 15 Pin # Name Control Function Type 1 PWD Bit 7 - N Div8 N Divider Prog bit 8 The decimal X Bit 6 - N Div9 N Divider Prog bit 9 representation of M and X N Divier in Byte 15 and Bit 5 - M Div5 16 will configure the X Bit 4 - M Div4 SRC VCO frequency. X Bit 3 - M Div3 M Divider Programming Default at power up = X Bit 2 M Div2 bits latch-in or Byte Rom - X table. VCO Frequency = Bit 1 - M Div x [NDiv(9:)+8] / X Bit - M Div [MDiv(5:)+2] X SMBus Table: SRC Frequency Control Register Byte 16 Pin # Name Control Function Type 1 PWD Bit 7 - N Div7 The decimal X Bit 6 - N Div6 representation of M and X N Divier in Byte 15 and Bit 5 - N Div5 16 will configure the X Bit 4 - N Div4 N Divider Programming SRC VCO frequency. X Bit 3 - N Div3 b(7:) Default at power up = X latch-in or Byte Rom Bit 2 - N Div2 X table. VCO Frequency = Bit 1 - N Div x [NDiv(9:)+8] / X Bit - N Div [MDiv(5:)+2] X SMBus Table: SRC Spread Spectrum Control Register Byte 17 Pin # Name Control Function Type 1 PWD Bit 7 - SSP7 X Bit 6 - SSP6 X Bit 5 - SSP5 These Spread Spectrum X Bit 4 - SSP4 Spread Spectrum bits in Byte 17 and 18 X Bit 3 - SSP3 Programming b(7:) will program the spread X Bit 2 - SSP2 pecentage of SRC X Bit 1 - SSP1 X Bit - SSP X 13

14 SMBus Table: SRC Spread Spectrum Control Register Byte 18 Pin # Name Control Function Type 1 PWD Bit 7 - Reserved Reserved R - - Bit 6 - SSP14 X Bit 5 - SSP13 X These Spread Spectrum Bit 4 - SSP12 X Spread Spectrum bits in Byte 17 and 18 Bit 3 - SSP11 X Programming b(14:8) will program the spread Bit 2 - SSP1 X pecentage of SRC Bit 1 - SSP9 X Bit - SSP8 X SMBus Table: Programmable Output Divider Register Byte 19 Pin # Name Control Function Type 1 PWD Bit 7 - CPUDiv3 X Bit 6 - CPUDiv2 CPU Divider Ratio See Table 3: CPU X Bit 5 - CPUDiv1 Programming Bits Divider Ratios X Bit 4 - CPUDiv X Bit 3 - PCIDiv3 X Bit 2 - PCIDiv2 PCI Divider Ratio See Table 4: PCI Divider X Bit 1 - PCIDiv1 Programming Bits Ratios X Bit - PCIDiv X SMBus Table: Programmable Output Divider Register Byte 2 Pin # Name Control Function Type 1 PWD Bit 7 - SRC_Div3 X Bit 6 - SRC_Div2 SRC_ Divider Ratio X Bit 5 - SRC_Div1 Programming Bits X Bit 4 - SRC_Div See Table 5: ATIG and X Bit 3 - ATIG_Div3 SRC Divider Ratios X Bit 2 - ATIG_Div2 ATIG_ Divider Ratio X Bit 1 - ATIG_Div1 Programming Bits X Bit - ATIG_Div X SMBusTable: Test Byte Register Byte 21 Test Test Function Type Test Result PWD Bit 7 ` ICS ONLY TEST Reserved Bit 6 ICS ONLY TEST Reserved Bit 5 ICS ONLY TEST Reserved Bit 4 ICS ONLY TEST Reserved Bit 3 ICS ONLY TEST Reserved Bit 2 ICS ONLY TEST Reserved Bit 1 ICS ONLY TEST Reserved Bit ICS ONLY TEST Reserved 14

15 Absolute Max Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage V DD +.5V V VDD_In 3.3V Logic Input Supply Voltage GND -.5 V DD +.5V V Ts Storage Temperature C Tambient Ambient Operating Temp 7 C Tcase Case Temperature 115 C ESD prot Input ESD protection human body model 2 V Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Input High Voltage V IH 3.3 V +/-5% 2 V DD +.3 V 1 Input Low Voltage V IL 3.3 V +/-5% V SS V 1 Input High Current I IH V IN = V DD -5 5 ua 1 Input Low Current I IL1 V IN = V; Inputs with no pullup resistors -5 ua 1 I IL2 V IN = V; Inputs with pull-up resistors -2 ua 1 Low Threshold Input- High Voltage V IH_FS 3.3 V +/-5%.7 V DD +.3 V 1 Low Threshold Input- Low Voltage V IL_FS 3.3 V +/-5% V SS V 1 Operating Current I DD3.3OP all outputs driven 4 ma 1 Powerdown Current I DD3.3PD all diff pairs driven 7 ma 1 all differential pairs tri-stated 12 ma 1 Input Frequency F i V DD = 3.3 V MHz 3 Pin Inductance L pin 7 nh 1 C IN Logic Inputs 5 pf 1 Input Capacitance C OUT Output pin capacitance 6 pf 1 C INX X1 & X2 pins 5 pf 1 From V DD Power-Up or deassertion of PD# to 1st clock Clk Stabilization T STAB 1.8 ms 1,2 Modulation Frequency Triangular Modulation 3 33 khz 1 Tdrive_PD# CPU output enable after PD# de-assertion 3 us 1 Tfall_Pd# PD# fall time of 5 ns 1 Trise_Pd# PD# rise time of 5 ns 2 SMBus Voltage V DD V 1 Low-level Output Voltage V I PULLUP.4 V 1 Current sinking at V OL =.4 V I PULLUP 4 ma 1 SCLK/SDATA (Max VIL -.15) to T RI2C Clock/Data Rise Time (Min VIH +.15) 1 ns 1 SCLK/SDATA (Min VIH +.15) to T FI2C Clock/Data Fall Time (Max VIL -.15) 3 ns 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal MHz to meet ppm frequency accuracy on PLL outputs. 15

16 Electrical Characteristics - CPU.7V Current Mode Differential Pair T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω 1 Voltage High VHigh Statistical measurement on single ,3 Voltage Low VLow ended signal using oscilloscope math function mv 1,3 Max Voltage Vovs Measurement on single ended mv Min Voltage Vuds signal using absolute value Crossing Voltage (abs) Vcross(abs) mv 1 Crossing Voltage (var) d-vcross Variation of crossing over all edges 14 mv 1 Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 4MHz nominal ns 2 4MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2 Average period Tperiod 2MHz nominal ns 2 2MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2 1.MHz nominal ns 2 1.MHz spread ns 2 4MHz nominal/spread ns 1, MHz nominal/spread ns 1, MHz nominal/spread ns 1,2 Absolute min period T absmin 2MHz nominal/spread ns 1, MHz nominal/spread ns 1, MHz nominal/spread ns 1,2 1.MHz nominal/spread ns 1,2 Rise Time t r V OL =.175V, V OH =.525V ps 1 Fall Time t f V OH =.525V V OL =.175V ps 1 Rise Time Variation d-t r 125 ps 1 Fall Time Variation d-t f 125 ps 1 Measurement from differential Duty Cycle d t3 wavefrom % 1 Skew t sk3 CPU(1:), V T = 5% 1 ps 1 CPU(1:) to CPU2_ITP, Skew t sk4 V T = 5% 15 ps 1 Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom (CPU2_ITP) 125 ps 1 Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom, (CPU(1:)) 85 ps 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at MHz 3 I REF = V DD /(3xR R ). For R R = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH Z O =5Ω. 16

17 Electrical Characteristics - SRC.7V Current Mode Differential Pair T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Current Source Output Zo V O = V x 3 Ω 1 Impedance Voltage High VHigh Statistical measurement ,3 mv Voltage Low VLow on single ended signal ,3 Max Voltage Vovs Measurement on single mv Min Voltage Vuds ended signal using -3 1 Crossing Voltage (abs) Vcross(abs) mv 1 Crossing Voltage (var) d-vcross Variation of crossing over all edges mv 1 Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 Average period Tperiod 1.MHz nominal ns 2 1.MHz spread ns 2 Absolute min period Tabsmin 1.MHz nominal/spread ns 1,2 V OL =.175V, Rise Time t r V OH =.525V ps 1 V OH =.525V Fall Time t f V OL =.175V ps 1 Rise Time Variation d-t r ps 1 Fall Time Variation d-t f ps 1 Measurement from Duty Cycle d t3 differential wavefrom % 1 Skew t sk3 V T = 5% 25 ps 1 Measurement from Jitter, Cycle to cycle t jcyc-cyc differential wavefrom 125 ps 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at MHz 3 I REF = V DD /(3xR R ). For R R = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH Z O =5Ω. 17

18 Electrical Characteristics - PCICLK/PCICLK_F T A = - 7 C; V DD = 3.3 V +/-5%; C L = 1-2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1,2 Clock period T period 33.33MHz output nominal ns MHz output spread ns 2 Output High Voltage V OH I OH = -1 ma 2.4 V 1 Output Low Voltage V OL I OL = 1 ma.55 V 1 Output High Current I OH V = 1. V -33 ma 1 V MAX = V -33 ma 1 Output Low Current I OL V MIN = 1.95 V 3 ma 1 V MAX =.4 V 38 ma 1 Edge Rate Rising edge rate 1 4 V/ns 1 Edge Rate Falling edge rate 1 4 V/ns 1 Rise Time t r1 V OL =.4 V, V OH = 2.4 V.5 2 ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V.5 2 ns 1 Duty Cycle d t1 V T = 1.5 V % 1 Jitter t jcyc-cyc V T = 1.5 V 25 ps 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at MHz Electrical Characteristics - 48MHz, USB T A = - 7 C; V DD = 3.3 V +/-5%; C L = 1-2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -1 1 ppm 1,2 Clock period T period 48.MHz output nominal ns 2 Output High Voltage V OH I OH = -1 ma 2.4 V 1 Output Low Voltage V OL I OL = 1 ma.55 V 1 Output High Current I OH V MIN = 1. V -33 ma 1 V MAX = V -33 ma 1 Output Low Current I OL V = 1.95 V 3 ma 1 V MAX =.4 V 38 ma 1 Edge Rate Rising edge rate 1 2 V/ns 1 Edge Rate Falling edge rate 1 2 V/ns 1 Rise Time t r1 V OL =.4 V, V OH = 2.4 V 1 2 ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V 1 2 ns 1 Duty Cycle d t1 V T = 1.5 V % 1 Jitter, Cycle to cycle t jcyc-cyc V T = 1.5 V 175 ps 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at MHz 18

19 Electrical Characteristics - REF MHz T A = - 7 C; V DD = 3.3 V +/-5%; C L = 1-2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm 1 Clock period T period MHz output nominal ns 1 Output High Voltage V OH I OH = -1 ma 2.4 V 1 Output Low Voltage V OL I OL = 1 ma.4 V 1 V = 1. V, Output High Current I OH V = V ma 1 V Output Low Current I = 1.95 V, V OL =.4 V ma 1 Rise Time t r1 V OL =.4 V, V OH = 2.4 V 1 2 ns 1 Fall Time t f1 V OH = 2.4 V, V OL =.4 V 1 2 ns 1,2 Skew t sk1 V T = 1.5 V 5 ps 2 Duty Cycle d t1 V T = 1.5 V % 1,2 Jitter t jcyc-cyc V T = 1.5 V 1 ps 1 1 Guaranteed by design and characterization, not 1% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at MHz 19

20 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value Unit Figure L1 length, Route as non -coupled 5 ohm trace..5 max inch 2, 3 L2 length, Route as non -coupled 5 ohm trace..2 max inch 2, 3 L3 length, Route as non -coupled 5 ohm trace..2 max inch 2, 3 Rs 33 ohm 2, 3 Rt 49.9 ohm 2, 3 Down Device Differential Routing Dimension or Value Unit Figure L4 length, Route as coupled microstrip 1 ohm 2 min to 16 max inch 2 differential trace. L4 length, Route as coup led stripline 1 ohm 1.8 min to 14.4 max inch 2 differential trace. Differential Routing to PCI Express Connector Dimension or Value Unit Figure L4 length, Route as coupled microstrip 1 ohm.25 to 14 max inch 3 differential trace. L4 length, Rout e as coupled stripline 1 ohm.225 min to 12.6 inch 3 differential trace. max L1 Rs L2 L4 Fig.1 L1 L2 Rs Rt Rt L4 HSCL Output Buffer L3 L3 PCI Ex REF_CLK Test Load L1 Rs L2 L4 Fig.2 L1 L2 Rs Rt Rt L4 HSCL Output Buffer L3 L3 PCI Ex Board Down Device REF_CLK Input L1 Rs L2 L4 Fig.3 L1 L2 Rs Rt Rt L4 HSCL Output Buffer L3 L3 PCI Ex Add In Board REF_CLK Input 2

21 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic ) voltage potential. A 1 Kilohm (1K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 1 21

22 INDEX AREA N 1 2 D E1 A E h x 45 c α L 56-Lead, 3 mil Body, 25 mil, SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS a 8 8 e b A1 -C- - SEATING PLANE VARIATIONS D mm. D (inch) N MIN MAX MIN MAX (.4) C Reference Doc.: JEDEC Publication 95, MO Ordering Information yflft Example: ICS XXXX y F LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 22

23 INDEX AREA A2 e N 1 2 D b E1 E A A1 c - C - SEATING PLANE aaa C L 56-Lead 6.1 mm. Body,.5 mm. Pitch TSSOP (24 mil) (2 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A A b c D E SEE VARIATIONS 8.1 BASIC SEE VARIATIONS.319 BASIC E e.5 BASIC.2 BASIC L N SEE VARIATIONS SEE VARIATIONS a 8 8 aaa VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, M O Ordering Information yglft Example: ICS XXXX y G LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 23

24 Revision History Rev. Issue Date Description Page # D 1/3/26 Fixed Comments on Bytes 11-12, Text Cutoff

System Clock Chip for ATI RS400 P4 TM -based Systems

System Clock Chip for ATI RS400 P4 TM -based Systems Recommended Application: ATI RS400 systems using Intel P4 TM processors Output Features: 6 - Pairs of SRC/PCI-Express clocks 2 - Pairs of ATIG (SRC/PCI