932SQ428. General Description. Features/Benefits. Key Specifications. Recommended Application. Output Features. Block Diagram DATASHEET

Transcription

1 DATASHEET 932SQ428 General Description The 932SQ428 is a main clock synthesizer for Romley-generation Intel based server platforms. The 932SQ428 is driven with a 25 MHz crystal for maximum performance. It generates CPU outputs of MHz. Recommended Application CK42BQ utput Features 2 - HCSL Non-Spread SAS outputs 3 - HCSL SRC outputs - can be used as CPU@M - HCSL DT96 output - 3.3V 48M output 5-3.3V PCI outputs - 3.3V 4.38M output Features/Benefits.5% down spread capable on SRC/PCI outputs; Lower EMI 48-pin MLF package; Space Savings Key Specifications Cycle to cycle jitter: SRC/NS_SAS < 5ps Phase jitter: PCIe Gen2 <3ps rms Phase jitter: PCIe Gen3 <ps rms Phase jitter: QPI 9.6GB/s <.2ps rms Phase jitter: NS-SAS <.4ps rms using raw phase data Phase jitter: NS-SAS <.3ps rms using Clk Jit Tool.6.3 Block Diagram IDT 932SQ428 REV E 4232

2 Pin Configuration X2_25 X_25 GNDXTAL GND4 REF4_3x VDD4 AVDD4 GND4 SMBCLK SMBDATA GND VDD VDDXTAL 36 GNDNS GNDPCI 2 35 AVDDNS PCI4_2x 3 34 NS_SAST PCI3_2x 4 33 NS_SASC PCI2_2x 5 32 GNDNS PCI_2x 6 3 VDDNS 932SQ428 PCI_2x 7 3 NS_SAST VDDPCI 8 29 NS_SASC VDD IREF 48M_2x 27 GNDSRC GND48 26 AVDDSRC GND VDDSRC DT96T DT96C VDD96 CKPWRGD#/PD VDDSRC SRCT SRCC GNDSRC SRCC SRCT SRCC2 SRCT2 48-Pin MLF (6x6mm.4mm pitch) Pins with ^ prefix have internal 2K pullup Pins with v prefix have internal 2K pulldown 932SQ428 Functionality SRC PCI REF NS_SAS DT96 USB Unit MHz Spread Spectrum Control SS_Enable SRC & PCI (Bb) FF N Power Group Table MLF VDD GND Description MHz PLL Analog REF4M utput and Logic 46 25MHz XTAL 8 2 PCI utputs and Logic 9 48MHz utput and Logic MHz PLL Analog, utput and Logic 7, 25 2 SRC utputs and Logic SRC PLL Analog 3 32 Non-Spreading Differential utputs & Logic NS-SAS PLL Analog Core Logic 932SQ428 Power Down Functionality CKPWRGD#/PD Differential Single-ended Single ended utputs utputs utputs w/latch HI-Z Low Low 2 Running. Hi-Z on the differential outputs will result in both True and Complement being low due to the termination network 2. These outputs are Hi-Z after VDD is applied and before the first assertion of CKPWRGD#. IDT 2 932SQ428 REV E 4232

3 Pin Descriptions PIN # PIN NAME TYPE DESCRIPTIN VDDXTAL PWR 3.3V power for the crystal oscillator. 2 GNDPCI PWR Ground pin for PCI outputs and logic. 3 PCI4_2x UT 3.3V PCI clock output 4 PCI3_2x UT 3.3V PCI clock output 5 PCI2_2x UT 3.3V PCI clock output 6 PCI_2x UT 3.3V PCI clock output 7 PCI_2x UT 3.3V PCI clock output 8 VDDPCI PWR 3.3V power for the PCI outputs and logic 9 VDD48 PWR 3.3V power for the 48MHz output and logic 48M_2x UT 3.3V 48MHz output GND48 PWR Ground pin for 48MHz output and logic. 2 GND96 PWR Ground pin for DT96 output and logic. 3 DT96T UT True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 4 DT96C UT Complementary clock of differential 96MHz output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 5 VDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic 6 CKPWRGD#/PD IN CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 7 VDDSRC PWR 3.3V power for the SRC outputs and logic 8 SRCT UT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 9 SRCC UT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 2 GNDSRC PWR Ground pin for SRC outputs and logic. 2 SRCC UT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 22 SRCT UT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 23 SRCC2 UT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 24 SRCT2 UT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 25 VDDSRC PWR 3.3V power for the SRC outputs and logic 26 AVDDSRC PWR 3.3V power for the SRC PLL analog circuits 27 GNDSRC PWR Ground pin for SRC outputs and logic. 28 IREF UT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 29 NS_SASC UT Complementary clock of differential non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 3 NS_SAST UT True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 3 VDDNS PWR 3.3V power for the Non-Spreading differential outputs outputs and logic 32 GNDNS PWR Ground pin for non-spreading differential outputs and logic. 33 NS_SASC UT Complementary clock of differential non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 34 NS_SAST UT True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. IDT 3 932SQ428 REV E 4232

4 Pin Descriptions (cont.) 35 AVDDNS PWR 3.3V power for the non-spreading SAS PLL analog circuits. 36 GNDNS PWR Ground pin for non-spreading differential outputs and logic. 37 VDD PWR 3.3V power for core logic 38 GND PWR Ground pin for core logic. 39 SMBDATA I/ Data pin of SMBUS circuitry, 5V tolerant 4 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 4 GND4 PWR Ground pin for 4MHz output and logic. 42 AVDD4 PWR Analog power pin for 4MHz PLL 43 VDD4 PWR Power pin for 4MHz output and logic, nominal 3.3V 44 REF4_3x UT 4.38 MHz reference clock. 3X drive strength as default 45 GND4 PWR Ground pin for 4MHz output and logic. 46 GNDXTAL PWR Ground pin for Crystal scillator. 47 X_25 IN Crystal input, Nominally 25.MHz. 48 X2_25 UT Crystal output, Nominally 25.MHz. IDT 4 932SQ428 REV E 4232

5 Test Loads and Recommended Terminations 932SQ SQ42 Differential Test Loads Rs Rs Rp Rp Differential Zo 2pF 2pF Differential utput Termination Table DIF Zo (Ω) Iref (Ω) Rs (Ω) Rp (Ω) or 43.2 HSCL utput Buffer Single-ended utput Termination Table Rs Value (for each load) utput Loads Zo = 5Ω Zo =6Ω PCI/ USB PCI/ USB REF REF REF 3 2 IDT 5 932SQ428 REV E 4232

6 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES 3.3V Core Supply Voltage VDDA 4.6 V,2 3.3V Logic Supply Voltage VDD 4.6 V,2 Input Low Voltage V IL GN D-.5 V Input High Voltage V IH Except for SMBus interface V DD +.5V V Input High Voltage V IH SMB SMBus clock and data pins 5.5V V Storage Temperature Ts C Junction Temperature Tj 25 C Input ESD protection ESD prot Human Body Model 2 V Guaranteed by design and characterization, not % tested in production. 2 peration under these conditions is neither implied nor guaranteed. Electrical Characteristics - Current Consumption TA = T CM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES All outputs C L perating Supply Current I DD3.3P 25 3 ma = Full load; Powerdown Current I DD 3.3PD Z All differential pairs tri-stated 2 2 ma Guaranteed by design and characterization, not % tested in production. DC Electrical Characteristics - Differential Current Mode utputs T A = T CM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Slew rate Trf Scope averaging on V/ns, 2, 3 Slew rate matching ΔTrf Slew rate matching, Scope averaging on 9 2 %, 2, 4 Rise/Fall Time Variation ΔTrf Rise/fall variation, Scope averaging off 8 25 ps, 7, 8 Voltage High VHigh Statistical measurement on mv Voltage Low VLow single-ended signal using Max Voltage Vmax Measurement on single ended 8 5, 7 mv Min Voltage Vmin signal using absolute value. -3-7, 7 Vswing Vswing Scope averaging off mv, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off mv, 5 Crossing Voltage (var) Δ-Vcross Scope averaging off 24 4 mv, 6 Guaranteed by design and characterization, not % tested in production. IREF = VDD/(3xR R ). For R R = 475Ω (%), I REF = 2.32mA. I H = 6 x I REF and V H Z =5Ω (Ω differential impedance). 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential V. This results in a +/-5mV window around differential V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. 7 Includes overshoot and undershoot. IDT 6 932SQ428 REV E 4232

7 Electrical Characteristics - Input/Supply/Common Parameters TA = T CM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Ambient perating Temperature T CM Commmercial range 7 C Input High Voltage V IH SMBus, low threshold and trilevel Single-ended inputs, except inputs Input Low Voltage V IL SMBus, low threshold and trilevel Single-ended inputs, except inputs 2 V DD +.3 V GND V I IN Single-ended inputs, V IN = GND, V IN = VDD -5 5 ua Input Current Single-ended inputs. V IN = V; Inputs with internal pullup I INP resistors -2 2 ua V IN = VDD; Inputs with internal pull-down resistors Low Threshold Input- High Voltage V IH _FS 3.3 V +/-5%.7 V DD +.3 V Low Threshold Input- Low Voltage V IL_FS 3.3 V +/-5% V SS V Input Frequency F i 25. MHz 2 Pin Inductance L p in 7 nh C IN Logic Inputs 5 pf Capacitance C UT utput pin capacitance 5 pf C INX X & X2 pins 5 pf Clk Stabilization T STAB input clock stabilization or deassertion.8 ms,2 From V DD Power-Up and after of PD# to st clock Allowable Frequency SS Modulation Frequency f MDIN (Triangular Modulation) khz Differential output enable after Tdrive_PD# t DR VPD PD# de-assertion 2. 3 us,3 Tfall t F Fall time of control inputs 5 ns,2 Trise t R Rise time of control inputs 5 ns,2 SMBus Input Low Voltage V ILSMB.8 V SMBus Input High Voltage V IH SMB 2. V DDSMB V SMBus utput Low Voltage V I PULLUP.4 V SMBus Sink Current I V L 4 ma Nominal Bus Voltage V DDSM B 3V to 5V +/- % V (Max VIL -.5) to (Min VIH + SCLK/SDATA Rise Time t RSMB.5) ns (Min VIH +.5) to (Max VIL - SCLK/SDATA Fall Time t FSMB.5) 3 ns SMBus perating Maximum SMBus operating f MAXSMB Frequency frequency khz Guaranteed by design and characterization, not % tested in production. 2 Control input must be monotonic from 2% to 8% of input swing. 3 Time from deassertion until outputs are >2 mv IDT 7 932SQ428 REV E 4232

8 AC Electrical Characteristics - Differential Current Mode utputs TA = T CM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Measured differentially, PLL Duty Cycle t DC Mode % Across all SRC outputs, Skew, utput to utput t sk3src V T = 5% ps Jitter, Cycle to cycle t jcyc- cyc SRC, NS_SAS outputs 35 5 ps,3 DT96 output ps,3 Guaranteed by design and characterization, not % tested in production. 2 I REF = V DD/(3xR R). For R R = 475Ω (%), I REF = 2.32mA. I H = 6 x I REF and V H Z =5Ω. 3 Measured from differential waveform Electrical Characteristics - Phase Jitter Parameters T A = - 7 C; Supply Voltage V DD/ V DDA = 3.3 V +/-5%, PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes t jphpcieg PCIe Gen ps (p-p),2,3,6 PCIe Gen 2 Lo Band ps.9 3,2,6 khz < f <.5MHz (rms) t jphpcieg2 PCIe Gen 2 High Band ps.7 3.,2,6.5MHz < f < Nyquist (5MHz) (rms) Phase Jitter PCIe Gen 3 t jphpcieg3 (PLL BW of 2-4MHz, CDR = MHz) QPI & SMI (MHz or 33MHz, 4.8Gb/s, 6.4Gb/s 2UI) t jphqpi_smi QPI & SMI (MHz, 8.Gb/s, 2UI) QPI & SMI (MHz, 9.6Gb/s, 2UI) SAS2G t jphsas2g (Filtered REFCLK Jitter 2KHz to 2MHz.) t jphsas2g SAS 2G.7.3 Guaranteed by design and characterization, not % tested in production. 2 See for complete specs 3 Sample size of at least K cycles. This figures extrapolates to 8ps M cycles for a BER of Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v Applies to SRC outputs 7 Applies to NS_SAS, NS_SRC outputs, Spread ff 8 Intel calculation from raw phase noise data ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms),2,4,6,5,6,5,6,5,6,7,8,5,7 IDT 8 932SQ428 REV E 4232

9 Electrical Characteristics - PCI T A = - 7 C; Supply Voltage V DD / V DD A = 3.3 V +/-5%, PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES utput Impedance R DSP V = V DD *(.5) 2 55 Ω utput High Voltage V H I H = - ma 2.4 V utput Low Voltage V L I L = ma.55 V utput High Current utput Low Current I H I L H =. V -33 ma H = 3.35 V -33 ma L =.95 V 3 ma V L =.4 V 38 ma Clock High Time T HIGH.5V 2 ns Clock Low Time T LW.5V 2 ns Edge Rate t slewr/f Rising/Falling edge rate.8 4 V/ns,2 Duty Cycle d t V T =.5 V % Group Skew t skew V T =.5 V ps Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 8 5 ps See "Single-ended Test Loads Page" for termination circuits Guaranteed by design and characterization, not % tested in production. 2 Measured between.8v and 2.V Electrical Characteristics - 48MHz T A = - 7 C; Supply Voltage V DD / V DD A = 3.3 V +/-5%, PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES utput Impedance R DSP V = V DD *(.5) 2 6 Ω utput High Voltage V H I H = - ma 2.4 V utput Low Voltage V L I L = ma.55 V utput High Current utput Low Current I H I L H =. V -29 ma H = 3.35 V -33 ma L =.95 V 29 ma V L =.4 V 27 ma Clock High Time T HIGH.5V ns Clock Low Time T LW.5V ns Edge Rate t slewr/f_usb Rising/Falling edge rate.5 2 V/ns,2 Duty Cycle d t V T =.5 V % Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 9 35 ps See "Single-ended Test Loads Page" for termination circuits Guaranteed by design and characterization, not % tested in production. 2 Measured between.8v and 2.V IDT 9 932SQ428 REV E 4232

10 Electrical Characteristics - REF T A = - 7 C; Supply Voltage V DD / V DD A = 3.3 V +/-5%, PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes utput Impedance R DSP V = V DD *(.5) 2 55 Ω utput High Voltage V H I H = - ma 2.4 V utput Low Voltage V L I L = ma.55 V utput High Current utput Low Current I H I L H =. V -33 ma H = 3.35 V -33 ma L =.95 V 3 ma V L =.4 V 38 ma Clock High Time T HIGH.5V 27.5 ns Clock Low Time T LW.5V 27.5 ns Edge Rate t slewr/f Rising/Falling edge rate.9 4 V/ns,2 Duty Cycle d t V T =.5 V % Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 75 ps See "Single-ended Test Loads Page" for termination circuits Guaranteed by design and characterization, not % tested in production. 2 Measured between.8v and 2.V IDT 932SQ428 REV E 4232

11 Clock AC Tolerances PPM tolerance Cycle to Cycle Jitter Spread SRC, NS_SAS PCI DT96 48MHz REF ppm ps -.5% -.5%.%.% % Clock Periods utputs with Spread Spectrum Disabled SSC N Center Freq. MHz Measurement Window Clock us.s.s.s us Clock -SSC - ppm + ppm +SSC -c2c jitter +c2c jitter Short-Term Long-Term ppm Period Long-Term Short-Term AbsPer AbsPer Average Average Nominal Average Average Min Max Min Min Max Max SRC, NS_SAS ns,2 PCI ns,2 DT ns,2 48MHz ns,2 REF ns,2 Clock Periods utputs with Spread Spectrum Enabled SSC N Center Freq. MHz Measurement Window Clock us.s.s.s us Clock -SSC - ppm + ppm +SSC -c2c jitter +c2c jitter Short-Term Long-Term ppm Period Long-Term Short-Term AbsPer AbsPer Average Average Nominal Average Average Min Max Min Min Max Max Units Notes Units Notes PCI ns,2 SRC ns,2 Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 4.388MHz. IDT 932SQ428 REV E 4232

12 General SMBus Serial Interface Information How to Write Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X- IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - ACK P stop bit X Byte SMBus write address = D2 hex SMBus read address = D3 hex How to Read Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X- IDT clock sends Byte through Byte X (if X (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address RD ReaD ACK N P ACK ACK Not acknowledge stop bit X Byte Data Byte Count=X Beginning Byte N Byte N + X - IDT 2 932SQ428 REV E 4232

13 SMBus Table: utput Enable Register Byte Pin # Name Control Function Type Default Bit 7 - DT96 Enable utput Enable RW Disable-Hi-Z Enable Bit 6 - NS_SAS Enable utput Enable RW Disable-Hi-Z Enable Bit 5 RESERVED NS_SAS Enable utput Enable RW Disable-Hi-Z Enable Bit 3 RESERVED SRC2 Enable utput Enable RW Disable-Hi-Z Enable Bit - SRC Enable utput Enable RW Disable-Hi-Z Enable Bit - SRC Enable utput Enable RW Disable-Hi-Z Enable SMBus Table: utput Enable Register Byte Pin # Name Control Function Type Default Bit 7 - REF4_3x Enable utput Enable RW Disable-Low Enable Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit RESERVED Bit SRC/PCI Spread Spectrum Enable Spread ff/n RW Spread ff Spread n SMBus Table: utput Enable Register Byte 2 Pin # Name Control Function Type Default Bit 7 RESERVED Bit 6 RESERVED Bit 5 - PCI4 Enable utput Enable RW Disable-Low Enable PCI3 Enable utput Enable RW Disable-Low Enable Bit 3 - PCI2 Enable utput Enable RW Disable-Low Enable PCI Enable utput Enable RW Disable-Low Enable Bit - PCI Enable utput Enable RW Disable-Low Enable Bit - 48MHz Enable utput Enable RW Disable-Low Enable Byte 3 ~ Byte 4 Reserved Register SMBus Table: NS_SAS Frequency Margining Table Byte 5 Pin # Name Control Function Type Default Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED FS4 Freq. Sel 4 RW Bit 3 - FS3 Freq. Sel 3 RW FS2 Freq. Sel 2 RW See NS_SAS Frequency Table Bit - FS Freq. Sel RW Bit - FS Freq. Sel RW SMBus Table: SRC/PCI Frequency Select Register Byte 6 Pin # Name Control Function Type Default Bit 7 - RESERVED Bit 6 - RESERVED Bit 5 - RESERVED RESERVED Bit 3 - FS3 Freq. Sel 3 RW FS2 Freq. Sel 2 RW See SRC/PCI Frequency Bit - FS Freq. Sel RW Select Table Bit - FS Freq. Sel RW IDT 3 932SQ428 REV E 4232

14 SMBus Table: Vendor & Revision ID Register Byte 7 Pin # Name Control Function Type Default Bit 7 - RID3 R Bit 6 - RID2 R REVISIN ID for A rev Bit 5 - RID R RID R Bit 3 - VID3 R VID2 R VENDR ID for ICS/IDT Bit - VID R Bit - VID R SMBus Table: Byte Count Register Byte 8 Pin # Name Control Function Type Default Bit 7 - BC7 RW Bit 6 - BC6 RW Bit 5 - BC5 RW Writing to this register will BC4 Byte Count RW configure how many bytes will Bit 3 - BC3 Programming b(7:) RW be read back, default is A BC2 RW bytes ( to 9) Bit - BC RW Bit - BC RW SMBus Table: Device ID Register Byte 9 Pin # Name Control Function Type Default Bit 7 DID7 R - - Bit 6 DID6 R - - Bit 5 DID5 R - - Bit 4 DID4 Device ID R - - Bit 3 DID3 (7 hex) R - - Bit 2 DID2 R - - Bit DID R - - Bit DID R - - SMBus Table: M/N Programming & Control Register Byte Pin # Name Control Function Type Default Bit 7 - M/N_EN SRC M/N Programming RW Disable Enable Enable Bit 6 - RESERVED Bit 5 - RESERVED RESERVED Bit 3 - RESERVED RESERVED Bit - RESERVED Bit - RESERVED SMBus Table: SRC/PCI Frequency Control Register Byte Pin # Name Control Function Type Default Bit 7 - SRC N Div8 N Divider Prog bit 8 RW The decimal representation of X Bit 6 - SRC N Div9 N Divider Prog bit 9 RW M and N Divider in Byte X Bit 5 - SRC M Div5 RW and 2 will configure the SRC X SRC M Div4 RW VC frequency. Default at X Bit 3 - SRC M Div3 M Divider Programming RW power up = latch-in or Byte 6 X SRC M Div2 bit (5:) RW Rom table. VC Frequency = X Bit - SRC M Div RW 25 x [NDiv(9:)+8] / X Bit - SRC M Div RW [MDiv(5:)+2] X IDT 4 932SQ428 REV E 4232

15 SMBus Table: SRC Frequency Control Register Byte 2 Pin # Name Control Function Type Default Bit 7 - SRC N Div7 RW The decimal representation of X Bit 6 - SRC N Div6 RW M and N Divider in Byte X Bit 5 - SRC N Div5 RW and 2 will configure the SRC X N Divider Programming SRC N Div4 RW VC frequency. Default at X Byte2 bit(7:) and Bit 3 - SRC N Div3 RW power up = latch-in or Byte 6 X Byte bit(7:6) SRC N Div2 RW Rom table. VC Frequency = X Bit - SRC N Div RW 25 x [NDiv(9:)+8] / X Bit - SRC N Div RW [MDiv(5:)+2] X SMBus Table: SRC Spread Spectrum Control Register Byte 3 Pin # Name Control Function Type Default Bit 7 - SRC SSP7 RW X Bit 6 - SRC SSP6 RW X Bit 5 - SRC SSP5 RW X These Spread Spectrum bits in SRC SSP4 Spread Spectrum RW X Byte 3 and 4 will program Bit 3 - SRC SSP3 Programming bit(7:) RW X the spread pecentage of SRC SRC SSP2 RW X Bit - SRC SSP RW X Bit - SRC SSP RW X SMBus Table: SRC Spread Spectrum Control Register Byte 4 Pin # Name Control Function Type Default Bit 7 - Reserved Bit 6 - SRC SSP4 RW X Bit 5 - SRC SSP3 RW X SRC SSP2 RW These Spread Spectrum bits in X Spread Spectrum Bit 3 - SRC SSP RW Byte 3 and 4 will program X Programming bit(4:8) SRC SSP RW the spread pecentage of SRC X Bit - SRC SSP9 RW X Bit - SRC SSP8 RW X SMBus Table: NS_SAS Frequency Control Register Byte 5 Pin # Name Control Function Type Default Bit 7 - NS_SAS N Div8 N Divider Prog bit 8 RW The decimal representation of X Bit 6 - NS_SAS N Div9 N Divider Prog bit 9 RW M and N Divider in Byte 5 X Bit 5 - NS_SAS M Div5 RW and 6 will configure the X NS_SAS M Div4 RW NS_SAS VC frequency. X M Divider Programming Bit 3 - NS_SAS M Div3 RW Default at power up = latch-in X bits (Fixed at for Rev NS_SAS M Div2 RW or Byte Rom table. VC X D) Bit - NS_SAS M Div RW Frequency = 25 x X Bit - NS_SAS M Div RW [NDiv(9:)+8] / [MDiv(5:)+2] X SMBus Table: NS_SAS Frequency Control Register Byte 6 Pin # Name Control Function Type Default Bit 7 - NS_SAS N Div7 RW The decimal representation of X Bit 6 - NS_SAS N Div6 RW M and N Divider in Byte 5 X Bit 5 - NS_SAS N Div5 RW and 6 will configure the X NS_SAS N Div4 N Divider Programming RW NS_SAS VC frequency. X Bit 3 - NS_SAS N Div3 b(7:) RW Default at power up = latch-in X NS_SAS N Div2 RW or Byte Rom table. VC X Bit - NS_SAS N Div RW Frequency = 25 x X Bit - NS_SAS N Div RW [NDiv(9:)+8] / [MDiv(5:)+2] X IDT 5 932SQ428 REV E 4232

16 SRC/PCI Frequency Selection Table Line Byte, Bit Spread Enable Byte6 Bit3 FS3 Byte6 Bit2 FS2 Byte6 Bit FS Byte6 Bit FS SRC (MHz) PCI (MHz) Spread % % -.5% IDT 6 932SQ428 REV E 4232

17 Line Byte5 Bit4 FS4 NS_SAS Margining Table Byte5 Bit3 FS3 Byte5 Bit2 FS2 Byte5 Bit FS Byte5 Bit FS NS_xxx (MHz) NTE: peration at other than the default entry is not guaranteed. These values are for margining purposes only. IDT 7 932SQ428 REV E 4232

18 DIF Reference Clock Common Recommendations for Differential Routing Dimension or Value Unit Figure L length, route as non-coupled 5ohm trace.5 max inch L2 length, route as non-coupled 5ohm trace.2 max inch L3 length, route as non-coupled 5ohm trace.2 max inch Rs 33 ohm Rt 49.9 ohm Down Device Differential Routing L4 length, route as coupled microstrip ohm differential trace 2 min to 6 max inch L4 length, route as coupled stripline ohm differential trace.8 min to 4.4 max inch Differential Routing to PCI Express Connector L4 length, route as coupled microstrip ohm differential trace.25 to 4 max inch 2 L4 length, route as coupled stripline ohm differential trace.225 min to 2.6 max inch 2 Figure : Down Device Routing L L2 Rs L4 L4' L' L2' HCSL utput Buffer Rs Rt Rt PCI Express Down Device REF_CLK Input L3' L3 Figure 2: PCI Express Connector Routing L L2 Rs L4 L4' L' L2' HCSL utput Buffer Rs Rt Rt PCI Express Add-in Board REF_CLK Input L3' L3 IDT 8 932SQ428 REV E 4232

19 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R R2 R3 R4 Note.45v.22v none ICS8743i-2 input compatible Standard LVDS Ra = Rb = R R2a = R2b = R2 Figure 3 L Ra L2 R3 L4 R4 L4' L' L2' HCSL utput Buffer Rb R2a R2b Down Device REF_CLK Input L3' L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b K 5% Cc. µf Vcm.35 volts Figure Volts Cc L4 R5a R5b Cc L4' R6a R6b PCIe Device REF_CLK Input IDT 9 932SQ428 REV E 4232

20 Package utline and Package Dimensions (48-pin MLF) IDT 2 932SQ428 REV E 4232

21 Marking Diagram ICS 32SQ428AL YYWW C LT Notes:. L denotes RoHS compliant package. 2. YYWW is the date code. 3. C is the country of origin. 4. LT is the lot number. rdering Information Part / rder Number Shipping Packaging Package Temperature 932SQ428AKLF Tray 48-pin MLF to +7 C 932SQ428AKLFT Tape and Reel 48-pin MLF to +7 C "LF" suffix to the part number are the Pb-Free configuration, RoHS compliant. A is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Revision History Rev. Issue Date Who Description Page # A 4/5/2 RDW Updated Idd, phase jitter, minor typo corrections; released to final Updated Power Down Functionality table to clarify functionality of singleended B 7/26/2 RDW outputs in power down. C 2/8/2 RDW. Updated Phase Jitter Table to correct typo in "Conditions" column for SAS. 8, 2 2. Mark spec added. D 4/3/22 AT Typo on pin 4 description. Pin type states UT; should be IN 4 E 4/23/22 RDW Updated Rp values on utput Terminations Table from 43.2 ohms to 42.2 or 43.2 ohms to be consistent with Intel. 5 IDT 2 932SQ428 REV E 4232

22 SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Integrated Device Technology, Inc. 2 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA