2-output 3.3V PCIe Clock Generator

Transcription

1 2-output 3.3V PCIe Clock Generator 9FGL2 Description The 9FGL2 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family. The devices have 2 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. The 9FGL2 supports PCIe Gen-4 Common Clocked architectures (CC) and PCIe Separate Reference no-spread (SRnS) and Separate Reference Independent Spread (SRIS) clocking architectures. The 9FGL2P can be programmed with a user-defined power up default SMBus configuration. Recommended Application PCIe Gen-4 clock generation for Riser Cards, Storage, Networking, JBD, Communications, Access Points utput Features 2 MHz Low-Power HCSL (LP-HCSL) DIF pairs 9FGL24 default ZUT = 9FGL25 default ZUT = 85 9FGL2P factory programmable defaults - 3.3V LVCMS REF output w/wake-n-lan (WL) support Easy AC-coupling to other logic families, see IDT application note AN-89 Key Specifications PCIe Gen CC-compliant PCIe Gen2-3 SRIS-compliant DIF cycle-to-cycle jitter <5ps DIF output-to-output skew <5ps DIF 2k-2M phase jitter is <2ps rms when SSC is off REF phase jitter is <3fs rms (SSC off) and <.5ps RMS (SSC on) ±ppm frequency accuracy on all clocks Block Diagram y DATASHEET Features/Benefits Direct connection to (xx4) or 85 (xx5) transmission lines; saves 8 resistors compared to standard PCIe devices 2mW typical power consumption (@3.3V); eliminates thermal concerns SMBus-selectable features allows optimization to customer requirements: control input polarity control input pull up/downs slew rate for each output 33, 85 or Ω output impedance for each output spread spectrum amount input frequency 4 and 5 devices contain default configuration; SMBus interface not required for device operation P device allows factory programming of customer-defined input/output frequencies and SMBus power up default; allows exact optimization to customer requirements E# pins; support DIF power management 8MHz - 4MHz input frequency with 9FGL2P device (25MHz default); flexibility Pin/SMBus selectable %, -.25% or -.5% spread on DIF outputs; minimize EMI and phase jitter for each application DIF outputs blocked until PLL is locked; clean system start-up Two selectable SMBus addresses; multiple devices can easily share an SMBus segment Space saving 24-pin 4x4mm VFQFPN; minimal board space ve(:)# IN/CLKIN_25 2 REF JA4I 25MHz 2 vsadr vss_en_tri ^CKPWRGD_PD# SDATA_3.3 Control Logic SSC Capable PLL DIF DIF SCLK_3.3 Note: Resistors default to internal on 4/5 devices. P devices have programmable default impedances on an output-by-output basis. 9FGL2 DECEMBER, Integrated Device Technology, Inc.

2 Pin Configuration IN/CLKIN_ VDDTAL3.3 3 vsadr/ref3.3 4 GNDREF 5 GNDDIG 6 GNDTAL vss_en_tri ^CKPWRGD_PD# GND VDD3.3 ve# FGL2xx epad is GND VDDDIG3.3 SCLK_3.3 SDATA_3.3 GND VDD3.3 ve# 8 DIF# 7 DIF 6 VDDA3.3 5 GNDA 4 DIF# 3 DIF SMBus Address Selection Table 24-pin VFQFPN, 4x4 mm,.5mm pitch ^ prefix indicates internal 2Khm pull up resistor v prefix indicates internal 2Khm pull down resistor State of SADR on first application of CKPWRGD_PD# Power Management Table SADR Address + Read/Write Bit x x CKPWRGD_PD# SMBus E bit True /P DIF Comp. /P REF Low Low Hi-Z 2 Running Running Running Disabled Disabled Running Disabled Disabled Disabled 4. The output state is set by B[:] (Low/Low default) 2. REF is Hi-Z until the st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is disabled unless Byte3[5]=, in which case REF is running.. 3. Input polarities defined at default values for 9FGLxx4/xx5. 4. See SMBus description for Byte 3, bit 4 Power Connections Pin Number VDD GND Description 3 5,24 TAL, REF 7 6 Digital Power,2,2,25 DIF outputs 6 5 PLL Analog 2-UTPUT 3.3V PCIE CLCK GENERATR 2 DECEMBER, 26

3 Pin Descriptions Pin# Pin Name Type Pin Description IN/CLKIN_25 IN Crystal input or Reference Clock input. Nominally 25MHz. 2 2 UT Crystal output. 3 VDDTAL3.3 PWR Power supply for TAL, nominal 3.3V 4 vsadr/ref3.3 LATCHED I/ Latch to select SMBus Address/3.3V LVCMS copy of /REFIN pin 5 GNDREF GND Ground pin for the REF outputs. 6 GNDDIG GND Ground pin for digital circuitry 7 VDDDIG3.3 PWR 3.3V digital power (dirty power) 8 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 9 SDATA_3.3 I/ Data pin for SMBus circuitry, 3.3V tolerant. GND GND Ground pin. VDD3.3 PWR Power supply, nominal 3.3V 2 ve# IN Active low input for enabling DIF pair. This pin has an internal pull-down. =disable outputs, = enable outputs 3 DIF UT Differential true clock output 4 DIF# UT Differential Complementary clock output 5 GNDA GND Ground pin for the PLL core. 6 VDDA3.3 PWR 3.3V power for the PLL core. 7 DIF UT Differential true clock output 8 DIF# UT Differential Complementary clock output 9 ve# IN Active low input for enabling DIF pair. This pin has an internal pull-down. =disable outputs, = enable outputs 2 VDD3.3 PWR Power supply, nominal 3.3V 2 GND GND Ground pin. 22 ^CKPWRGD_PD# IN Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 23 vss_en_tri Latched select input to select spread spectrum amount at initial power up : LATCHED IN = -.5% spread, M = -.25%, = Spread ff 24 GNDTAL GND GND for TAL 25 epad GND Connect to ground DECEMBER, UTPUT 3.3V PCIE CLCK GENERATR

4 Test Loads Low-Power Differential utput Test Load Rs Rs 5 inches Zo=ohm 2pF 2pF Terminations Device Zo (Ω) Rs (Ω) 9FGL24 None needed 9FGL FGL2P Prog. 9FGL24 85 N/A 9FGL25 85 None needed 9FGL2P 85 Prog. Note: The device can drive transmission line lengths greater than those specified by the PCIe SIG REF utput Test Load Zo = 5 ohms 33 5pF REF utput Alternate Terminations The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See AN-89 Driving LVPECL, LVDS, and CML Logic with IDT's "Universal" Low-Power HCSL utputs for details. 2-UTPUT 3.3V PCIE CLCK GENERATR 4 DECEMBER, 26

5 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9FGL2. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBL CNDITINS MIN TYP MA UNITS NTES Supply Voltage VDDx V,2 Input Voltage V IN -.5 V DD +.5 V,3 Input High Voltage, SMBus V IHSMB SMBus clock and data pins 3.9 V Storage Temperature Ts C Junction Temperature Tj 25 C Input ESD protection ESD prot Human Body Model 25 V Guaranteed by design and characterization, not % tested in production. 2 peration under these conditions is neither implied nor guaranteed. 3 Not to exceed 4.6V. Electrical Characteristics SMBus Parameters TA = T AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MA UNITS NTES SMBus Input Low Voltage V ILSMB V DDSMB = 3.3V.8 V SMBus Input High Voltage V IHSMB V DDSMB = 3.3V V SMBus utput Low Voltage V I PULLUP.4 V SMBus Sink Current I V L 4 ma Nominal Bus Voltage V DDSMB V SCLK/SDATA Rise Time t RSMB (Max VIL -.5) to (Min VIH +.5) ns SCLK/SDATA Fall Time t FSMB (Min VIH +.5) to (Max VIL -.5) 3 ns SMBus perating Frequency f SMB SMBus operating frequency 5 khz 2 Guaranteed by design and characterization, not % tested in production. 2. The device must be powered up for the SMBus to function. DECEMBER, UTPUT 3.3V PCIE CLCK GENERATR

6 Electrical Characteristics Input/Supply/Common Parameters Normal perating Conditions TA = T AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MA UNITS NTES Supply Voltage Ambient perating Temperature VDDxxx T AMB Supply voltage for core, analog and singleended LVCMS outputs V Commmercial range 25 7 C Industrial range C Input High Voltage V IH Single-ended inputs, except SMBus.75 V DDx V DDx +.3 V Input Low Voltage V IL V DDx V Input High Voltage V IHtri.75 V DDx V DD +.3 V Input Mid Voltage V IMtri Single-ended tri-level inputs ('_tri' suffix).4 V DDx.5 V DDx.6 V DDx V Input Low Voltage V ILtri V DDx V I IN Single-ended inputs, V IN = GND, V IN = VDD -5 5 ua Single-ended inputs Input Current V IN = V; Inputs with internal pull-up resistors I INP V IN = VDD; Inputs with internal pull-down resistors -5 5 ua Input Frequency F in TAL, or input MHz 4 Pin Inductance L pin 7 nh Capacitance C IN Logic Inputs, except DIF_IN.5 5 pf C UT utput pin capacitance 6 pf Clk Stabilization T STAB From V DD Power-Up and after input clock stabilization or de-assertion of PD# to st clock.34.8 ms,2 Allowable Frequency SS Modulation Frequency f MD (Triangular Modulation) khz DIF start after E# assertion E# Latency t LATE# DIF stop after E# deassertion 3 clocks,3 DIF output enable after Tdrive_PD# t DRVPD PD# de-assertion 28 3 us,3 Tfall t F Fall time of single-ended control inputs 5 ns,2 Trise t R Rise time of single-ended control inputs 5 ns,2 Guaranteed by design and characterization, not % tested in production. 2 Control input must be monotonic from 2% to 8% of input swing. 3 Time from deassertion until outputs are >2 mv 4 The 9FGLxxP devices can be programmed for various input frequencies from 8 to 4MHz. The 9FGLxx4/5 devices use 25MHz. 2-UTPUT 3.3V PCIE CLCK GENERATR 6 DECEMBER, 26

7 Electrical Characteristics DIF Low-Power HCSL utputs TA = T AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MA UNITS NTES Slew rate Trf Scope averaging on, fast setting V/ns 2,3 Scope averaging, slow setting 2. 3 V/ns 2,3 Crossing Voltage (abs) Vcross_abs Scope averaging off mv,4,5 Crossing Voltage (var) Δ-Vcross Scope averaging off 4 4 mv,4,9 Avg. Clock Period Accuracy T PERID_AVG ppm 2,,3 Absolute Period T PERID_ABS Includes jitter and Spread Spectrum Modulation ns 2,6 Jitter, Cycle to cycle t jcyc-cyc 37 5 ps 2,5 Voltage High V HIGH mv Voltage Low V LW Absolute Max Voltage Vmax 797 5,7,5 mv Absolute Min Voltage Vmin -3-22,8,5 Duty Cycle t DC % 2 Slew rate matching ΔTrf 8 2 %,4 Skew, utput to utput t sk3 Averaging on, V T = 5% 2 5 ps 2 Measured from single-ended waveform. 2 Measured from differential waveform. 3 Measured from -5 mv to +5 mv on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 3 mv measurement window is centered on the differential zero crossing. 4 Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. 5 Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread spectrum modulation. 7 Defined as the maximum instantaneous voltage including overshoot. 8 Defined as the minimum instantaneous voltage including undershoot. 9 Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in V CRSS for any particular system. Refer to Section of the PCI Express Base Specification, Revision 3. for information regarding PPM considerations. System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL = 2 pf. 2 T STABLE is the time the differential clock must maintain a minimum ±5 mv differential voltage after rising/falling edges before it is allowed to droop back into the VRB ± mv differential range. 3 PPM refers to parts per million and is a DC absolute period accuracy specification. PPM is /,,th of. MHz exactly or Hz. For 3 PPM, then we have an error budget of Hz/PPM * 3 PPM = 3 khz. The period is to be measured with a frequency counter with measurement window set to ms or greater. The ±3 PPM applies to systems that do not employ Spread Spectrum Clocking, or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,5 PPM nominal shift in maximum period resulting from the.5% down spread resulting in a maximum average period specification of +2,8 PPM. 4 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mv window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not exceed 2% of the slowest edge rate. 5 At default SMBus amplitude settings. DECEMBER, UTPUT 3.3V PCIE CLCK GENERATR

8 Electrical Characteristics Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures T AMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MA INDUSTRY LIMIT t jphpcieg-cc PCIe Gen Phase Jitter PCIe Gen 2 Lo Band khz < f <.5MHz (PLL BW of 5-6MHz or 8-5MHz, CDR = 5MHz) t jphpcieg2-cc PCIe Gen 2 High Band.5MHz < f < Nyquist (5MHz) (PLL BW of 5-6MHz or 8-5MHz, CDR = 5MHz) PCIe Gen 3 t jphpcieg3-cc (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) PCIe Gen 4 t jphpcieg4-cc (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) Applies to all outputs. 2 Based on PCIe Base Specification Rev4. version.7draft. See for latest specifications. 3 Sample size of at least K cycles. This figures extrapolates to 8ps M cycles for a BER of Electrical Characteristics Filtered Phase Jitter Parameters - PCIe Separate Reference Independent Spread (SRIS) Architectures 3 UNITS ps (p-p) ps (rms) ps (rms) ps (rms) ps (rms) Notes,2,3,2,2,2,2 T AMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MA Phase Jitter, PLL Mode Applies to all outputs. t jphpcieg2- SRIS t jphpcieg3- SRIS PCIe Gen 2 (PLL BW of 6MHz, CDR = 5MHz) PCIe Gen 3 (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) INDUSTRY LIMIT UNITS ps (rms) ps (rms) Notes,2,2 2 Based on PCIe Base Specification Rev3.a. These filters are different than Common Clock filters. See for latest specifications. There is a proposal to reduce the PCIe Gen3 limit to.5ps. 3 As of PCIe Base Specification Rev4. draft.7, SRIS is not currently defined for Gen or Gen4. Electrical Characteristics DIF LP-HCSL utput Unfiltered Phase Jitter Parameters TA = T AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions INDUSTRY PARAMETER SYMBL CNDITINS MIN TYP MA LIMIT MHz outputs with REF output enabled Phase Jitter, 2k-2M t jph2k2m.5 2 N/A SSC ff UNITS ps (rms) 2-UTPUT 3.3V PCIE CLCK GENERATR 8 DECEMBER, 26

9 Electrical Characteristics Current Consumption TA = T AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MA UNITS NTES perating Supply Current Wake-on-LAN Current (Power down state and Byte 3, bit 5 = '') Powerdown Current (Power down state and Byte 3, bit 5 = '') I DDAP VDDA, All outputs 3 6 ma I DDP All VDD, except VDDA, All outputs 2 3 ma I DDAPD VDDA, DIF outputs off, REF output running.7.5 ma I DDPD All VDD, except VDDA, DIF outputs off, REF output running ma I DDAPD VDDA, all outputs off.7.5 ma I DDPD All VDD, except VDDA, all outputs off ma This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = ) Electrical Characteristics REF TA = T AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MA UNITS Notes Long Accuracy ppm see Tperiod min-max values ppm,2 Clock period T period REF output 4 ns 2 High output Voltage V HIGH I H = -2mA.8xV DDREF V Low output Voltage V LW I L = 2mA.2xV DDREF V t rf Byte 3 = F, V H =.8*VDD, V L =.2*VDD V/ns Rise/Fall Slew Rate t rf Byte 3 = 5F, VH =.8*VDD, VL =.2*VDD V/ns,3 t rf Byte 3 = 9F, VH =.8*VDD, VL =.2*VDD V/ns t rf Byte 3 = DF, VH =.8*VDD, VL =.2*VDD V/ns Duty Cycle d t V T = VDD/2 V %,4 Duty Cycle Distortion d tcd V T = VDD/2 V - %,5 Jitter, cycle to cycle t jcyc-cyc V T = VDD/2 V 7 5 ps,4 Noise floor Jitter, phase t jdbck t jphref khz offset 2kHz to 5MHz, DIF SSC ff dbc ps (rms),4,4 t jdbck t jphref khz offset to Nyquist 2kHz to 5MHz, DIF SSC n dbc ps (rms),4,4 Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25. MHz 3 Default SMBus Value 4 When driven by a crystal. 5 When driven by an external oscillator via the pin, 2 should be floating. DECEMBER, UTPUT 3.3V PCIE CLCK GENERATR

10 General SMBus Serial Interface Information How to Write Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+- IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = ACK Beginning Byte N ACK Byte N + - ACK P stop bit Byte Note: SMBus Read/Write Address is Latched on SADR pin. Unless otherwise indicated, default values are for the xx4 and xx5. P devices are fully factory programmable. How to Read Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = IDT clock sends Byte N+- IDT clock sends Byte through Byte (if (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address RD ReaD ACK N P ACK ACK Not acknowledge stop bit Byte Data Byte Count= Beginning Byte N Byte N UTPUT 3.3V PCIE CLCK GENERATR DECEMBER, 26

11 SMBus Table: utput Enable Register Byte Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DIF E utput Enable RW Low/Low Pin Control Bit DIF E utput Enable RW Low/Low Pin Control Bit. A low on these bits will overide the E# pin and force the differential output to the state indicated by B[:] (Low/Low default). SMBus Table: Spread Spectrum and Vhigh Control Register Byte Name Control Function Type Default Bit 7 SSENRB SS Enable Readback Bit R ' for SS_EN_tri =, '' for SS_EN_tri Latch Bit 6 SSENRB SS Enable Readback Bit R = 'M', ' for SS_EN_tri = '' Latch Bit 5 SSEN_SWCNTRL Enable SW control of SS RW SS controlled by latch (B[7:6]). Values in B[4:3] control SS amount. Bit 4 SSENSW SS Enable Software Ctl Bit RW ' = SS ff, '' = -.25% SS, Bit 3 SSENSW SS Enable Software Ctl Bit RW '' =, ''= -.5% SS Bit 2 Bit AMPLITUDE RW =.6V =.68V Controls utput Amplitude Bit AMPLITUDE RW =.75V =.85V. Spread must be selected FF or N with the hardware latch pin. These bits should not be used to turn spread N or FF after power up. These bits can be used to change the spread amount, and B[5] must be set to a for these bits to have any effect on the part. If These bits are used to turn spread FF or N, the system will need to be reset. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SLEWRATESEL DIF Adjust Slew Rate of DIF RW Slow Setting Fast Setting Bit SLEWRATESEL DIF Adjust Slew Rate of DIF RW Slow Setting Fast Setting Bit Note: See "Low-Power HCSL utputs" table for slew rates. SMBus Table: REF Control Register Byte 3 Name Control Function Type Default Bit 7 RW = Slowest = Slow REF Slew Rate Control Bit 6 RW = Fast = Faster Bit 5 REF Power Down Function Wake-on-Lan Enable for REF RW REF disabled in REF runs in Power Power Down Down Bit 4 REF E REF utput Enable RW Disabled Enabled Bit 3 Bit 2 Bit Bit Byte 4 is DECEMBER, 26 2-UTPUT 3.3V PCIE CLCK GENERATR

12 SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function Type Default Bit 7 RID3 R Bit 6 RID2 R Revision ID B rev = Bit 5 RID R Bit 4 RID R Bit 3 VID3 R Bit 2 VID2 R VENDR ID = IDT Bit VID R Bit VID R SMBus Table: Device Type/Device ID Byte 6 Name Control Function Type Default Bit 7 Device Type R = FGx, = DBx, Device Type Bit 6 Device Type R = DMx, = DBx w/opll Bit 5 Device ID5 R Bit 4 Device ID4 R Bit 3 Device ID3 R Device ID binary or 2 hex Bit 2 Device ID2 R Bit Device ID R Bit Device ID R SMBus Table: Byte Count Register Byte 7 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 BC4 RW Bit 3 BC3 RW Writing to this register will configure how Bit 2 BC2 Byte Count Programming RW many bytes will be read back, default is Bit BC RW = 8 bytes. Bit BC RW Bytes 8 and 9 are SMBus Table: PLL MN Enable, PD_Restore Byte Name Control Function Type Default Bit 7 Reserve bit, leave at default RW Bit 6 Power-Down (PD) Restore Restore Default Config. In PD RW Clear Config in PD Keep Config in PD Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit 2-UTPUT 3.3V PCIE CLCK GENERATR 2 DECEMBER, 26

13 SMBus Table: Stop State Control Byte Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit STP[] True/Complement DIF utput RW = Low/Low = High/Low Bit STP[] Disable State RW = HiZ/HiZ = Low/High SMBus Table: Impedance Control Byte 2 Name Control Function Type Default Bit 7 DIF_imp[] DIF Zout RW =33 DIF Zout = DIF Zout Bit 6 DIF_imp[] DIF Zout RW =85 DIF Zout = See Note Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit SMBus Table: Impedance Control Byte 3 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DIF_imp[] DIF Zout RW =33 DIF Zout = DIF Zout Bit 2 DIF_imp[] DIF Zout RW =85 DIF Zout = See Note Bit Bit SMBus Table: Pull-up Pull-down Control Byte 4 Name Control Function Type Default Bit 7 E_pu/pd[] E Pull-up(PuP)/ RW =None =Pup Bit 6 E_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit SMBus Table: Pull-up Pull-down Control Byte 5 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 E_pu/pd[] E Pull-up(PuP)/ RW =None =Pup Bit 2 E_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Bit Bit DECEMBER, UTPUT 3.3V PCIE CLCK GENERATR

14 SMBus Table: Pull-up Pull-down Control Byte 6 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit CKPWRGD_PD_pu/pd[] CKPWRGD_PD Pull-up(PuP)/ RW =None =Pup Bit CKPWRGD_PD_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Byte 7 is SMBus Table: Polarity Control Byte 8 Name Control Function Type Default Bit 7 Bit 6 Bit 5 E_polarity Sets E polarity RW Enabled when Low Enabled when High Bit 4 Bit 3 E_polarity Sets E polarity RW Enabled when Low Enabled when High Bit 2 Bit Bit SMBus Table: Polarity Control Byte 9 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit CKPWRGD_PD Determines Power Down when Power Down when RW CKPWRGD_PD polarity Low High 2-UTPUT 3.3V PCIE CLCK GENERATR 4 DECEMBER, 26

15 Recommended Crystal Characteristics (3225 package) PARAMETER VALUE UNITS NTES Frequency 25 MHz Resonance Mode Fundamental - Frequency 25 C ±2 PPM Max Frequency Stability, 25 C ver perating Temperature Range ±2 PPM Max Temperature Range (commerical) ~7 C Temperature Range (industrial) -4~85 C Equivalent Series Resistance (ESR) 5 Ω Max Shunt Capacitance (C ) 7 pf Max Load Capacitance (C L ) 8 pf Max Drive Level.3 mw Max Aging per year ±5 PPM Max Notes:. F Marking Diagrams LT 24BI YYWW LT 25BI YYWW LT B YYWW Notes:. LT is the lot sequence number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. Line 2: truncated part number 4. I denotes industrial temperature range device. 5. P denotes factory programmable defaults Thermal Characteristics PARAMETER SYMBL CNDITINS PKG TYP UNITS NTES VALUE θ JC Junction to Case 62 C/W θ Jb Junction to Base 5.4 C/W Thermal Resistance θ JA Junction to Air, still air 5 C/W NLG24 θ JA Junction to Air, m/s air flow 43 C/W θ JA3 Junction to Air, 3 m/s air flow 39 C/W θ JA5 Junction to Air, 5 m/s air flow 38 C/W epad soldered to board DECEMBER, UTPUT 3.3V PCIE CLCK GENERATR

16 Package utline and Package Dimensions (NLG24) 2-UTPUT 3.3V PCIE CLCK GENERATR 6 DECEMBER, 26

17 Package utline and Package Dimensions (NLG24), cont. DECEMBER, UTPUT 3.3V PCIE CLCK GENERATR

18 rdering Information Part / rder Number Shipping Packaging Package Temperature 9FGL24BKILF Trays 24-pin VFQFPN -4 to +85 C 9FGL24BKILFT Tape and Reel 24-pin VFQFPN -4 to +85 C 9FGL25BKILF Trays 24-pin VFQFPN -4 to +85 C 9FGL25BKILFT Tape and Reel 24-pin VFQFPN -4 to +85 C 9FGL2PBxxxKILF Trays 24-pin VFQFPN -4 to +85 C 9FGL2PBxxxKILFT Tape and Reel 24-pin VFQFPN -4 to +85 C LF suffix to the part number are the Pb-Free configuration and are RoHS compliant. B is the device revision designator (will not correlate with the datasheet revision). xxx is a unique factory assigned number to identify a particular default configuration. Revision History Rev. Issue Date Intiator Description Page #. Removed VDDI reference, this part does not have the feature 2. Clarified that the 9FGL4P device has 8MHz to 4MHz input C 4/2/26 RDW frequency range, and that the 9FGL44/45 use a 25MHz input. 3. Updated max IDD for case WL mode from ma to 4mA. 4. Corrected Stop State Control bit decode in Byte 5. Updated Amplitude Control Bit Decode in Byte D 6/3/26 RDW. Update electrical tables for B rev production release 2. Added PCIe SRIS and PCIe Gen4 CC to phase jitter tables. 3. Updated front page text. 4. Removed '' blank device from ordering information. Various 5. Updated Byte wording for clarity 6. Updated Byte[:] descriptions. E 6/22/26 RDW. Updated electrical tables with final data from PE/TE Various F /8/26 RDW. Removed IDT crystal part number G /3/26 RDW. Updated Byte and its footnote for clarity. 2-UTPUT 3.3V PCIE CLCK GENERATR 8 DECEMBER, 26

19 Corporate Headquarters 624 Silver Creek Valley Road San Jose, CA 9538 USA Sales or Fax: Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. ther trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 26 Integrated Device Technology, Inc.. All rights reserved.

20 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology): 9FGL2PAKILF 9FGL2PAKILFT