Freescale P10XX and P20XX System Clock with Selectable DDR Frequency

Transcription

1 Freescale PXX and P2XX System Clock with Selectable DDR Frequency 6V4925B DATASHEET Description The 6V4925B is a main clock for Freescale Pxx and P2xx-based systems. It has a selectable System CCB clock and 2 DDRCLK speeds M or 66.66M. The 6V4925B also provides LP-HCSL PCIe outputs for low-power and reduced board space. utput Features Sys_CCB 3.3V LVCMS output at M/83.33M/ 8M/66.66M DDRCLK 3.3V LVCMS output at M or 66.66M 25M 3.3V LVCMS output 6 LP-HCSL PCIe pairs selectable at M or 25M 6 25MHz 3.3V LVCMS outputs M 3.3V LVCMS outputs 2 USB 3.3V LVCMS outputs at 2M or 24M Key Specifications PCIe Gen-2-3 compliant < 3p rms phase noise on REF outputs Typical Applications System Clock for Freescale Pxx and P2xx-based designs Features Replaces crystals, 2 oscillators and 3 clock generators; lowers cost, power and area Integrated terminations on LP-HCSL PCIe outputs; eliminate 24 resistors, saving 4mm 2 of board area Industrial temperature range operation; supports demanding environmental conditions Advanced 3.3V CMS process; high-performance, low-power Supports independent spread spectrum on Sys_CCB/DDRCLK and PCIe outputs Available in space-saving 7 x 7 mm 48-VFQFPN with.5mm pad pitch; reduced board space without the need for fine-pitch assembly techniques Block Diagram SCLK SDATA ^FS ^FS ^SEL#_66 ^SELPCIE25#_ Control Logic PLL (SS) PLL4 (SS) MHz Sys_CCB DDRCLK PCIe_L(5:) 25MHz Crystal X X2 Crystal scillator PLL3 (non- SS) PLL2 (non- SS) USB_CLK(2:) 2.48M(:) 25M REF(5:) GND Note : For DDR Clock: Processor core and I/ supply rails must be ramped with VDD3P3 or earlier. Clock signal will be clamped LW and output clock will be MHz if this is not followed (see diagram below). VDD3P3 R4 K DDRCLK R39 K 6V4925B MAY 5, Integrated Device Technology, Inc.

2 Pin Assignments X2_25 48 VDDREF X_ SDATA GNDREF 3 46 SCLK REF GndDDR REF ^SEL#_66/DDRCLK REF VddDDR VDDREF 7 42 AVDDSYS GNDREF 8 4 Sys_CCB REF2 9 4 GNDSYS REF 39 GNDPCIe ^SELPCIE25#_/REF 38 PCIeT_LR5 AVDD2_ PCIeC_LR5 ^FS/USB_CLK 3 36 PCIeT_LR4 ^FS/USB_CLK PCIeC_LR4 GND2_ GNDPCIe GND AVDDPCIe CK2.48_ 7 32 PCIeT_LR3 CK2.48_ 8 3 PCIeC_LR3 VDD PCIeT_LR2 AVDD PCIeC_LR2 25M 2 28 GNDPCIe GND25M VDDPCIe PCIeT_LR23 26PCIeT_LR PCIeC_LR24 25PCIeC_LR 48-Pin TSSP ^ Indicates Internal kohm pull up resistor 6V4925B REF3 6 VDDREF 7 GNDREF 8 REF2 9 REF ^SELPCIE25#_/REF AVDD2_24 2 VDDREF SDATA SCLK GndDDR ^SEL#_66/DDRCLK VddDDR AVDDSYS Sys_CCB GNDSYS GNDPCIe PCIeT_LR5 PCIeC_LR X2_25 X_25 2 GNDREF 3 REF5 4 REF4 5 6V4925B PCIeT_LR4 35 PCIeC_LR4 34 GNDPCIe 33 AVDDPCIe 32 PCIeT_LR3 3 PCIeC_LR3 3 PCIeT_LR2 29 PCIeC_LR2 28 GNDPCIe 27 VDDPCIe 26 PCIeT_LR 25 PCIeC_LR ^FS/USB_CLK ^FS/USB_CLK2 GND2_24 GND2.48 CK2.48_ CK2.48_ VDD2.48 AVDD25 25M GND25M PCIeT_LR PCIeC_LR 48-Pin VFQFPN ^ Indicates Internal kohm pull up resistor FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY 2 MAY 5, 27

3 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTIN X2_25 UT Crystal output, Nominally 25.MHz. 2 X_25 IN Crystal input, Nominally 25.MHz. 3 GNDREF PWR Ground pin for the REF outputs. 4 REF5 UT Copy of crystal input 5 REF4 UT Copy of crystal input 6 REF3 UT Copy of crystal input 7 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 8 GNDREF PWR Ground pin for the REF outputs. 9 REF2 UT Copy of crystal input REF UT Copy of crystal input Latched input to select the PCIe output frequency/ref output. ^SELPCIE25#_/RE I/ = 25M F = M 2 AVDD2_24 PWR Power for 2_24MHz PLL core, and outputs. Nominal 3.3V 3 ^FS/USB_CLK I/ Frequency select latch for Sys_CCB / 2 or 24MHz USB clock output. 3.3V. This pin has an internal pull up resistor. 4 ^FS/USB_CLK2 I/ Frequency select latch for Sys_CCB / 2 or 24MHz USB clock output. 3.3V. This pin has an internal pull up resistor. 5 GND2_24 PWR Ground pin for 2_24M outputs. 6 GND2.48 PWR Ground pin for 2.48M outputs. 7 CK2.48_ UT 2.48M output, nominal 3.3V. 8 CK2.48_ UT 2.48M output, nominal 3.3V. 9 VDD2.48 PWR Power supply for 2.48M outputs, nominal 3.3V. 2 AVDD25 PWR Power for 25MHz PLL core and output, nominal 3.3V 2 25M UT 25M output, nominal 3.3V. 22 GND25M PWR Ground pin for 25M outputs. 23 PCIeT_LR UT True clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 24 PCIeC_LR UT Complement clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 25 PCIeC_LR UT Complement clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 26 PCIeT_LR UT True clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 27 VDDPCIe PWR Power supply for PCI Express outputs, nominal 3.3V 28 GNDPCIe PWR Ground pin for the PCIe outputs. 29 PCIeC_LR2 UT Complement clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 3 PCIeT_LR2 UT True clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 3 PCIeC_LR3 UT Complement clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 32 PCIeT_LR3 UT True clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 33 AVDDPCIe PWR Analog Power supply for PCI Express clocks, nominal 3.3V 34 GNDPCIe PWR Ground pin for the PCIe outputs. 35 PCIeC_LR4 UT Complement clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 36 PCIeT_LR4 UT True clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 37 PCIeC_LR5 UT Complement clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 38 PCIeT_LR5 UT True clock of.8v differential push-pull PCI_Express pair with integrated 33ohm series resistor 39 GNDPCIe PWR Ground pin for the PCIe outputs. 4 GNDSYS PWR Ground pin for the Sys_CCB output 4 Sys_CCB UT System CCB clock output 42 AVDDSYS PWR Analog Power supply for Sys_CCB clock and outputs, nominal 3.3V 43 VddDDR PWR Power supply for DDR Clock output, nominal 3.3V 44 ^SEL#_66/DDRCLK I/ Latched input to select the DDR output frequency/ddrclk output. See note regarding system power sequencing. = M = M 45 GndDDR PWR Ground pin for the DDR outputs. 46 SCLK IN Clock pin of SMBus circuitry. 47 SDATA I/ Data pin for SMbus circuitry. 48 VDDREF PWR Ref, XTAL power supply, nominal 3.3V MAY 5, 27 3 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

4 Table : PCIEX Spread Table (selectable via SMBUS) SELPCIE25#_ B6b4 Bb4 Bb3 Spread % (25MHz) x x No Spread (MHz) No Spread (default) (MHz) Down -.5% (MHz) Down -.75% (MHz) No Spread *nce in spread mode, do not return to non spread without reset Table 2: Sys_CCB and DDR Spread Table (selectable via SMBUS) Bb7 Bb6 Bb5 Spread % No Spread (default) Down -.5% Down -.75% Down -.25% Down -% Down -.25% Down -.5% Down -2% Table 3: Sys_CCB Frequency Select Table (Latched and selectable via SMBUS) FS / B4b3 FS / B4b2 Sys_CCB (MHz) Table 4: PCI Express Amplitude Control B6b7 B6b6 PCIe Amplitude 7mV 8mV 9mV mv FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY 4 MAY 5, 27

5 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 6V4925B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes Maximum Supply Voltage VDDxxx Supply Voltage 4.6 V Maximum Input Voltage V IH Referenced to GND VDD +.5 V Minimum Input Voltage V IL Referenced to GND GND -.5 V Storage Temperature Ts C Junction Temperature Tj - 25 C Input ESD protection ESD prot Human Body Model 2 V NTES on Absolute Max Parameters peration under these conditions is neither implied, nor guaranteed. Electrical Characteristics - Input/Supply/Common utput DC Parameters T AMB = -4 to +85 C; V DD = 3.3 V +/-5%, All outputs driving test loads (unless noted otherwise). PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes Ambient perating Temp T AMB C Supply Voltage VDDxxx Supply Voltage V Power supply Ramp Time T PWRRMP Power supply ramp must be monotonic 4 ms Latched Input High Voltage V IH_LI Single-ended Latched Inputs 2. V DD +.3 V Latched Input Low Voltage V IL_LI Single-ended Latched Inputs V SS V Input Leakage Current I IN V IN = V DD, V IN = GND -5 5 ua 2 perating Supply Current I DDP3.3 All outputs loaded and running 9 55 ma Input Frequency F i MHz 3 Pin Inductance L pin 5 7 nh C IN Logic Inputs pf Input Capacitance C UT utput pin capacitance 5 6 pf C INX X & X2 pins 5 6 pf From VDD Power-Up or de-assertion of PD Clk Stabilization T STAB to st clock ms Tfall_SE T FALL Fall/rise time of all 3.3V control inputs from ns Trise_SE T RISE 2-8% ns SMBus Voltage V DD V Low-level utput Voltage V I PULLUP.4 V Current sinking at V LSMB =.4 V I PULLUP SMB Data Pin 4 ma SCLK/SDATA (Max VIL -.5) to T Clock/Data Rise Time RI2C (Min VIH +.5) ns SCLK/SDATA (Min VIH +.5) to T FI2C Clock/Data Fall Time (Max VIL -.5) 3 ns SMBus perating Frequency F SMBUS 4 khz NTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not % tested in production). Signal is required to be monotonic in this region. 2 Input leakage current does not include inputs with pull-up or pull-down resistors. 3 For margining purposes only. Normal operation should have Fin =25MHz. MAY 5, 27 5 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

6 AC Electrical Characteristics - Low Power HCSL-Compatible PCIe utputs PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Clock Frequency f Spread off. MHz 2,3 25. MHz 2,3 Synthesis error ppm SSof f PCIe MHz or 25MHz ppm,2 ppm SSon -.5% spread, MHz only +/- ppm,2 Rising/Falling Edge Slew Rate t SLEW Differential Measurement V/ns,3,6 Slew Rate Variation t SLVAR Single-ended Measurement 2 %,6 Maximum utput Voltage V HIGH Includes overshoot mv 6,7 Minimum utput Voltage V LW Includes undershoot mv 6,7 Differential Voltage Swing V SWING Differential Measurement 3 mv,6 Crossing Point Voltage V XABS Single-ended Measurement mv,4,6 Crossing Point Variation V XABSVAR Single-ended Measurement 5 4 mv,4,5 Duty Cycle D CYC Differential Measurement % PCIe Jitter - Cycle to Cycle PCIe JC2C Differential Measurement ps PCIe[5:] Skew T SKEwPCIe5 Differential Measurement 72 5 ps,6,8 Spread Spectrum Modulation Frequency f SSMD Triangular Modulation khz Notes for PCIe Clocks: Guaranteed by design and characterization, not % tested in production. 2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz. 3 Slew rate measured through V_swing voltage range centered about differential zero. 4 Vcross is defined at the voltage where Clock = Clock#. 5 nly applies to the differential rising edge (Clock rising, Clock# falling.) 6 At default SMBus settings. 7 The Freescale P-series CPU's have internal terminations on their SerDes Reference Clock inputs. The resulting amplitude at these inputs will be /2 of the values listed, which are well within the 8mV Freescale specification for these inputs. 8 This value includes an intentional output-to-output skew of approximately 25ps. Electrical Characteristics - Phase Jitter, PCIe utputs at MHz PARAMETER SYMBL CNDITINS MIN TYP MAX INDUSTRY SPEC LIMIT UNITS NTES t jphpcie PCIe Gen phase jitter ps,2,3 t jphpcie2lo PCIe Gen 2 phase jitter ps Lo-band content (RMS),2,3 Jitter, Phase PCIe Gen 2 phase jitter ps t jphpcie2hi Hi-band content (RMS),2,3 t jphpcie3 PCIe Gen 3 phase jitter.5.83 ps (RMS),2,3 Notes on Phase Jitter: See for complete specs. Guaranteed by design and characterization, not tested in production. 2 Sample size of at least K cycles. This figures extrapolates to 8ps M cycles for a BER of Applies to PCIe default amplitude and MHz with spread off or at -.5%. FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY 6 MAY 5, 27

7 Electrical Characteristics - DDR Clock PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES DDR Clock Frequency Synthesis error f DDR66.66 ppm SSof f SEL#_66 =, V T = VDD/2 V Spread off MHz ppm 2,3,6,2,5 f DDR ppm SSon SEL#_66 =, V T = VDD/2 V Spread on. +/-5 MHz ppm 2,3,6,2,5 utput High Voltage V H V H at the selected operating frequency 2.4 V utput Low Voltage V L V L at the selected operating frequency.4 V t SLEW '' = Hi-Z Hi-Z V/ns Slew Rate t SLEW '' Slow Slew Rate (Averaging on) V/ns,3,8 VDD = 3.3V t SLEW '' Fast Slew Rate (Averaging on) V/ns,3,8 t SLEW '' Fastest Slew Rate (Averaging on) V/ns,3,8 Duty Cycle d t V T = VDD/2 V %,6 Jitter, Peak period jitter t jpeak V T = VDD/2 V ±96 ±5 ps,6 Phase Noise t phasenoise -56dBc 5 khz,7 AC Input Swing 3.3V V DD V AC This is the difference between VL and VH at the selected operating frequency V Spread Spectrum Modulation Frequency Electrical Characteristics - Sys_CCB f SSMD Triangular Modulation khz Clock Frequency f Sys_CCB PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES FS(:) =, VT = VDD/2 V. MHz 2,3,6 FS(:) =, VT = VDD/2 V 8. MHz 2,3,6 FS(:) =, VT = VDD/2 V MHz 2,3,6 FS(:) =, VT = VDD/2 V MHz 2,3,6 Synthesis error ppm SSof f Spread off ppm,2,5 ppm SSon Spread on +/-5 ppm,2,5 utput High Voltage V H V H at the selected operating frequency 2.4 V utput Low Voltage V L V L at the selected operating frequency.4 V t SLEW '' = Hi-Z Hi-Z V/ns Slew Rate t SLEW '' Slow Slew Rate (Averaging on) V/ns,3,8 VDD = 3.3V t SLEW '' Fast Slew Rate (Averaging on) V/ns,3,8 t SLEW '' Fastest Slew Rate (Averaging on) V/ns,3,8 Duty Cycle d t V T = VDD/2 V %,6 Jitter, Peak period jitter t jpeak V T = VDD/2 V, SSC <.75% ±6 ±5 ps Phase Noise t phasenoise -56dBc 5 khz,7 AC Input Swing 3.3V V DD V AC This is the difference between VL and VH at the selected operating frequency..9 V Spread Spectrum Modulation Frequency f SSMD Triangular Modulation khz Electrical Characteristics - 25M PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Clock frequency f 25M V T = VDD/2 V 25. ns 2,3,6 Synthesis error ppm ppm,2,5 utput High Voltage V H V H at the selected operating frequency 2.2 V utput Low Voltage V L V L at the selected operating frequency.5 V Rise/Fall time VDD = 3.3V t RF25M3.3V Measured between.6v and 2.7V.7 ns,3 Duty Cycle d t V T = VDD/2 V % Jitter, Peak period jitter t jpeak V T = VDD/2 V ±5 ps MAY 5, 27 7 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

8 Electrical Characteristics - REF(5:) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Clock Frequency f V T = VDD/2 V 25. MHz 2,3 Crystal Frequency Error ppm Including all aging and tuning effects -5 5 ppm,2 utput High Voltage V H V H at the selected operating frequency 2.2 V utput Low Voltage V L V L at the selected operating frequency.4 V Slew Rate t SLEW '' = Hi-Z V/ns,3,4 VDD Duty Cycle 3 3V d t V T = VDD/2 V % V Pin to Pin Skew t T =.5 V, odd/even outputs have an skew intentional 8degree phase shift. N/A ps Jitter, Peak period jitter t jpeak V T = VDD/2 V ±78 ±2 ps Jitter, Phase t jphase (2kHz-5MHz), V T =.5 V.7 3 ps rms Electrical Characteristics - USB_CLK(2:) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Clock Frequency f USB_CLK V T = VDD/2 V 2. MHz 2,3 24. MHz 2,3 Synthesis error ppm ppm,2,5 utput High Voltage V H V H at the selected operating frequency 2.2 V utput Low Voltage V L V L at the selected operating frequency.4 V t SLEW '' = Hi-Z Hi-Z V/ns Slew Rate t SLEW '' Slow Slew Rate (Averaging on)..4.8 V/ns,3,4 VDD = 3.3V t SLEW '' Fast Slew Rate (Averaging on) V/ns,3,4 t SLEW '' Fastest Slew Rate (Averaging on) V/ns,3,4 Duty Cycle d t V T = VDD/2 V % Jitter, RMS t jrms 2kHz to Nyquist 23 2 ps Jitter, Cycle to cycle t jcyc-cyc V T = VDD/2 V ps Electrical Characteristics M(:) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Clock Frequency f USB_CLK V T = VDD/2 V 2.48 MHz 2,3,6 Synthesis error ppm ppm,2,5 utput High Voltage V H V H at the selected operating frequency 2.2 V utput Low Voltage V L V L at the selected operating frequency.4 V t SLEW '' = Hi-Z Hi-Z V/ns Slew Rate t SLEW '' Slow Slew Rate (Averaging on) V/ns,3,4 VDD = 3.3V t SLEW '' Fast Slew Rate (Averaging on) V/ns,3,4 t SLEW '' Fastest Slew Rate (Averaging on) V/ns,3,4 Duty Cycle d t V T = VDD/2 V % Pin to Pin Skew t skew V T = VDD/2 V 8 25 ps Jitter, RMS t jrms 2kHz to Nyquist 47 7 ps Jitter, Peak period jitter t jpeak V T = VDD/2 V ±7 ±25 ps Notes for single-ended clocks: Guaranteed by design and characterization, not % tested in production. 2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz. 3 At default SMBus settings. 4 Measured between 2% and 8% of VDD. 5 This is the frequency error with respect to the crystal frequency. 6 Measured at the rising and/or falling edge at VDD/2 V. 7 Phase noise is calculated as the FFT of the TIE jitter. 8 Slew rate is measured from ±.3ΔV AC at the center of peak to peak voltage at the clock input. FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY 8 MAY 5, 27

9 General SMBus Serial Interface Information How to Write Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X- IDT clock will acknowledge each byte one at a time Controller (host) sends a stop bit Index Block Write peration Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N Byte N + X - P stop bit X Byte IDT (Slave/Receiver) Note: I 2 C compatible. Native mode is SMBus Block mode protocol. To use I 2 C Byte mode set the 2^7 bit in the command Byte. No Byte count is used. How to Read Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X- IDT clock sends Byte through Byte X (if X (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD N P Not acknowledge stop bit X Byte Data Byte Count=X Beginning Byte N Byte N + X - MAY 5, 27 9 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

10 Byte Frequency and Spread Select Register Bit Name Description Type Default 7 SS4 RW Sys_CCB and DDRCLK Spread See Table 2: Sys_CCB and DDRCLK 6 SS3 RW Selection Table Spread Table 5 SS2 RW 4 SS RW PCIE Spread Selection Table See Table : PCIE Spread Table 3 SS RW 2 REF_5_EN utput enable for REF_5 RW utput Disabled utput Enabled REF_4_EN utput enable for REF_4 RW utput Disabled utput Enabled REF_3_EN utput enable for REF_5 RW utput Disabled utput Enabled Byte utput Enable Register Bit Name Description Type Default 7 REF_2_EN utput enable for REF_2 RW utput Disabled utput Enabled 6 REF EN utput enable for REF_ RW utput Disabled utput Enabled 5 REF EN utput enable for REF_ RW utput Disabled utput Enabled 4 USB_CLK_EN utput enable for USB_CLK RW utput Disabled utput Enabled 3 USB_CLK2_EN utput enable for USB_CLK2 RW utput Disabled utput Enabled 2 CK2.48 EN utput enable for CK2.48_ RW utput Disabled utput Enabled CK2.48 EN utput enable for CK2.48_ RW utput Disabled utput Enabled DDRCLK_EN utput enable for DDRCLK RW utput Disabled utput Enabled Byte 2 utput Enable Register Bit Name Description Type Default 7 Sys_CCB_EN utput enable for Sys_CCB RW utput Disabled utput Enabled 6 PCIe5_EN utput enable for PCIe5 RW utput Disabled utput Enabled 5 PCIe4_EN utput enable for PCIe4 RW utput Disabled utput Enabled 4 PCIe3_EN utput enable for PCIe3 RW utput Disabled utput Enabled 3 PCIe2_EN utput enable for PCIe2 RW utput Disabled utput Enabled 2 PCIe_EN utput enable for PCIe RW utput Disabled utput Enabled PCIe_EN utput enable for PCIe RW utput Disabled utput Enabled 25M_EN utput enable for 25M RW utput Disabled utput Enabled Byte 3 Slew Rate Control Register Bit Name Description Type Default 7 USB_SLEW RW USB_CLK Slew Rate Control See USB Electrical Tables 6 USB_SLEW RW 5 USB2_SLEW RW USB_CLK2 Slew Rate Control See USB Electrical Tables 4 USB2_SLEW RW 3 CK2.48_SLEW CK2.48_ and CK2.48_ Slew Rate RW See CK2.48 Electrical Tables 2 CK2.48_SLEW Control RW Sys_CCB_SLEW RW Sys_CCB Slew Rate Control See Sys_CCB Electrical Tables Sys_CCB_SLEW RW Byte 4 Slew Rate Control Register Bit Name Description Type Default 7 DDR_Slew RW DDRCLK Slew Rate Control See DDR Electrical Tables 6 DDR_Slew RW 5 Reserved 4 Reserved 3 FS RW See Table 3: Sys_CCB Frequency Latch Sys_CCB Frequency Select Latch 2 FS RW Selection Latch USB_fSel USB_CLK Clock Frequency Select RW 2MHz 24MHz USB2_fSel USB_CLK2 Clock Frequency Select RW 2MHz 24MHz Byte 5 is Reserved FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY MAY 5, 27

11 Byte 6 PCI Express Amplitude Control Register Bit Name Description Type Default 7 PCIE_AMP RW See Table 4: PCIe Amplitude Selection PCI Express Amplitude Control 6 PCIE_AMP RW Table 5 SEL#_66 DDRCLK latch select R MHz 66MHz latch 4 SELPCIE25#_ PCI Express latch select R 25MHz MHz latch 3 Reserved Reserved RW Reserved Reserved RW - - Reserved Reserved RW - - Reserved Reserved RW - - Byte 7 Revision and Vendor ID Register Bit Name Description Type Default 7 REV ID R REV ID R - - Revision ID 5 REV ID R REV ID R Vendor ID R Vendor ID R - - Vendor ID Vendor ID R - - Vendor ID R - - Byte 8 Byte Count Register Bit Name Description Type Default 7 BC7 RW 6 BC6 RW 5 BC5 RW 4 BC4 RW Writing to this register will configure how Byte Count Programming b(7:) 3 BC3 RW many bytes will be read back. 2 BC2 RW BC RW BC RW Recommended Crystal Characteristics PARAMETER VALUE UNITS NTES Frequency 25 MHz Resonance Mode Fundamental - Frequency 25 C ±2 PPM Max Frequency Stability, 25 C ver perating Temperature Range ±2 PPM Max Temperature Range (commercial) ~7 C Temperature Range (industrial) -4~85 C Equivalent Series Resistance (ESR) 5 Ω Max Shunt Capacitance (C ) 7 pf Max Load Capacitance (C L ) 8 pf Max Drive Level. mw Max Aging per year ±5 PPM Max MAY 5, 27 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

12 Test Loads Low-Power push-pull HCSL utput test load (integrated terminations) Device L inches Differential Zo Rs=39 Zo Test Load CL=4.7pF except DDRCLK outputs where CL=5pf 2pF 2pF Single-ended utput Differential Test Load, Zo = ohm, L = 5 inches Thermal Characteristics (48-TSSP) PARAMETER SYMBL CNDITINS PKG TYP UNITS NTES VALUE θ JC Junction to Case 28 C/W θ Jb Junction to Base 42 C/W Thermal Resistance θ JA Junction to Air, still air PAG48 62 C/W θ JA Junction to Air, m/s air flow 54 C/W θ JA3 Junction to Air, 3 m/s air flow 5 C/W Thermal Characteristics (48-VFQFPN) PARAMETER SYMBL CNDITINS PKG TYP UNITS NTES VALUE θ JC Junction to Case 25 C/W θ Jb Junction to Base 3. C/W Thermal Resistance θ JA Junction to Air, still air NLG48 32 C/W θ JA Junction to Air, m/s air flow 25 C/W θ JA3 Junction to Air, 3 m/s air flow 22 C/W epad soldered to board Marking Diagrams 48 IDT 6V4925BPAGI YYWW$ 25 IDT6V4 925BN LGI YYWW$ 24 48TSSP 48VFQFPN Notes:. $ is the mark code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. G after the two-letter package code denotes Pb free package. 4. I denotes industrial temperature range. 5. Bottom marking for TSSP: country of origin if not USA. FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY 2 MAY 5, 27

13 Package utline and Dimensions (7 x 7mm 48-VFQFPN) 6V4925B DATASHEET MAY 5, 27 3 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

14 Package utline and Dimensions (7 x 7mm 48-VFQFPN), cont. FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY 4 MAY 5, 27

15 Package utline and Dimensions (6. mm Body 48-TSSP) 6V4925B DATASHEET MAY 5, 27 5 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

16 Package utline and Dimensions (6. mm Body 48-TSSP), cont. FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY 6 MAY 5, 27

17 rdering Information Part / rder Number Marking Shipping Packaging Package Temperature 6V4925BPAGI see page 2 Tubes 48-pin TSSP -4 to +85 C 6V4925BPAGI8 Tape and Reel 48-pin TSSP -4 to +85 C 6V4925BNLGI see page 2 Tray 48-pin VFQFPN -4 to +85 C 6V4925BNLGI8 Tape and Reel 48-pin VFQFPN -4 to +85 C G after the two-letter package code denotes Pb-Free configuration, RoHS compliant. Revision History Rev. Issue Date Issuer Description Page # M 2/9/23 R. Wade. Extensive overhaul of Electrical tables to more closely align with Freescale published specifications. 2. Updated electrical tables with characterization data. 3. Clarified SMBus registers for Slew Rate Controls 4. Moved electrical tables in front of SMBus for consistency with other data sheets. Various 5. Updated Thermal Data and added test loads for clarity. 6. Updated front page text 7. Minor updates to pin names (mainly power and ground) for consistency and clarity 8. Move to Final N 6/2/24 R. Wade. Corrected pin description for pin P 8//25 R. Wade. Updated SMBus operating frequency from KHz minimum to 4KHz maximum. 5 Q 5//26 RDW. Correct PCIeT_LRn and PCIeC_LRn to be PCIeT_Ln and PCIeC_Ln to indicate that the Rs for the PCIe outputs is outside the part and to correct the pin description accordingly. The test -3 loads for the device are correct. 2. Update block diagram PCIe pin names to be consistent. R /22/26 RDW. Undo Revision Q 2. PCIe outputs have integrated terminations for ohm differential Zo. 3. Update Test Loads 4. Update Features/Benefits -3, 2 S 5/5/27 RDW. Updated bit values in the Sys_CCB Frequency Select table. 2. Updated 48-TSSP and 48-VFQFPN package outline drawings. 3. Updated legal disclaimer. 3, 3-6 MAY 5, 27 7 FREESCALE PXX AND P2XX SYSTEM CLCK WITH SELECTABLE DDR FREQUENCY

18 Corporate Headquarters 624 Silver Creek Valley Road San Jose, CA 9538 USA Sales Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as IDT ) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. ther trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit Integrated Device Technology, Inc.. All rights reserved. 6V4925B MAY 5, Integrated Device Technology, Inc.

19 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology): 6V4925BPAGI 6V4925BPAGI8 6V4925BNLGI 6V4925BNLGI8