Frequency Generator & Integrated Buffers for Celeron & PII/III TM *SEL24_48#/REF0 VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI

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1 Integrated Circuit Systems, Inc. ICS Frequency Generator & Integrated Buffers for Celeron & PII/III TM Recommended Application: 80/80E and Solano type chipset. Output Features: V V, including free running V - 2.5V, 3.3V 3.3V fixed. - selectable by I 2 C MHz. Features: Up to 200MHz frequency support Support FS0-FS4 strapping status bit for I 2 C read back. Support power management: Through Power down Mode from I 2 C programming. Spread spectrum for EMI control ( ± 0.25% center). Uses external 4.38MHz crystal Skew Specifications: CPU CPU: <75ps SDRAM - SDRAM: < 250ps 3V66 3V66: <75ps PCI PCI: < For group skew specifications, please refer to group timing relationship. *SEL24_48#/REF0 VDDREF X X2 GNDREF GND3V66 3V66-0 3V66-3V66-2 VDD3V66 VDDPCI *FS0/PCICLK0 **FS/PCICLK GNDPCI PCICLK2 PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 GNDPCI PD# SCLK SDATA Pin Configuration ICS VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK GNDLCPU GNDSDR SDRAM0 SDRAM SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND48 24_48MHz/FS2** 48MHz/FS3* 48MHz/FS4* VDD48 48-Pin 300mil SSOP * These inputs have a 20K pull up to VDD. ** These inputs have a 20K pull down to GND. These are double strength. Block Diagram Functionality X X2 SEL24_48# SDATA SCLK FS[4:0] PD# PLL2 XTAL OSC PLL Spread Spectrum Control Logic Config. Reg. / 2 CPU DIVDER SDRAM DIVDER IOAPIC DIVDER PCI DIVDER 3V66 DIVDER MHz [:0] 24_48MHz REF0 CPUCLK [:0] SDRAM [7:0] SDRAM_F IOAPIC PCICLK [6:0] 3V66 [2:0] FS4 FS3 FS2 FS FS0 CPU SDRAM 3V66 PCICLK IOAPIC (MHz) (MHz) (MHz) (MHz) (MHz) Additional frequencies selectable through I 2 C programming.

2 ICS General Description The ICS is the single chip clock solution for designs using the 80/80E and Solano style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 2 C programming. Spread spectrum typically reduces system EMI by 8dB to 0dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I 2 C interface allows changing functions, stop clock programming and frequency selection. Pin Configuration PIN NUMBER PIN NAME TYPE DESCRIPTION Logic inputs frequency select I/O/USB output, SEL24_48MHz# IN When a "0" is latched, output frequency = 48MHz When a "" is latched, output frequency = 24MHz REF0 OUT 4.38 MHz reference clock. 2, 0,, 8, 25, 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference VDD PWR 30, 38 output buffers and 48MHz output 3 X IN Crystal input,nominally 4.38MHz. 4 X2 OUT Crystal output, nominally 4.38MHz. 5, 6, 4, 2, 29, 34, 42 GND PWR Ground pin for 3V outputs. 9, 8, 7 3V66 [2:0] OUT 3.3V Clocks 2 3 FS0 FS IN IN Frequency select pin. Frequency select pin. PCICLK0 PCICLK OUT OUT PCI clock output PCI clock output 20, 9, 7, 6, 5 PCICLK [6:2] OUT PCI clock outputs. 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input, 5V tolerant input 24 SDATA IN Data input for I2C serial input, 5V tolerant input FS4 FS3 FS2 IN IN IN Frequency select pin. Frequency select pin. Frequency select pin. 48MHz 48MHz 24_48MHz OUT OUT OUT 48MHz output clocks 48MHz output clocks 24 or 48MHz output 3 SDRAM_F OUT Free running SDRAM - used for feed back to chipset, should remain on always. 32, 33, 35, 36, 37, 39, 40, 4, SDRAM [7:0] OUT SDRAM clock outputs 43 GNDLCPU PWR Ground pin for the CPU clocks. 44, 45 CPUCLK [:0] OUT CPU clock outputs. 46 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V 47 IOAPIC OUT 2.5V clock output 48 VDDLAPIC PWR Power pin for the IOAPIC. 2.5V 2

3 ICS Serial Configuration Command map Byte0: Functionality and Frequency Select Register (default = 0) 2, 7:4 3 0 Description bit2 bit7 bit6 bit5 bit4 CPUCL- SDRAM 3V66 PCICLK IOAPIC K FS4 FS3 FS2 FS FS0 (MHz) (MHz) (MHz) (MH) (MHz) Spread Precentage to -0.5% Down Spread to -0.5% Down Spread to -0.5% Down Spread to -0.5% Down Spread Frequency is selected by hardware select, Latched Inputs - Frequency is selected by 2, 6:4 0 - Normal - Spread Spectrum Enabled 0 - Running - Tristate all outputs Note : Default at power-up will be for latched logic inputs to define frequency, as displayed by 3. (0,000) I 2 C is a trademark of Philips Corporation 3

4 ICS Byte : SDRAM Control Register (= enable, 0 = disable) B IT PIN# DESCRIPTION 7 - X FS2# 6 - X FS# 5 3 SDRAM_ F 4 32 SDRAM SDRAM SDRAM5 36 SDRAM SDRAM3 Byte 2: PCI, Control Register (= enable, 0 = disable) B IT PIN# DESCRIPTION 7 - X FS0# 6 20 PCICLK6 5 9 PCICLK5 4 7 PCICLK4 3 6 PCICLK3 2 5 PCICLK2 3 PCICLK 0 2 PCICLK0 Byte 3: 3V66, Control Register (= enable, 0 = disable) B IT PIN# DESCRIPTION 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved MHz MHz _48MHz B IT PIN# DESCRIPTION 7 - X FS4# 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 7 3V V V66-2 Byte 4: Control Register (= enable, 0 = disable) Byte 5: Control Register (= enable, 0 = disable) B IT PIN# DESCRIPTION 7 - X (SEL24_48#)# 6 REF IOAPIC 4 44 CPUCLK 3 45 CPUCLK SDRAM2 40 SDRAM 0 4 SDRAM0 Notes:. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. Byte 6: Control Register (= enable, 0 = disable) B IT PIN# DESCRIPTION 7-0 Reserved (Note) 6-0 Reserved (Note) 5-0 Reserved (Note) 4-0 Reserved (Note) 3-0 Reserved (Note) 2 - Reserved (Note) - Reserved (Note) 0-0 Reserved (Note) Note: Don t write into this register, writing into this register can cause malfunction. This Byte becomes the Byte Count for Readback, so it cannot be seen as data. 4

5 ICS Absolute Maximum Ratings Core Supply Voltage V I/O Supply Voltage V Logic Inputs GND 0.5 V to V DD +0.5 V Ambient Operating Temperature C to +70 C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table CPU to Group CPU to SDRAM to SDRAM 3V66 3V66 CPU 66MHz SDRAM 00MHz Offset Tolerance CPU 00MHz SDRAM 00MHz Offset Tolerance CPU 33MHz SDRAM 00MHz Offset Tolerance CPU 33MHz SDRAM 33MHz Offset Tolerance 2.5ns 5.0ns 3.75ns 7.5ns 5.0ns 3.75ns 3V66 to PCI.5-3.5ns.5-3.5ns.5-3.5ns.5-3.5ns PCI to PCI USB & DOT.0ns.0ns.0ns.0ns Asynch N/ A Asynch N/ A Asynch N/ A Asynch N/ A Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0-70 C; Supply Voltage V DD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) Input High Voltage V IH 2 V DD V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD -5 5 ma Input Low Current I IL V IN = 0 V; Inputs with no pull-up resistors -5 ma Input Low Current I IL2 V IN = 0 V; Inputs with pull-up resistors -200 ma Operating I DD3.3OP C L = 0 pf; 66M 00 ma Supply Current Power Down I DD3.3PD C L = 0 pf; With input address to Vdd or GND 600 ma Supply Current Input frequency F i V DD = 3.3 V; 4.38 MHz Pin Inductance L pin 7 nh Input Capacitance C IN Logic Inputs 5 pf C out Out put pin capacitance 6 pf C INX X & X2 pins pf Transition Time T trans To st crossing of target Freq. 3 ms Settling Time T s From st crossing to % target Freq. 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target Freq. 3 ms Delay t PZH,t PZH output enable delay (all outputs) 0 ns t PLZ,t PZH output disable delay (all outputs) 0 ns Guaranteed by design, not 00% tested in production. 5

6 ICS Electrical Characteristics - CPU T A = 0-70 C, V DDL = 2.5 V +/-5%; C L = 0-20 pf (unless otherwise stated) R DSP2B V O = V DD *(0.5) Ω R DSN2B V O = V DD *(0.5) Ω Output High Voltage V OH2B I OH = - ma 2 V Output Low Voltage V OL2B I OL = ma 0.4 V Output High Current I OH2B V =.0V, V OH@ MAX = 2.375V ma Output Low Current I OL2B V =.2V, V OL@ MAX = 0.3V ma Rise Time t r2b V OL = 0.4 V, V OH = 2.0 V ns Fall Time t f2b V OH = 0.4 V, V OL = 2.0 V ns Duty Cycle d t2b V T =.25 V % Skew t sk2b V T =.25 V 250 ps Jitter t jcyc-cyc V T =.25 V 250 ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - 3V66 T A = 0-70 C; V DD = 3.3 V +/-5%; C L = 0-30 pf (unless otherwise stated) R DSP V O = V DD *(0.5) 2 55 Ω R DSN V O = V DD *(0.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma 0.55 V Output High Current I OH VOH@ MIN =.0 V, VOH@ MAX = 3.35 V ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MAX= ma Rise Time t r V OL = 0.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL = 0.4 V ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 75 ps Jitter t jcyc-cyc V T =.5 V 500 ps Guaranteed by design, not 00% tested in production. 6

7 ICS Electrical Characteristics - IOAPIC T A = 0-70 C;V DDL = 2.5 V +/-5%; C L = 0-20 pf (unless otherwise stated) R DSP4B V O = V DD *(0.5) 9 30 Ω R DSN4B V O = V DD *(0.5) 9 30 Ω Output High Voltage V OH4\B I OH = -5.5 ma 2 V Output Low Voltage V OL4B I OL = 9.0 ma 0.4 V Output High Current I OH4B V OH@ min =.0 V, V OH@ MAX = V ma Output Low Current I OL4B V OL@ MIN =.2 V, V OL@ MAX= 0.3 V ma Rise Time t r4b V OL = 0.4 V, V OH = 2.0 V ns Fall Time t f4b V OH = 2.0 V, V OL = 0.4 V ns Duty Cycle d t4b V T =.25 V % Skew t sk4 250 ps Jitter t jcyc-cyc V T =.25 V 500 ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - SDRAM T A = 0-70 C; V DD = V DDL = 3.3 V +/-5%; C L = pf (unless otherwise stated) R DSP3 V O = V DD *(0.5) 0 24 Ω R DSN3 V O = V DD *(0.5) 0 24 Ω Output High Voltage V OH3 I OH = - ma 2.4 V Output Low Voltage V OL3 I OL = ma 0.4 V Output High Current I OH3 V = 2.0 V, V OH@ MAX =3.35 V ma Output Low Current I OL3 V OL@ MIN =.0 V, V OL@ MAX =0.4 V ma Rise Time T r3 V OL = 0.4 V, V OH = 2.4 V ns Fall Time T f3 V OH = 2.4 V, V OL = 0.4 V ns Duty Cycle D t3 V T =.5 V % Skew T sk3 V T =.5 V 250 ps Jitter t j cyc-cyc V T =.5 V 250 ps Guaranteed by design, not 00% tested in production. 7

8 ICS Electrical Characteristics - PCI T A = 0-70 C; V DD = 3.3 V +/-5%; C L = 0-30 pf (unless otherwise stated) R DSP V O = V DD *(0.5) 2 55 Ω R DSN V O = V DD *(0.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma 0.55 V Output High Current I OH VOH@ MIN =.0 V, VOH@ MAX = ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MAX= ma Rise Time t r V OL = 0.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL = 0.4 V ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 500 ps Jitter t jcyc-cyc V T =.5 V 500 ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - REF, 48MHz_0 T A = 0-70 C; V DD = V DDL = 3.3 V +/-5%; C L = 0-20 pf (unless otherwise stated) R DSP5 V O = V DD *(0.5) Ω R DSN5 V O = V DD *(0.5) Ω Output High Voltage V OH5 I OH = ma 2.4 V Output Low Voltage V OL5 I OL = - ma 0.4 V Output High Current I OH5 V = V, V OH@MAX = 3.35 V ma Output Low Current I OL5 V OL@MIN =.95 V, V OL@MIN =0.4 V ma Rise Time t r5 V OL = 0.4 V, V OH = 2.4 V 4 ns Fall Time t f5 V OH = 2.4 V, V OL = 0.4 V 4 ns Duty Cycle d t5 V T =.5 V % Skew T sk V T =.5 V 250 ps Jitter t jcyc-cyc t jcyc-cyc Guaranteed by design, not 00% tested in production. V T =.5 V; Fixed Clocks 500 ps V T =.5 V; Ref Clocks 000 ps 8

9 ICS General I 2 C serial interface information The information in this section assumes familiarity with I 2 C programming. For more information, contact ICS for an I 2 C programming application note. How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Notes:. The ICS clock generator is a slave/receiver, I 2 C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 00K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. Controller (Host) Start Address D2 (H) Dummy Command Code Dummy Byte Count Byte 0 Byte Byte 2 Byte 3 Byte 4 Byte 5 Stop How to Write: ICS (Slave/Receiver) Controller (Host) Start Address D3 (H) Stop How to Read: ICS (Slave/Receiver) Byte Count Byte 0 Byte Byte 2 Byte 3 Byte 4 Byte 5 9

10 ICS Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic 0) voltage potential. A 0 Kilohm (0K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Fig. 0

11 ICS PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 ms. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# CPUCLK 3V66 PCICLK VCO Crystal Notes:. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 33MHz. Similar operation when CPU is 00MHz.

12 ICS INDEX AREA N 2 D E E h x 45 c α 300 mil SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS L MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e BASIC BASIC h L N SEE VARIATIONS SEE VARIATIONS a A A -C- - VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, MO-8 e b SEATING PLANE (.004) C Ordering Information 9248yF-38 Example: XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) 2