HTT0T_LPRS/66M REF0/SEL_HTT66 REF1/SEL_SATA VDDREF VDDHTT REF MHz_ VDDCPU 48MHz_0 2

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1 DATASHEET Programmable System Clock Chip for ATI RS79 - K8 TM based Systems 9LPRS47C Recommended Application: ATI RS79 systems using AMD K8 processors Output Features: 2 - Greyhound compatible K8 CPU pair 6 - low-power differential SRC pairs 2 - low-power differential SouthBridge SRC pairs 4 - low-power differential ATIG pairs - Selectable low-power differential MHz nonspread SATA/ SRC output - Selectable MHz low-power differential/ 66 MHz single-ended HTT clock 2-48MHz USB clock MHz Reference clock Key Specifications: CPU outputs cycle-to-cycle jitter < 85ps SRC outputs cycle-to-cycle jitter < 25ps ATIG outputs cycle-to-cycle jitter < 25ps +/- 3ppm frequency accuracy on CPU, SRC & ATIG clocks Features/Benefits: CPU, ATIG, SB_SRC and SRC outputs are independently programmable for frequency Spread Spectrum for EMI reduction Outputs may be disabled via SMBus External crystal load capacitors for maximum frequency accuracy Meets PCIE Gen2 specifications Pin Configuration VDD48 2 GNDREF VDDREF REF/SEL_HTT66 REF/SEL_SATA REF2 VDDHTT HTTT_LPRS/66M HTTC_LPRS/66M GNDHTT RESTORE# PD# CPUKGT_LPRS CPUKGC_LPRS MHz_ 48 VDDCPU 48MHz_ 2 47 GNDCPU GND CPUKGT_LPRS SMBCLK 4 45 CPUKGC_LPRS SMBDAT 5 44 VDDA SRC5C_LPRS 6 43 GNDA SRC5T_LPRS 7 42 GNDSATA SRC4C_LPRS 8 SRC4T_LPRS 9 9LPRS47C 4 SRC6T/SATAT_LPRS 4 SRC6C/SATAC_LPRS GNDSRC 39 VDDSATA VDDSRC 38 ATIGT_LPRS SRC3C_LPRS 2 37 ATIGC_LPRS SRC3T_LPRS 3 36 ATIGT_LPRS SRC2C_LPRS 4 35 ATIGC_LPRS SRC2T_LPRS 5 34 VDDATIG VDDSRC GNDATIG GNDSRC SRCC_LPRS SRCT_LPRS SRCC_LPRS SRCT_LPRS SB_SRCC_LPRS SB_SRCT_LPRS GNDSB_SRC VDDSB_SRC SB_SRCC_LPRS SB_SRCT_LPRS GNDATIG ATIG3C_LPRS ATIG3T_LPRS ATIG2C_LPRS ATIG2T_LPRS 64-Pin MLF * Internal Pull-Up Resistor ** Internal Pull-Down Resistor

2 Pin Description PIN # PIN NAME TYPE DESCRIPTION 48MHz_ OUT 48MHz clock output. 2 48MHz_ OUT 48MHz clock output. 3 GND48 GND Ground pin for the 48MHz outputs 4 SMBCLK IN Clock pin of SMBus circuitry, 5V tolerant. 5 SMBDAT I/O Data pin for SMBus circuitry, 5V tolerant. 6 SRC5C_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 7 SRC5T_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 8 SRC4C_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 9 SRC4T_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed GNDSRC GND Ground pin for the SRC outputs VDDSRC PWR Supply for SRC core, 3.3V nominal 2 SRC3C_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 3 SRC3T_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 4 SRC2C_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 5 SRC2T_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 6 VDDSRC PWR Supply for SRC core, 3.3V nominal 7 GNDSRC GND Ground pin for the SRC outputs 8 SRCC_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 9 SRCT_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 2 SRCC_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 2 SRCT_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 22 SB_SRCC_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 23 SB_SRCT_LPRS OUT True clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 24 GNDSB_SRC GND Ground pin for the SB_SRC outputs 25 VDDSB_SRC PWR Supply for SRC core, 3.3V nominal 26 SB_SRCC_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 27 SB_SRCT_LPRS OUT True clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 28 GNDATIG GND Ground pin for the ATIG outputs 29 ATIG3C_LPRS OUT Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 3 ATIG3T_LPRS OUT True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 3 ATIG2C_LPRS OUT Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 32 ATIG2T_LPRS OUT True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 33 GNDATIG GND Ground pin for the ATIG outputs 34 VDDATIG PWR Power supply for ATIG core, nominal 3.3V 35 ATIGC_LPRS OUT Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 36 ATIGT_LPRS OUT True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 2

3 Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION 38 ATIGT_LPRS OUT True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 39 VDDSATA PWR Power supply for SATA core logic, nominal 3.3V 4 SRC6C/SATAC_LPRS OUT Complement clock of low power differential SRC/SATA clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 4 SRC6T/SATAT_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 42 GNDSATA GND Ground pin for the SRC outputs 43 GNDA GND Ground for the Analog Core 44 VDDA PWR 3.3V Power for the Analog Core 45 CPUKGC_LPRS OUT Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor.(no 33 ohm series resistor needed) 46 CPUKGT_LPRS OUT True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor. (no 33 ohm series resistor needed) 47 GNDCPU GND Ground pin for the CPU outputs 48 VDDCPU PWR Supply for CPU core, 3.3V nominal 49 CPUKGC_LPRS OUT Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor. (no 33 ohm series resistor needed) 5 CPUKGT_LPRS OUT True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor.(no 33 ohm series resistor needed) 5 PD# IN Enter /Exit Power Down. = Power Down, = normal operation. 52 RESTORE# I/O Open Drain I/O. As an input it restores the PLL's to power up default state. As an output, this signal is driven low when the internal watchdog hardware timer expires. It is cleared when the internal watchdog hardware timer is reset or disabled. The input is falling edge triggered. = Restore Settings, = normal operation. 53 GNDHTT PWR Ground pin for the HTT outputs 54 HTTC_LPRS/66M OUT Complementary signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended 66MHz hyper transport clock 55 HTTT_LPRS/66M OUT True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended 66MHz hyper transport clock 56 VDDHTT PWR Supply for HTT clocks, nominal 3.3V. 57 REF2 OUT 4.38 MHz reference clock, 3.3V 58 REF/SEL_SATA I/O 4.38 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA output = MHz differential spreading SRC clock, = MHz non-spreading differential SATA clock 59 REF/SEL_HTT66 I/O 4.38 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock Frequency. = MHz differential HTT clock, = 66MHz 3.3V single ended HTT clock 6 VDDREF PWR Ref, TAL power supply, nominal 3.3V 6 GNDREF GND Ground pin for the REF outputs. 62 IN Crystal input, nominally 4.38MHz 63 2 OUT Crystal output, nominally 4.38MHz 64 VDD48 PWR Power pin for the 48MHz outputs and core. 3.3V 3

4 General Description The 9LPRS47C is a main clock synthesizer chip that provides all clocks required for ATI RS7xx-based systems.using AMD processors. An SMBus interface allows full control of the device. Block Diagram 2 OSC 4.38MHz REF 48MHz_(:) Fixed PLL4 EACT 48MHz SEL_SATA MHz SRC6/SATA SS PLL SB_SRC (-.5% DWN SP) 8MHz MHz SB_SRC(:) SS PLL SB_SRC/SRC SRC ZDB PLL 4 to 9 MHz 6MHz/6 SEL_HTT66 SRC(5:) HTT MHz HTT_T/66 SS PLL HTT 66MHz 2MHz HTT_C/66 CPUKG(:) ATIG ZDB PLL ATIG(3:) PD# SEL_HTT66 SEL_SATA SMBCLK SMBDAT RESTORE# CLKREQ(A:B)# MODE Control Logic 9LPR47C Power Group Table Pin Number VDD GND Description M I/O & Core, 6, 7 SRC & SRCI/O I/O & Core; SRC PLL Analog SB_SRCI/O I/O & Core; SB_SRC PLL Analog / Digital 34 28, 33 ATIG I/O & Core; ATIG PLL Analog SATA I/O & Core; FI PLL Analog / Digital ATIG PLL & SRC PLL Digital CPU I/O & Core; CPU PLL Analog / Digital HTT I/O & Core 6 6 Crystal, REF I/O & Core 4

5 Table: CPU and HTT Frequency Selection Table Byte 3 Bit4 Bit3 Bit2 Bit Bit CPU (MHz) CPU FS4 CPU FS3 CPU FS2 CPU FS CPU FS HTT Single-ended HTT Differential SEL_HTT66 = SEL_HTT66 = Spread % (B6b6= and B3b5=) % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % Depends on SB_SRC PLL. See Table 4. CPU OverClock % 5

6 Table 2: SRC Frequency Selection Table Byte 4 Bit3 Bit2 Bit Bit SRC Spread SRC SB FS3 SB FS2 SB FS SB FS (MHz) % (B6b5=) OverClock %. %. % 2. 2% 3. 3% 4. 4% 5. 5% 6. 6% 7. 7% 8. 8% 9. 9%. %. % 2. 2% 3. 3% 4. 4%. OFF % -.5% Table3: ATIG Frequency Selection Table Byte 5 Spread Bit3 Bit2 Bit Bit ATIG(3:) ATIG % ATIG ATIG ATIG ATIG (MHz) OverClock % (B6b7=) FS3 FS2 FS FS. %. % 2. 2% 3. 3% 4. 4% 5. 5% 6. 6% 7. 7% 8. 8% 9. 9%. %. % 2. 2% 3. 3% 4. 4%. OFF % -.5% 6

7 Table4: SB_SRC Frequency Selection Table Byte 6 SB_SRC Spread Bit4 Bit3 Bit2 Bit Bit SB_SRC (:) % SRC SRC SRC SRC SRC OverClock % (MHz) (B6b6=) FS4 FS3 FS2 FS FS % % % % 89. -% 9. -% 9. -9% % % % % % % % 99. -%. OFF %. %. % 2. 2% 3. 3% 4. 4% 5. 5% 6. 6% 7. 7% 8. 8% 9. 9%. %. % 2. 2% 3. 3% 4. 4% 5. 5% NOTE: All frequencies assume that the SB_SRC are at % Overclocking. Table 5: IO_Vout select table B2b2 B2b B2b IO_Vout.3V.4V.5V.6V.7V.8V.9V.V Bold Entry is Power up Default -.5% -.5% 7

8 General SMBus serial interface information for the 9LPRS47C How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) T start bit Slave Address *D (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N ICS (Slave/Receiver) ACK ACK ACK ACK How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Controller (Host) T start bit Slave Address *D (H) WR WRite Beginning Byte = N RT Repeat start Slave Address *D (H) RD ReaD ICS (Slave/Receiver) ACK ACK ACK P Byte N + - stop bit Byte ACK ACK ACK Byte Data Byte Count = Beginning Byte N N P Not acknowledge stop bit Byte N + - 8

9 SMBus Table: Latched Input Readback Output Enable Control Register Byte Name Description Type Default Bit 7 SEL_HTT66 readback Hypertransport Select R MHz Differential HTT clock 66 MHz 3.3V Single-ended HTT clock Latch Bit 6 SEL_SATA readback SATA Select R SRC6/SATA pair is SRC SS SRC6/SATA pair is SATA nonspread output capable output Latch Bit 5 REF_OE Output Enable RW Hi-Z Enabled Bit 4 REF_OE Output Enable RW Hi-Z Enabled Bit 3 REF2_OE Output Enable RW Hi-Z Enabled Bit 2 48MHz OE Output Enable RW Low Enabled Bit 48MHz OE Output Enable RW Low Enabled Bit SMBus Table:Output Enable Control Register Byte Name Control Function Type Default Bit 7 Bit 6 SRC6/SATA_OE Enable Output Enable RW Low/Low Enabled Bit 5 SRC5_OE Output Enable RW Low/Low Enabled Bit 4 SRC4_OE Output Enable RW Low/Low Enabled Bit 3 SRC3_OE Output Enable RW Low/Low Enabled Bit 2 SRC2_OE Output Enable RW Low/Low Enabled Bit SRC_OE Output Enable RW Low/Low Enabled Bit SRC_OE Output Enable RW Low/Low Enabled SMBus Table: Output Enable and 48MHz Strength Control Register Byte 2 Name Control Function Type Default Bit 7 SB_SRC_OE Output Enable RW Low/Low Enabled Bit 6 SB_SRC_OE Output Enable RW Low/Low Enabled Bit 5 ATIG3_OE Output Enable RW Low/Low Enabled Bit 4 ATIG2_OE Output Enable RW Low/Low Enabled Bit 3 ATIG_OE Output Enable RW Low/Low Enabled Bit 2 ATIG_OE Output Enable RW Low/Low Enabled Bit 48MHz Strength 48MHz_ Drive Strength Sel. RW Load 2 Load Bit 48MHz Strength 48MHz_ Drive Strength Sel. RW Load 2 Load SMBus Table: CPU/HTT Frequency Control Register Byte 3 Name Control Function Type Default Bit 7 CPU_OE Output enable RW Low/Low Enable Bit 6 CPU_OE Output enable RW Low/Low Enable Bit 5 CPU Source CPU Spread Source RW Fix PLL SB_SRC PLL Bit 4 CPU_FS4 CPU Frequency Select MSB RW Bit 3 CPU_FS3 CPU Frequency Select RW See CPU Frequency Select Table Bit 2 CPU_FS2 CPU Frequency Select RW Default value corresponds to 2MHz. Bit CPU_FS CPU Frequency Select RW Note that Selected HTT frequency tracks the CPU frequency. Bit CPU_FS CPU Frequency Select LSB RW SMBus Table: SRC Frequency Control Register Byte 4 Name Control Function Type Default Bit 7 REF_Strength REF_Drive Strength Sel RW Load 2 Load Bit 6 REF_Strength REF_Drive Strength Sel RW Load 2 Load Bit 5 REF2_Strength REF2_Drive Strength Sel RW Load 2 Load Bit 4 Bit 3 SRC_FS3 SRC Frequency Select RW Bit 2 SRC_FS2 SRC Frequency Select RW See SRC Frequency Select Table Bit SRC_FS SRC Frequency Select RW Bit SRC_FS SRC Frequency Select LSB RW 9

10 SMBus Table: ATIG Frequency Select Register Byte 5 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Disable O vershoot R eduction Bit 4 DISABLE_ORT T echnology during CPU PLL M/N RW ENABLE ORT DISABLE ORT Programming Bit 3 ATIG_FS3 ATIG Frequency Select RW Bit 2 ATIG_FS2 ATIG Frequency Select RW See ATIG Frequency Select Table Bit ATIG_FS ATIG Frequency Select RW Bit ATIG_FS ATIG Frequency Select LSB RW SMBus Table: SB_SRC Frequency Select Register Byte 6 Name Control Function Type Default Bit 7 ATIG SSEN ATIG Spread Enable RW Disable Enable Bit 6 SB_SRC/CPU SSEN SB_SRC/CPU Spread Enable RW Disable Enable Bit 5 SRC SSEN SRC Spread Enable RW Disable Enable Bit 4 SB_SRC_FS4 SB_SRC Frequency Select MSB RW See SB_SRC Frequency Select Table Bit 3 SB_SRC_FS3 SB_SRC Frequency Select RW Note: SB_SRC and CPU Clocks are synchronous. Changing Bit 2 SB_SRC_FS2 SB_SRC Frequency Select RW this frequency will alter the SB_SRC and CPU frequency by the Bit SB_SRC_FS SB_SRC Frequency Select RW same percentage. Bit SB_SRC_FS SB_SRC Frequency Select LSB RW SMBus Table: Device ID register Byte 7 Name Control Function Type Default Bit 7 Device ID7 R x Bit 6 Device ID6 R x Bit 5 Device ID5 R x Bit 4 Device ID4 R 78 hex for 9LPRS478, x Device ID Bit 3 Device ID3 R 7 hex for 9LPRS47 x Bit 2 Device ID2 R x Bit Device ID R x Bit Device ID R x SMBus Table: Vendor & Revision ID Register Byte 8 Name Control Function Type Default Bit 7 RID3 R - - Bit 6 RID2 R - - REVISION ID Bit 5 RID R - - Bit 4 RID R - - Bit 3 VID3 R - - Bit 2 VID2 R - - VENDOR ID Bit VID R - - Bit VID R - - SMBus Table: WatchDog Timer Control Register Byte 9 Name Control Function Type Default Bit 7 HWD_EN Watchdog Hard Alarm Enable RW Disable and Reload Hartd Alarm Timer, Clear WD Hard Enable Timer status bit. Bit 6 SWD_EN Watchdog Soft Alarm Enable RW Disable Enable Bit 5 WD Hard Status WD Hard Alarm Status R Normal Alarm Bit 4 WD Soft Status WD Soft Alarm Status R Normal Alarm Bit 3 WDTCtrl Watch Dog Alarm Time base Control RW 29ms Base 6ms Base Bit 2 HWD2 WD Hard Alarm Timer Bit 2 RW These bits represent the number of Watch Dog Time Base Bit HWD WD Hard Alarm Timer Bit RW Units that pass before the Watch Alarm expires. Default is 7 Bit HWD WD Hard Alarm Timer Bit RW 29ms = 2s.

11 SMBus Table: WD Timer Safe Frequency Control Register Byte Name Control Function Type Default Bit 7 SWD2 WD Soft Alarm Timer Bit 2 RW These bits represent the number of Watch Dog Time Base Bit 6 SWD WD Soft Alarm Timer Bit RW Units that pass before the Watch Alarm expires. Default is 7 Bit 5 SWD WD Soft Alarm Timer Bit RW 29ms = 2s. Bit 4 WD SF4 RW These bits configure the safe frequency that the device returns Bit 3 WD SF3 RW Watch Dog Safe Freq to if the Watchdog Timer expires. The value show here Bit 2 WD SF2 RW Programming bits corresponds to the power up default of the device. See the Bit WD SF RW various Frequency Select Tables for the exact frequencies. Bit WD SF RW SMBus Table: Byte Count Register Byte Name Control Function Type Default Bit 7 Bit 6 Bit 5 BC5 Byte Count bit 5 (MSB) RW Bit 4 BC4 Byte Count bit 4 RW Bit 3 BC3 Byte Count bit 3 RW Determines the number of bytes that are read back from the Bit 2 BC2 Byte Count bit 2 RW device. Default is F hex. Bit BC Byte Count bit RW Bit BC Byte Count bit (LSB) RW SMBus Table: M/N Programming Enable and I/O Vout Control Register Byte 2 Name Control Function Type Default Bit 7 CPU M/N En CPU PLL M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 6 SRC M/N En SRC M/N Prog.Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 5 ATIG M/N En ATIG M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 4 SB_SRC M/N En SB_SRC M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 3 IO Output Voltage Select (Most Bit 2 IO_VOUT2 RW Significant Bit) See Table 5: V_IO Selection Bit IO_VOUT IO Output Voltage Select RW (Default is.8v) IO Output Voltage Select (Least Bit IO_VOUT RW Significant Bit) SMBus Table: CLKREQA# Configuration Register (9LPRS478 only) Byte 3 Name Control Function Type Default Bit 7 Bit 6 CLKREQA#_SRC6/SATA CLKREQA# controls SRC6/SATA RW Not Controlled Controlled Bit 5 CLKREQA#_SRC5 CLKREQA# controls SRC5 RW Not Controlled Controlled Bit 4 CLKREQA#_SRC4 CLKREQA# controls SRC4 RW Not Controlled Controlled Bit 3 CLKREQA#_SRC3 CLKREQA# controls SRC3 RW Not Controlled Controlled Bit 2 CLKREQA#_SRC2 CLKREQA# controls SRC2 RW Not Controlled Controlled Bit CLKREQA#_SRC CLKREQA# controls SRC RW Not Controlled Controlled Bit CLKREQA#_SRC CLKREQA# controls SRC RW Not Controlled Controlled SMBus Table: CLKREQB# Configuration Register (9LPRS478 only) Byte 4 Name Control Function Type Default Bit 7 Bit 6 CLKREQB#_SRC6/SATA CLKREQB# controls SRC6/SATA RW Not Controlled Controlled Bit 5 CLKREQB#_SRC5 CLKREQB# controls SRC5 RW Not Controlled Controlled Bit 4 CLKREQB#_SRC4 CLKREQB# controls SRC4 RW Not Controlled Controlled Bit 3 CLKREQB#_SRC3 CLKREQB# controls SRC3 RW Not Controlled Controlled Bit 2 CLKREQB#_SRC2 CLKREQB# controls SRC2 RW Not Controlled Controlled Bit CLKREQB#_SRC CLKREQB# controls SRC RW Not Controlled Controlled Bit CLKREQB#_SRC CLKREQB# controls SRC RW Not Controlled Controlled Note: If CLKREQA and CLKREQB are both selected to control an output, the control condition is an OR function. CLKREQA# = OR CLKREQB = results in the controlled output running.

12 SMBus Table:Test Mode Register Byte 5 Name Control Function Type Default Bit 7 Test_Sel Selects Test Mode RW Normal mode All ouputs are REF/N Bit 6 SB_SRC Source SB_SRC Source Selection RW SB_SRC PLL SRC PLL Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit SMBus Table: CPU PLL Frequency Control Register Byte 6 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW Bit 6 N Div N Divider Prog bit RW Bit 5 M Div5 RW The decimal representation of M and N Divider in Byte 6 and Bit 4 M Div4 RW 7 will configure the VCO frequency. Default at power up = Bit 3 M Div3 RW Byte 3 Rom table. See M/N Caculation Tables for VCO M Divider Programming bits Bit 2 M Div2 RW frequency formulas. Bit M Div RW Bit M Div RW SMBus Table: CPU PLL Frequency Control Register Byte 7 Name Control Function Type Default Bit 7 N Div RW Bit 6 N Div9 RW Bit 5 N Div8 RW The decimal representation of M and N Divider in Byte 6 and Bit 4 N Div7 RW 7 will configure the VCO frequency. Default at power up = N Divider Programming b(:3) Bit 3 N Div6 RW Byte 3 Rom table. See M/N Caculation Tables for VCO Bit 2 N Div5 RW frequency formulas. Bit N Div4 RW Bit N Div3 RW SMBus Table: SB_SRC PLL Spread Spectrum Control Register Byte 8 Name Control Function Type Default Bit 7 SSP7 RW Bit 6 SSP6 RW Bit 5 SSP5 RW Bit 4 SSP4 Spread Spectrum Programming RW These bits set the SB_SRC spread pecentage.please contact Bit 3 SSP3 b(7:) RW IDT for the appropriate values. Bit 2 SSP2 RW Bit SSP RW Bit SSP RW SMBus Table: SB_SRC PLL Spread Spectrum Control Register Byte 9 Name Control Function Type Default Bit 7 SSP5 RW Bit 6 SSP4 RW Bit 5 SSP3 RW Bit 4 SSP2 Spread Spectrum Programming RW These bits set the SB_SRC spread pecentage.please contact Bit 3 SSP b(5:8) RW IDT for the appropriate values. Bit 2 SSP RW Bit SSP9 RW Bit SSP8 RW 2

13 SMBUS Table: CPU Output Divider Register Byte 2 Name Control Function Type Default Bit 7 CPU NDiv LSB N Divider Programming RW Byte 28 has the N Divider LSB (bit ) for CPU M/N Bit 6 Bit 5 Bit 4 Bit 3 CPUDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 CPUDiv2 CPU Divider Ratio Programming RW :/3 ; :/6 :/2 ; :/24 Bit CPUDiv Bits RW :/5 ; :/ :/2 ; :/4 Bit CPUDiv RW :/9 ; :/8 :/36 ; :/72 SMBUS Table: SRC Frequency Control Register Byte 2 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW Bit 6 N Div N Divider Prog bit RW Bit 5 M Div5 RW The decimal representation of M and N Divider in Byte 2 and Bit 4 M Div4 RW 22 configure the SRC VCO frequency. See M/N Caculation Bit 3 M Div3 M Divider Programming RW Tables for VCO frequency formulas. Bit 2 M Div2 bit (5:) RW Bit M Div RW Bit M Div RW SMBUS Table: SRC Frequency Control Register Byte 22 Name Control Function Type Default Bit 7 N Div RW Bit 6 N Div9 RW Bit 5 N Div8 RW The decimal representation of M and N Divider in Byte 2 and Bit 4 N Div7 N Divider Programming Byte6 RW 22 configure the SRC VCO frequency. See M/N Caculation Bit 3 N Div6 bit(7:) and Byte5 bit(7:6) RW Tables for VCO frequency formulas. Bit 2 N Div5 RW Bit N Div4 RW Bit N Div3 RW SMBUS Table: SRC Spread Spectrum Control Register Byte 23 Name Control Function Type Default Bit 7 SSP7 RW Bit 6 SSP6 RW Bit 5 SSP5 RW Bit 4 SSP4 Spread Spectrum Programming RW These bits set the SRC spread pecentages.please contact IDT Bit 3 SSP3 bit(7:) RW for the appropriate values. Bit 2 SSP2 RW Bit SSP RW Bit SSP RW SMBUS Table: SRC Spread Spectrum Control Register Byte 24 Name Control Function Type Default Bit 7 SSP5 RW Bit 6 SSP4 RW Bit 5 SSP3 RW Bit 4 SSP2 Spread Spectrum Programming RW These bits set the SRC spread pecentages.please contact IDT Bit 3 SSP bit(5:8) RW for the appropriate values. Bit 2 SSP RW Bit SSP9 RW Bit SSP8 RW 3

14 SMBUS Table: SRC Output Divider Control Register Byte 25 Name Control Function Type Default Bit 7 SB_SRC NDiv LSB N Divider Programming RW N Divider LSB (bit ) for SRC M/N programming. Bit 6 Bit 5 Bit 4 Bit 3 SRCDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 SRCDiv2 SRC Divider Ratio Programming RW :/3 ; :/6 :/2 ; :/24 Bit SRCDiv Bits RW :/5 ; :/ :/2 ; :/4 Bit SRCDiv RW :/9 ; :/8 :/36 ; :/72 SMBUS Table: ATIG Frequency Control Register Byte 26 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW Bit 6 N Div N Divider Prog bit RW Bit 5 M Div5 RW The decimal representation of M and N Divider in Byte 26 and Bit 4 M Div4 RW 27 will configure the VCO frequency. Default at power up = Bit 3 M Div3 M Divider Programming RW Byte 5 Rom table. See M/N Caculation Tables for VCO Bit 2 M Div2 bit (5:) RW frequency formulas. Bit M Div RW Bit M Div RW SMBUS Table: ATIG Frequency Control Register Byte 27 Name Control Function Type Default Bit 7 N Div RW Bit 6 N Div9 RW Bit 5 N Div8 RW The decimal representation of M and N Divider in Byte 26 and Bit 4 N Div7 N Divider Programming Byte2 RW 27 will configure the VCO frequency. Default at power up = Bit 3 N Div6 bit(7:) and Byte9 bit(7:6) RW Byte 5 Rom table. See M/N Caculation Tables for VCO Bit 2 N Div5 RW frequency formulas. Bit N Div4 RW Bit N Div3 RW SMBUS Table: ATIG Output Divider Control Register Byte 28 Name Control Function Type Default Bit 7 ATIG NDiv LSB N Divider Programming RW N Divider LSB (bit ) for ATIG M/N programming. Bit 6 Bit 5 Bit 4 Bit 3 ATIGDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 ATIGDiv2 ATIG Divider Ratio Programming RW :/3 ; :/6 :/2 ; :/24 Bit ATIGDiv Bits RW :/5 ; :/ :/2 ; :/4 Bit ATIGDiv RW :/9 ; :/8 :/36 ; :/72 SMBUS Table: SB_SRC Frequency Control Register Byte 29 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW Bit 6 N Div N Divider Prog bit RW Bit 5 M Div5 RW The decimal representation of M and N Divider in Byte 29 and Bit 4 M Div4 RW 3 will configure the VCO frequency. Default at power up = Bit 3 M Div3 M Divider Programming RW Byte 6 Rom table. See M/N Caculation Tables for VCO Bit 2 M Div2 bit (5:) RW frequency formulas. Bit M Div RW Bit M Div RW 4

15 SMBUS Table: SB_SRC Frequency Control Register Byte 3 Name Control Function Type Default Bit 7 N Div RW Bit 6 N Div9 RW Bit 5 N Div8 RW The decimal representation of M and N Divider in Byte 29 and Bit 4 N Div7 N Divider Programming Byte2 RW 3 will configure the VCO frequency. Default at power up = Bit 3 N Div6 bit(7:) and Byte9 bit(7:6) RW Byte 6 Rom table. See M/N Caculation Tables for VCO Bit 2 N Div5 RW frequency formulas. Bit N Div4 RW Bit N Div3 RW SMBUS Table: SB_SRC Output Divider Control Register Byte 3 Name Control Function Type Default Bit 7 SB_SRC NDiv LSB N Divider Programming RW N Divider LSB (bit ) for SRC M/N programming. Bit 6 Bit 5 Bit 4 Bit 3 SB_SRCDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 SB_SRCDiv2 SB_SRC Divider Ratio RW :/3 ; :/6 :/2 ; :/24 Bit SB_SRCDiv Programming Bits RW :/5 ; :/ :/2 ; :/4 Bit SB_SRCDiv RW :/9 ; :/8 :/36 ; :/72 Bytes 32-4 are reserved SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 4 Name Control Function Type Default Bit 7 SSP7 RW Bit 6 SSP6 RW Bit 5 SSP5 RW Bit 4 SSP4 Spread Spectrum Programming RW These bits set the ATIG spread pecentage.please contact IDT Bit 3 SSP3 b(7:) RW for the appropriate values. Bit 2 SSP2 RW Bit SSP RW Bit SSP RW SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 42 Name Control Function Type Default Bit 7 SSP5 RW Bit 6 SSP4 RW Bit 5 SSP3 RW Bit 4 SSP2 Spread Spectrum Programming RW These bits set the ATIG spread pecentage.please contact IDT Bit 3 SSP b(5:8) RW for the appropriate values. Bit 2 SSP RW Bit SSP9 RW Bit SSP8 RW 5

16 Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes 3.3V Core Supply Voltage VDDxxx GND + 3.9V V Storage Temperature Ts C Ambient Operating Temp Tambient - 7 C Case Temperature Tcase - 5 C Input ESD protection HBM ESD prot - 2 V Guaranteed by design and characterization, not % tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS Notes 3.3V Core Supply Voltage VDDxxx V Input High Voltage V IH VDD = 3.3 V +/-5% 2 V DD +.3 V Input Low Voltage V IL VDD = 3.3 V +/-5% V SS V Input High Current I IH V IN = V DD -5 5 ua Input Low Current V I IN = V; Inputs with no pull-up IL resistors -5 ua V I IN = V; Inputs with pull-up IL2 resistors -2 ua Low Threshold Input- High Voltage V IH_FS VDD = 3.3 V +/-5%.7 V DD +.3 V Low Threshold Input- Low Voltage V IL_FS VDD = 3.3 V +/-5% V SS V Operating Current I DD3.3OP all outputs driven 225 ma Powerdown Current I DD3.3PD all diff pairs low/low 2 ma Input Frequency F i VDD = 3.3 V +/-5% MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C OUT Output pin capacitance 6 pf C IN & 2 pins 5 pf From VDD Power-Up or deassertion of PD to st clock Clk Stabilization T STAB.8 ms Modulation Frequency Triangular Modulation 3 33 khz Tdrive_PD CPU output enable after PD de-assertion 3 us Tfall_PD PD fall time of 5 ns Trise_PD PD rise time of 5 ns SMBus Voltage V DDSMB V Low-level Output Voltage V I PULLUP.4 V Current sinking at V OL =.4 V I PULLUPSMB 4 6 ma SMBCLK/SMBDAT (Max VIL -.5) to T Clock/Data Rise Time RSMB (Min VIH +.5) ns SMBCLK/SMBDAT (Min VIH +.5) to T Clock/Data Fall Time FSMB (Max VIL -.5) 3 ns *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 4.388MHz to meet ppm frequency accuracy on PLL outputs. 6

17 AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Crossing Point Variation ΔV CROSS Single-ended Measurement 4 mv,2,5 Frequency f Spread Specturm On MHz,3 Long Term Accuracy ppm Spread Specturm Off ppm, Rising Edge Slew Rate S RISE Differential Measurement.5 V/ns,4 Falling Edge Slew Rate S FALL Differential Measurement.5 V/ns,4 Slew Rate Variation t SLVAR Single-ended Measurement 2 % CPU, DIF HTT Jitter - Cycle to Cycle CPUJ C2C Differential Measurement 5 ps,6 Accumulated Jitter t JACC See Notes ns,7 Peak to Peak Differential Voltage V D(PK-PK) Differential Measurement 4 24 mv,8 Differential Voltage V D Differential Measurement 2 2 mv,9 Duty Cycle D CYC Differential Measurement % Amplitude Variation ΔV D Change in V D DC cycle to cycle mv, CPU[:] Skew CPU SKEW Differential Measurement ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2pF with Rs = Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 Single-ended measurement at crossing point. Value is maximum minimum over all time. DC value of common mode is not important due to the blocking cap. 3 Minimum Frequency is a result of.5% down spread spectrum 4 Differential measurement through the range of ± mv, differential signal must remain monotonic and within slew rate spec when crossing through this region. 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 Max difference of t CYCLE between any two adjacent cycles. 7 Accumulated tjc.over a µs time period, measured with JIT2 TIE at 5ps interval. 8 VD(PK-PK) is the overall magnitude of the differential signal. 9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross V VD. VD(max) is the largest amplitude allowed. The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the signal. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 7

18 AC Electrical Characteristics - Low-Power DIF Outputs: SRC, SB_SRC, ATIG PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Rising Edge Slew Rate t SLR Differential Measurement.6 4 V/ns,2 Falling Edge Slew Rate t FLR Differential Measurement.6 4 V/ns,2 Slew Rate Variation t SLVAR Single-ended Measurement 2 % Maximum Output Voltage V HIGH Includes overshoot 5 mv Minimum Output Voltage V LOW Includes undershoot -3 mv Differential Voltage Swing V SWING Differential Measurement 3 mv Crossing Point Voltage V ABS Single-ended Measurement 3 55 mv,3,4 Crossing Point Variation V ABSVAR Single-ended Measurement 4 mv,3,5 Duty Cycle D CYC Differential Measurement % SRC, SB_SRC, ATIG, Jitter - Cycle to Cycle SRCJ C2C Differential Measurement 25 ps SRC[5:] Skew SRC SKEW Differential Measurement 25 ps SB_SRC[:] Skew SRC SKEW Differential Measurement ps ATIG[3:] Skew SRC SKEW Differential Measurement ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2pF with Rs = Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz Electrical Characteristics - Single-Ended HTT 66MHz Clock PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 PCI33 Clock period HTT66 Clock period 33.33MHz output nominal ns MHz output spread ns MHz output nominal ns MHz output spread ns 2 Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current Output Low Current T period T period I OH I OL V =. V -33 ma V MA = 3.35 V -33 ma V MIN =.95 V 3 ma V MA =.4 V 38 ma Edge Rate. V. t Rising edge rate 4 V/ns Edge Rate. V. t Falling edge rate 4 V/ns Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V % Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 8 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5pF with Rs = 33Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 4.388MHz 8

19 Electrical Characteristics - USB - 48MHz PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Long Accuracy ppm see Tperiod min-max values - ppm,2 Clock period T period 48.MHz output nominal ns 2 Clock Low Time T low Measure from <.6V ns 2 Clock High Time T high Measure from > 2.V ns 2 Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current Output Low Current I OH I OL V =. V -33 ma V = 3.35 V -33 ma V MIN =.95 V 3 ma V MA =.4 V 38 ma Rise Time t r_usb V OL =.4 V, V OH = 2.4 V.5.5 ns Fall Time t f_usb V OH = 2.4 V, V OL =.4 V.5.5 ns Duty Cycle d t V T =.5 V % Group Skew t skew V T =.5 V 25 ps Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 3 ps,2 *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5pF with Rs = 33Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification Electrical Characteristics - REF-4.38MHz PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 Clock period T period 4.38MHz output nominal ns 2 Clock Low Time T low Measure from <.6V ns 2 Clock High Time T high Measure from > 2.V ns 2 Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V V =. V, Output High Current I OH V = 3.35 V ma V =.95 V, Output Low Current I OL V =.4 V ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 ns Skew t sk V T =.5 V 25 ps Duty Cycle d t V T =.5 V % Jitter t jcyc-cyc V T =.5 V 2 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5pF with Rs = 33Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 9

20 Clock Jitter Specifications - Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES t jphasepll PCIe Gen 86 SRC/SB_SRC/ATIG PCIe Gen 2 t Phase Jitter jphaselo khz < f <.5MHz 3 PCIe Gen 2 t jphasehigh.5mhz < f < Nyquist (5MHz) 3. *TA = - 7 C; Supply Voltage VDD = 3.3V +/-5%, Rs = ohms, CL = 2pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. ps (pp) ps (RMS) ps (RMS),2,4,4 2 JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece 3 Phase jitter requirement: The deisgnated Gen2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a componnet test board under quiet condittions with all outputs on. 4 See for complete specs Marking Diagram ICS 9LPRS47CKL LOT COO YYWW Notes:. L denotes RoHS compliance. 2. LOT denotes the lot number. 3. COO denotes country of origin. 4. YYWW denotes the assembly date code. 2

21 Index Area E N Top View Seating Plane Anvil Singulation OR A Sawn Singulation A3 E2 L E2 2 (N D - )x e (Ref. ) N (Ref. ) N D & N E Even e (Typ.) 2 If N D & are Even 2 (N E - )x e (Ref. ) b N E D Chamfer 4x.6 x.6 max OPTIONAL.8 C A C e (Ref.) N D & N E Odd D2 D2 2 Thermal Base THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS OPTION DIMENSIONS (mm) OPTION 2 DIMENSIONS (mm) SYMBOL MIN. MA. SYMBOL MIN. MA. SYMBOL 64L A.8. A.8. N 64 A.5 A.5 N D 6 A3.25 Reference A3.25 Reference N E 6 b.8.3 b.8.3 e.5 BASIC e.5 BASIC D x E BASIC 9. x 9. D x E BASIC 9. x 9. D2 MIN. / MA D2 MIN. / MA E2 MIN. / MA E2 MIN. / MA L MIN. / MA..3.5 L MIN. / MA..3.5 Ordering Information 9LPRS47CKLFT *Due to package size constraints actual top side marking may differ from the full orderable part number. Example: C K LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type 2

22 Programmable System Clock Chip for ATI RS79 - K8 TM based Systems Revision History Rev. Issue Date Description Page #. /2/27 Initial Release -.2 3/2/28 Added IO_Vout select table 7.3 4/8/28. Updated MLF Ordering Information. 2. Reformatted Dimensions Tables 2.4 Fixed typo in Electrical Specifications.5 9/6/29 Updated Power Group Table /5/2 Updated electrical tables; updated document template Various.7 2/9/2 Corrected RESTORE# pin description 3.8 5/23/22 Added marking diagram/notes. 2 Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 22