46 VDDCORE_1.5V 45 GNDCORE_1.5V 44 CPUT_L0_CPU 43 CPUC_L0_CPU 42 CPUT_L1F_NB 41 CPUC_L1F_NB 40 VDDCPU_1.5V 9UM709B/BI

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1 DATASHEET Ultra Low Power Programmable Main Clock for VIA VX9 Chipset ICS9UM79B Recommended Application: Ultra low power main clock for VIA VX9 chipset Output Features: pairs.7v differential pushpull CPU outputs pairs.7v differential pushpull PCIEX outputs pair.7v differential pushpull MCLK output pair.7v differential pushpull CPU/PCIEX selectable output SATA MHz singleended.v output USB 8MHz singleended.v output AGP.MHz singleended.v outputs GFX 7MHz singleended.v outputs PCI.MHz singleended.v outputs REF.88MHz singleended.v outputs Pin Configuration Features/Benefits: Supports programmable spread percentage and frequency Uses external.8mhz crystal, external crystal load caps are required for frequency tuning Low power differential clock outputs (No Ω resistor to GND needed) Programmable output skew Programmable watchdog safe frequency Integrated ohm series resistor on all differential outputs Low power supply voltage support for differential outputs Meets PCIEX Gen specifications Uses.V core voltage for ultra low power design Output programmable slew rate controls Key Specifications: CPU output cyclecycle jitter < 8ps PCIEX output cyclecycle jitter < ps +/ ppm frequency accuracy for all output clocks CPUAGP skew ~.ns typical AGPPCIA skew ~.ns typical AGPPCIB skew ~.ns typical CPUPCIA skew ~.ns typical CPUPCIB skew ~.ns typical FSLA/REF VDDREF_.V X X GNDREF GNDPCI FSLB/PCICLKA_F_NB 7 PCICLKB_X 8 *CPU_STOP#/PCICLKB_X 9 VDDPCI_.V VDDV_.V FSLC/VCLK GNDV VDD8_.V **SEL_ITP/8MHz_ 8MHz F/PEREQ#* GND8 7 GND7 8 **N_MODE/7MHz_DP_X 9 VDD7_.V GNDSATA SATA_M_.V VDDSATA_.V *RESET_IN#/RESET_OUT#/PEREQ# 9UM79B/BI 8 SCLK 7 SDATA VDDCORE_.V GNDCORE_.V CPUT_L_CPU CPUC_L_CPU CPUT_LF_NB CPUC_LF_NB VDDCPU_.V 9 GNDCPU 8 VDDCORE_.V 7 PCIeT_L_G/CPU_ITPT PCIeC_L_G/CPU_ITPC PCIeT_L_G PCIeC_L_G PCIeT_L_G PCIeC_L_G VDDPCIEX_.V GNDPCIEX 9 VDDA_SATA_.V 8 PCIeT_L_G 7 PCIeC_L_G PCIeT_L_G PCIeC_L_G 8TSSOP * Internal PullUp Resistor ** Internal PullDown Resistor IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

2 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Pin Description PIN # PIN NAME TYPE DESCRIPTION FSLA/REF I/O.V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values / Fixed.V singleended.8 MHz reference clock. VDDREF_.V PWR Ref, crystal power supply, nominal.v. X IN Crystal input, nominally.8mhz. X OUT Crystal output, nominally.8mhz. GNDREF PWR Ground pin for reference clock output. GNDPCI PWR Ground pin for PCI outputs. 7 FSLB/PCICLKA_F_NB I/O.V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values /.V freerunning.mhz PCI clock output for North Bridge. 8 PCICLKB_X OUT.V singleended.mhz PCI clock output default at x drive. 9 *CPU_STOP#/PCICLKB_X I/O Stops all CPU clocks at logic level when low, except those set to be freerunning clocks /.V singleended.mhz PCI clock output default at x drive. VDDPCI_.V PWR Power supply pin for PCI outputs, nominal.v. VDDV_.V PWR Power supply pin for V outputs, nominal.v. FSLC/VCLK I/O.V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values / Fixed singleended V. GNDV PWR Ground pin for V outputs. VDD8_.V PWR Ground pin for 8MHz outputs. **SEL_ITP/8MHz_ I/O ITP_EN: latched input to select pin functionality (default) = PCIEX pair, = CPU_ITP pair /.V singleended 8MHz output. 8MHz F/PEREQ#* I/O.V singleended 8MHz output / Realtime input pin that controls PCIEX or PCIEX outputs that are selected through the IC. = disabled, = enabled. 7 GND8 PWR Ground pin for 8MHz outputs. 8 GND7 PWR Ground pin for 7MHz outputs. 9 **N_MODE/7MHz_DP_X I/O Input latch pin to select chip to operate in Desktop or Notebook mode. (default) = Notebook, =Desktop /.V singleended 7MHz output, default at x drive. VDD7_.V PWR Power supply pin for 7M outputs, nominal.v. GNDSATA PWR Ground pin for singleended.v SATACLK. SATA_M_.V OUT.V singleended.v MHz SATACLK. VDDSATA_.V PWR Power supply pin for singleended.v SATACLK, nominal.v. *RESET_IN#/RESET_OUT#/PEREQ# I/O Real time active low input. When active, SMBus is reset to power up default / Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low / Realtime input pin that controls PCIEX or PCIEX outputs that are selected through the IC. = disabled, = enabled. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

3 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Pin Description (continued) PIN # PIN NAME TYPE DESCRIPTION PCIeC_L_G OUT Complement clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. PCIeT_L_G OUT True clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. 7 PCIeC_L_G OUT Complement clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. 8 PCIeT_L_G OUT True clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. 9 VDDA_SATA_.V PWR Analog power supply for SATA PLL, typically.v. GNDPCIEX PWR Ground pin for PCIEX outputs. VDDPCIEX_.V PWR Low voltage power supply pin for differential PCIEX outputs, nominal.v. PCIeC_L_G OUT Complement clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. PCIeT_L_G OUT True clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. PCIeC_L_G OUT Complement clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. PCIeT_L_G OUT True clock of.7v differential pushpull PCI_Express pair with integrated ohm series resistor. No ohm resistor to GND needed. PCIeC_L_G/CPU_ITPC OUT Complementary clock of differential pair.7v pushpull CPU or PCIEX Gen output with integrated ohm series resistor. No ohm resistor to GND needed. 7 PCIeT_L_G/CPU_ITPT OUT True clock of differential pair.8v pushpull CPU or PCIEX Gen output with integrated ohm series resistor. No ohm resistor to GND needed. 8 VDDCORE_.V PWR Power supply pin for core PLL, nominal.v. 9 GNDCPU PWR Ground pin for CPU outputs. VDDCPU_.V PWR Low voltage power supply pin for differential CPU outputs, nominal.v. CPUC_LF_NB OUT Complement clock of.7v differential pushpull CPU output for NorthBridge with integrated ohm series resistor. No ohm resistor to GND needed. CPUT_LF_NB OUT True clock of.7v differential pushpull CPU output for NorthBridge with integrated ohm series resistor. No ohm resistor to GND needed. CPUC_L_CPU OUT Complement clock of.7v differential pushpull CPU output with integrated ohm series CPUT_L_CPU OUT resistor. No ohm resistor to GND needed. True clock of.7v differential pushpull CPU output with integrated ohm series resistor. No ohm resistor to GND needed. GNDCORE_.V PWR Ground pin for low voltage core PLL. VDDCORE_.V PWR Power supply pin for low voltage core PLL, nominal.v. 7 SDATA I/O Data pin for SMBus circuitry,.v tolerant. 8 SCLK IN Clock pin of SMBus circuitry,.v tolerant. Power Distribution Table: VDD Pin# GND pin# VDD Connection Description REF clock output PCI clock output V clock output 7 8M clock output; 8M PLL analog 8 7M clock output; 7M PLL analog SATA clock output 9 SATA PLL analog SRC clock output; PCIEX PLL analog 8 V core circuit 8 PCI core circuit 9 CPU clock output All PLL digital; Crystal; REF core IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

4 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset General Description ICS9UM79B is a ultra low power main clock for VIA VX9 chipset. ICS9UM79B is driven with a.8mhz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCIExpress support. Block Diagram Fixed PLL Frequenc y Dividers SATA 8M [:] V 7M PCI[:] X X XTAL REF SCLK SDATA FSLC:A NMode ITPEN PEREQ: Control Logic PLL Array Programmable Frequency Divider Array STOP Logic CPUT_LR[:] CPUC_LR[:] PCIEXT_LR[:] PCIEXC_LR[:] CPUT_ITP/PCIEXT_LR CPUC_ITP/PCIEXC_LR CPU_STOP# RESET_IN# RESET_OUT# Transmission lines to load do not share series resistors. Desktop (Zo=Ω) and mobile (Zo=Ω) have the same drive strength. D.C.Drive Strength Number of Loads to Drive Match Point for N & P Voltage / Current (ma). / (7Ω).9 / (Ω). / 99 (.Ω) Number of Loads Actually Driven. Load Rs = Loads Rs= Loads Rs = Ω [9Ω] 9Ω [Ω] Ω [7Ω] Ω [Ω] 7Ω [Ω] Ω [Ω] IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

5 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset CPU PLL Table: Frequency Selection Table Bb Bb Bb Bb Bb CPU V PCI Spread FS FS FSLC FSLB FSLA MHz MHz MHz %....% Down....% Down....% Down....% Down Reserved....% Down Reserved Reserved... +/.% Center... +/.% Center... +/.% Center... +/.% Center Reserved... +/.% Center Reserved Reserved % Down. 7...% Down. 7...% Down % Down Reserved. 7...% Down Reserved Reserved % Down % Down % Down % Down Reserved % Down Reserved Reserved IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

6 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset PCIEX PLL Table: Frequency Selection Table B9b B9b B9b B9b B9b PCIEX V PCI SATA Spread FS FS FSLC FSLB FSLA MHz MHz MHz MHz %.....% Down.....% Down.....% Down.....% Down.....% Down.....% Down.....% Down.....% Down.... +/.% Center.... +/.% Center.... +/.% Center.... +/.% Center.... +/.% Center.... +/.% Center.... +/.% Center.... +/.% Center % Down % Down % Down % Down % Down % Down % Down % Down % Down % Down % Down % Down % Down % Down % Down % Down IO_Vout Selection Table b b b IO_Vout.V.V.V.V.7V.8V.9V.V *Bold is default IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

7 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset PowerUp Sequence Requirement Differential Power Management Table CPU_STOP# PEREQ# CPU[:]T/C CPU_ITPT/C (SEL_ITP=) SMBus CPU CPU CPU CPU Register OE Stoppable FreeRunning Stoppable FreeRunning X Running/Running Running/Running Running/Running Running/Running X High/Low Running/Running High/Low Running/Running X X Disable Low/Low Low/Low Low/Low Low/Low CPU_STOP# PEREQ# PCIEX[,,,]T/C PCIEXT/C SMBus PEREQ# PEREQ# Register OE Controlled Not Controlled X Running/Running Running/Running Running/Running X Low/Low Running/Running Running/Running X X Disable Low/Low Low/Low Low/Low SingledEnded Power Management Table CPU_STOP# PEREQ# SMBus PCI[:] REF 7M 8M[:] V SATA Register OE X X Running Running Running Running Running Running X X Disable Low Low Low Low Low Low PEREQ# Control Table: PEREQ# PCIEX,, IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/ 7

8 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Commercial Temperature Specifications Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes.V Logic Input Supply Voltage VDD_In Logic Supply GND. V DD +.V V,,.V Supply Voltage VDD_. Core Supply GND. V DD +.V V,.V Supply Voltage VDDx_. Low Voltage Differential Core/Logic Supply GND. V DD +.V V, VDDIO Supply Voltage VDDx_IO Low Voltage Differential I/O Supply GND. V DD +.V V, Storage Temperature Ts C, Case Temperature Tcase C, Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Operation under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD Electrical Characteristics Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Ambient Operating Temp Tambient 7 C.V Supply Voltage VDDxxx_..V +/ %.. V.V Supply Voltage VDDxxx_..V +/ %..7 V.V Input High Voltage V IHSE. V DDxx_. +. V,.V Input Low Voltage V ILSE. V SS..8 V,.V referenced inputs are: SCLK, SDATA, CPU_STOP#, SEL_ITP, N_MODE, RESET_IN# and PEREQ/. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/ 8 V DDxxx_..V Input High Voltage V IHSE V.V Input Low Voltage V ILSE. V SS.. V Low Threshold Input High Voltage V IH_FS_.. V +/%.7 V DD +. V Low Threshold Input Low Voltage V IL_FS_.. V +/% V SS.. V Input Leakage Current I IN V IN = V DD, V IN = GND ua, Input Leakage Current I INRES resistors ua Inputs with pull or pull down V IN = V DD, V IN = GND Output High Voltage V OHSE Singleended outputs, I OH = ma. V, Output Low Voltage V OLSE Singleended outputs, I OL = ma. V, I DD.OP 9 ma Operating Current I DD.OP All outputs driven, Full Active 8 ma I DDIO_.OP ma Input Frequency F i V DD =. V MHz Pin Inductance L pin 7 nh C IN Logic Inputs. pf Input Capacitance C OUT Output pin capacitance pf C INX X & X pins pf Spread Spectrum Modulation Frequency f SSMOD Triangular Modulation khz *TA = 7 C; Supply Voltage VDD =.V/.V +/% Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Signal is required to be monotonic in this region. Input leakage current does not include inputs with pullup or pulldown resistors

9 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics SMBus Interface PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes SMBus Voltage V DD.7. V Lowlevel Output Voltage V I PULLUP. V Current sinking at V OLSMB =. V I PULLUP SMB Data Pin ma SCLK/SDATA (Max VIL.) to T RIC Clock/Data Rise Time (Min VIH +.) ns SCLK/SDATA (Min VIH +.) to T FIC Clock/Data Fall Time (Max VIL.) ns Maximum SMBus Operating Frequency F SMBUS Block Mode khz Unless otherwise noted, guaranteed by design and characterization, not % tested in production. AC Electrical Characteristics Input/Common Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes From 7% VDD (VDD., VDD., Clk Stabilization T STAB VDDIO) to clock output. ms CPU output enable after Tdrive_CPU T DRSRC CPU_STOP# deassertion ns Tfall_PD# T FALL Fall/Rise time of CPU_STOP# ns Trise_PD# T RISE inputs ns Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Electrical Characteristics AGPMHz (V) Clock Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, Jitter, Cycle to cycle t jcyccyc V T =. V 7 ps, t CPUAGP skew V T =. V. ns, Group to Group Skew t AGPPCIA skew V T =. V. ns, t AGPPCIB skew V T =. V. ns, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/ 9

10 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset AC Electrical Characteristics CPUCLK (.7V PushPull) Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm Rising Edge Slew Rate t SLR Differential Measurement. 8 V/ns,, Falling Edge Slew Rate t FLR Differential Measurement. 8 V/ns,, Slew Rate Variation t SLVAR Singleended Measurement %,,7 Average Maximum Output Voltage V HIGHTYP Average High 8 mv, Average Minimum Output Voltage V LOWTYP Average Low mv, Maximum Output Voltage V HIGH Includes overshoot mv,,8 Minimum Output Voltage V LOW Includes undershoot mv,,9 Differential Voltage Swing V SWING Differential Measurement mv, Crossing Point Voltage V XABS Singleended Measurement mv,,, Crossing Point Variation V XABSVAR Singleended Measurement mv,,, Duty Cycle D CYC Differential Measurement %, CPU[:] Skew t CPU skew Singleended Measurement ps, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Measurement taken for single ended waveform on a component test board (not in system) Measurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) Only applies to the differential rising edge (Clock rising, Clock# falling) 7 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/7mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage. 8 The max voltage including overshoot. 9 The min voltage including undershoot. The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

11 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset AC Electrical Characteristics PCIEX (.7V PushPull) Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm Rising Edge Slew Rate t SLR Differential Measurement. V/ns,, Falling Edge Slew Rate t FLR Differential Measurement. V/ns,, Slew Rate Variation t SLVAR Singleended Measurement %,,7 Average Maximum Output Voltage V HIGHTYP Average High 8 mv, Average Minimum Output Voltage V LOWTYP Average Low mv, Maximum Output Voltage V HIGH Includes overshoot mv,,8 Minimum Output Voltage V LOW Includes undershoot mv,,9 Differential Voltage Swing V SWING Differential Measurement mv, Crossing Point Voltage V XABS Singleended Measurement mv,,, Crossing Point Variation V XABSVAR Singleended Measurement mv,,, Duty Cycle D CYC Differential Measurement %, PCIEX[:] Skew t PCIEX skew Singleended Measurement ps, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Measurement taken for single ended waveform on a component test board (not in system) Measurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) Only applies to the differential rising edge (Clock rising, Clock# falling) 7 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/7mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage. 8 The max voltage including overshoot. 9 The min voltage including undershoot. The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

12 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics PCICLK Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, PCI[B:A] Skew t skew V T =. V ps, Jitter, Cycle to cycle t jcyccyc V T =. V ps, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=ohm (for PCICLKA), Rs=9ohm (for PCICLKB), CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. Electrical Characteristics 8M Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period 8.MHz output nominal.8.8 ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Risetime t R V OH=.V, V OL=.8V.. ns, Falltime t F V OH=.V, V OL=.8V.. ns, Duty Cycle d t V T =. V %, Jitter, Cycle to cycle t jcyccyc V T =. V ps, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

13 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics 7MHz GFX Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period 7.MHz output nominal ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current Output Low Current I OH I OL V =. V 9 ma V OH@MAX =. V ma V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, Jitter t ltj Long Term (us), V T =. V ps, t jcyccyc Cycle to Cycle, V T =. V ps, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=9ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. Electrical Characteristics REF.8MHz PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period.8mhz output nominal ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V V =. V, Output High Current I OH V OH@MAX =. V ma V =.9 V, Output Low Current I OL V =. V 8 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, Jitter, Cycle to cycle t jcyccyc V T =. V ps, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

14 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics MHz SATA Clock Output PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period.mhz output nominal ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma, V MAX =. V 7 ma, Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Duty Cycle d t V T =. V %, Cycle to Cycle, V T =. V, t jcyccyc source from PCIEX spread PLL 7 ps, Jitter Long Term (us), V T =. V, t ltj source from SATA nonspread PLL ps, *TA = 7 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. Clock Jitter Specifications Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES CPU Jitter Cycle to Cycle CPUJ CC Differential Measurement 8 ps, PCIEX Jitter Cycle to Cycle SRCJ CC Differential Measurement ps, t jphasepll PCIe Gen 8 ps (pp), PCIEX Phase Jitter PCIe Gen t jphaselo khz < f <.MHz. ps (RMS),, PCIe Gen t jphasehigh.mhz < f < Nyquist (MHz). ps (RMS),, *TA = 7 C; Supply Voltage VDD =.V +/ %, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the insystem performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured in a real system. Phase jitter requirement: The designated Gen outputs will meet the reference clock jitter requiremernts from the PCI Express Gen Base Spec. The test is performed on a componnet test board under quiet condittions with all outputs on. See for complete specs IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

15 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Industrial Temperature Specifications Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes.V Logic Input Supply Voltage VDD_In Logic Supply GND. V DD +.V V,,.V Supply Voltage VDD_. Core Supply GND. V DD +.V V,.V Supply Voltage VDDx_. Low Voltage Differential Core/Logic Supply GND. V DD +.V V, Storage Temperature Ts C, Case Temperature Tcase C, Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Operation under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD Electrical Characteristics Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Ambient Operating Temp Tambient 8 C.V Supply Voltage VDDxxx_..V +/ %.. V.V Supply Voltage VDDxxx_..V +/ %..7 V.V Input High Voltage V IHSE. V DDxx_. +. V,.V Input Low Voltage V ILSE. V SS..8 V, IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/ V DDxxx_..V Input High Voltage V IHSE V.V Input Low Voltage V ILSE. V SS.. V Low Threshold Input High Voltage V IH_FS_.. V +/%.7 V DD +. V Low Threshold Input Low Voltage V IL_FS_.. V +/% V SS.. V Input Leakage Current I IN V IN = V DD, V IN = GND ua, Input Leakage Current I INRES resistors ua Inputs with pull or pull down V IN = V DD, V IN = GND Output High Voltage V OHSE Singleended outputs, I OH = ma. V, Output Low Voltage V OLSE Singleended outputs, I OL = ma. V, I DD.OP 9 ma Operating Current I DD.OP All outputs driven, Full Active 8 ma I DDIO_.OP ma Input Frequency F i V DD =. V MHz Pin Inductance L pin 7 nh C IN Logic Inputs. pf Input Capacitance C OUT Output pin capacitance pf C INX X & X pins pf Spread Spectrum Modulation Frequency f SSMOD Triangular Modulation khz *TA = C ~ 8 C; Supply Voltage VDD =.V/.V +/% Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Signal is required to be monotonic in this region. Input leakage current does not include inputs with pullup or pulldown resistors.v referenced inputs are: SCLK, SDATA, CPU_STOP#, SEL_ITP, N_MODE, RESET_IN# and PEREQ/.

16 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics SMBus Interface PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes SMBus Voltage V DD.7. V Lowlevel Output Voltage V I PULLUP. V Current sinking at V OLSMB =. V I PULLUP SMB Data Pin ma SCLK/SDATA (Max VIL.) to T RIC Clock/Data Rise Time (Min VIH +.) ns SCLK/SDATA (Min VIH +.) to T FIC Clock/Data Fall Time (Max VIL.) ns Maximum SMBus Operating Frequency F SMBUS Block Mode khz Unless otherwise noted, guaranteed by design and characterization, not % tested in production. AC Electrical Characteristics Input/Common Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes From 7% VDD (VDD., VDD., Clk Stabilization T STAB VDDIO) to clock output. ms CPU output enable after Tdrive_CPU T DRSRC CPU_STOP# deassertion ns Tfall_PD# T FALL Fall/Rise time of CPU_STOP# ns Trise_PD# T RISE inputs ns Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Electrical Characteristics AGPMHz (V) Clock Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, Jitter, Cycle to cycle t jcyccyc V T =. V 7 ps, t CPUAGP skew V T =. V. ns, Group to Group Skew t AGPPCIA skew V T =. V. ns, t AGPPCIB skew V T =. V. ns, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

17 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset AC Electrical Characteristics CPUCLK (.7V PushPull) Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm Rising Edge Slew Rate t SLR Differential Measurement. 8 V/ns,, Falling Edge Slew Rate t FLR Differential Measurement. 8 V/ns,, Slew Rate Variation t SLVAR Singleended Measurement %,,7 Average Maximum Output Voltage V HIGHTYP Average High 8 mv, Average Minimum Output Voltage V LOWTYP Average Low mv, Maximum Output Voltage V HIGH Includes overshoot mv,,8 Minimum Output Voltage V LOW Includes undershoot mv,,9 Differential Voltage Swing V SWING Differential Measurement mv, Crossing Point Voltage V XABS Singleended Measurement mv,,, Crossing Point Variation V XABSVAR Singleended Measurement mv,,, Duty Cycle D CYC Differential Measurement %, CPU[:] Skew t CPU skew Singleended Measurement ps, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Measurement taken for single ended waveform on a component test board (not in system) Measurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) Only applies to the differential rising edge (Clock rising, Clock# falling) 7 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/7mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage. 8 The max voltage including overshoot. 9 The min voltage including undershoot. The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/ 7

18 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset AC Electrical Characteristics PCIEX (.7V PushPull) Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm Rising Edge Slew Rate t SLR Differential Measurement. V/ns,, Falling Edge Slew Rate t FLR Differential Measurement. V/ns,, Slew Rate Variation t SLVAR Singleended Measurement %,,7 Average Maximum Output Voltage V HIGHTYP Average High 8 mv, Average Minimum Output Voltage V LOWTYP Average Low mv, Maximum Output Voltage V HIGH Includes overshoot mv,,8 Minimum Output Voltage V LOW Includes undershoot mv,,9 Differential Voltage Swing V SWING Differential Measurement mv, Crossing Point Voltage V XABS Singleended Measurement mv,,, Crossing Point Variation V XABSVAR Singleended Measurement mv,,, Duty Cycle D CYC Differential Measurement %, PCIEX[:] Skew t PCIEX skew Singleended Measurement ps, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. Measurement taken for single ended waveform on a component test board (not in system) Measurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) Only applies to the differential rising edge (Clock rising, Clock# falling) 7 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/7mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage. 8 The max voltage including overshoot. 9 The min voltage including undershoot. The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/ 8

19 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics PCICLK Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, PCI[B:A] Skew t skew V T =. V ps, Jitter, Cycle to cycle t jcyccyc V T =. V ps, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=ohm (for PCICLKA), Rs=9ohm (for PCICLKB), CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. Electrical Characteristics 8M Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period 8.MHz output nominal.8.8 ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Risetime t R V OH=.V, V OL=.8V.. ns, Falltime t F V OH=.V, V OL=.8V.. ns, Duty Cycle d t V T =. V %, Jitter, Cycle to cycle t jcyccyc V T =. V ps, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/ 9

20 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics 7MHz GFX Outputs PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period 7.MHz output nominal ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma V MAX =. V 7 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, Jitter t ltj Long Term (us), V T =. V ps, t jcyccyc Cycle to Cycle, V T =. V ps, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=9ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. Electrical Characteristics REF.8MHz PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period.8mhz output nominal ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V V =. V, Output High Current I OH V OH@MAX =. V ma V =.9 V, Output Low Current I OL V =. V 8 ma Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Rise Time t r Measured from.8 to. V.. ns, Fall Time t f Measured from. to.8 V.. ns, Duty Cycle d t V T =. V %, Jitter, Cycle to cycle t jcyccyc V T =. V ps, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

21 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset Electrical Characteristics MHz SATA Clock Output PARAMETER SYMBOL CONDITIONS MIN Typ MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm,, Clock period T period.mhz output nominal ns,, Output High Voltage V OH I OH = ma. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V =. V 9 ma V OH@MAX =. V ma Output Low Current I OL V MIN =.9 V 9 ma, V MAX =. V 7 ma, Rising Edge Slew Rate t SLR Measured from.8 to. V V/ns, Falling Edge Slew Rate t FLR Measured from. to.8 V V/ns, Duty Cycle d t V T =. V %, Cycle to Cycle, V T =. V, t jcyccyc source from PCIEX spread PLL 7 ps, Jitter Long Term (us), V T =. V, t ltj source from SATA nonspread PLL ps, *TA = C ~ 8 C; Supply Voltage VDD =. V +/%, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at.88mhz Edge rate in system is measured from.8v to.v. Duty cycle, Period, Skew and Jitter are measured with respect to.v The average period over any us period of time Using frequency counter with the measurment interval equal or greater that.s. Target frequencies are.88 MHz, 7.MHz,.MHz, 8.MHz,.MHz and.mhz. Clock Jitter Specifications Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES CPU Jitter Cycle to Cycle CPUJ CC Differential Measurement 8 ps, PCIEX Jitter Cycle to Cycle SRCJ CC Differential Measurement ps, t jphasepll PCIe Gen 8 ps (pp), PCIEX Phase Jitter PCIe Gen t jphaselo khz < f <.MHz. ps (RMS),, PCIe Gen t jphasehigh.mhz < f < Nyquist (MHz). ps (RMS),, *TA = C ~ 8 C; Supply Voltage VDD =.V +/ %, Rs=ohm, CL=pF Unless otherwise noted, guaranteed by design and characterization, not % tested in production. JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the insystem performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured in a real system. Phase jitter requirement: The designated Gen outputs will meet the reference clock jitter requiremernts from the PCI Express Gen Base Spec. The test is performed on a componnet test board under quiet condittions with all outputs on. See for complete specs IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

22 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset General SMBus serial interface information for the ICS9UM79B How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X ICS clock sends Byte through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit T Index Block Write Operation Controller (Host) ICS (Slave/Receiver) start bit Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N ACK ACK ACK ACK Slave Address D (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D (H) RD ReaD ACK ACK ACK Byte N + X P stop bit X Byte ACK ACK ACK X Byte Data Byte Count = X Beginning Byte N N P Not acknowledge stop bit Byte N + X IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

23 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset SMBUS Table: CPU PLL Frequency Select Register Byte Name Control Function Type Bit 7 ROD Reset On Demand RW Disable Bit SS_EN PCIEX PLL Spread RW OFF ON Bit SS_EN CPU PLL Spread RW OFF ON Bit FS Freq Select Bit RW Bit FS Freq Select Bit RW See Table : CPU PLL Frequency Selection Bit FSLC Freq Select Bit RW Latch Table Bit FSLB Freq Select Bit RW Latch Bit FSLA Freq Select Bit RW Latch SMBUS Table: Input Select Control Register Byte Name Control Function Type Bit 7 Reserved Reserved RW Bit Reserved Reserved RW Bit CPU PLL MNEN CPU PLL M/N RW Disable Bit Reserved Reserved RW Bit PCIEX PLL MNEN PCIEX PLL M/N RW Disable Bit RESET_EN RESET pin enable bit (enables pin to be active) RW Disable Bit **ITPEN Select CPUITP or PCIEX R PCIEX CPUITP Latch Bit **NMode Select Desktop or Mobile Mode R Mobile Desktop Latch * Default powerup state of Pin is PEREQ#, following Byte bit SMBUS Table: Output Control Register Byte Name Control Function Type Bit 7 REF Output Control RW Disable Bit 8M_ Output Control RW Disable Bit 8M_ Output Control RW Disable Bit 7M_DP Output Control RW Disable Bit AGP_V Output Control RW Disable Bit PCICLKA Output Control RW Disable Bit PCICLKB Output Control RW Disable Bit PCICLKB Output Control RW Disable SMBUS Table: Output Control Register Byte Name Control Function Type Bit 7 SATA_M Output Control RW Disable Bit CPUCLK_ Output Control RW Disable Bit CPUCLK_ Output Control RW Disable Bit CPUCLK ITP Output Control RW Disable Bit PCIEXT/C Output Control RW Disable Bit PCIEXT/C Output Control RW Disable Bit PCIEXT/C Output Control RW Disable Bit PCIEXT/C Output Control RW Disable IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/

24 ICS9UM79B Ultra Low Power Programmable Main Clock for VIA VX9 Chipset SMBUS Table: Output Control Register Byte Name Control Function Bit 7 PCIEXT/C Output Control RW Disable Bit PCICLKA PCICLKA Strength Control RW x x Bit PCICLKB PCICLKB Strength Control RW x x Bit PCICLKB PCICLKB Strength Control RW x x Bit REF REF Strength Control RW x x Bit 8M_ 8M_ Strength Control RW x x Bit 8M_ 8M_ Strength Control RW x x Bit 7M_DP 7M_DP Strength Control RW x x SMBUS Table: Output Control Register Byte Name Control Function Type Bit 7 AGP_V V Strength Control RW x x Bit SATA_M SATA Strength Control RW x x Bit CPU_SR CPU Group Programmable Slew Rate Control RW =.V/ns = V/ns Bit CPUCLK_ Free running control (during CPU_STOP#) RW Freerunning Stoppable Bit CPUCLK_ Free running control (during CPU_STOP#) RW Freerunning Stoppable Bit CPUCLK ITP Free running control (during CPU_STOP#) RW Freerunning Stoppable Bit PCIEX_SR PCIEX Group Programmable Slew Rate Control RW =.V/ns = V/ns Bit Load Control IIC Load control/ram read back Load/ RB from Active Do not Load/ RB from RW select RAM Shadow RAM SMBUS Table: Output Control Register Byte Name Control Function Type CPU IO Output Voltage Select Bit 7 CPU IO_VOUT RW (Most Significant Bit) See Table : V_IO Selection Bit CPU IO_VOUT CPU IO Output Voltage Select RW (Default is.7v) CPU IO Output Voltage Select Bit CPU IO_VOUT RW (Least Significant Bit) Bit PCIEX IO_VOUT PCIEX IO Output Voltage Select (Most Significant Bit) RW Bit PCIEX IO_VOUT PCIEX IO Output Voltage Select RW See Table : V_IO Selection (Default is.7v) Bit PCIEX IO_VOUT PCIEX IO Output Voltage Select (Least Significant Bit) RW Bit PEREQ# Control PCIEX is controlled RW Not Controlled Controlled Bit PEREQ# Control PCIEX is controlled RW Not Controlled Controlled IDT TM Ultra Low Power Programmable Main Clock for VIA VX9 Chipset /8/